CN219657712U - Chip test seat with high heat dissipation - Google Patents
Chip test seat with high heat dissipation Download PDFInfo
- Publication number
- CN219657712U CN219657712U CN202320768226.0U CN202320768226U CN219657712U CN 219657712 U CN219657712 U CN 219657712U CN 202320768226 U CN202320768226 U CN 202320768226U CN 219657712 U CN219657712 U CN 219657712U
- Authority
- CN
- China
- Prior art keywords
- diamond layer
- chip
- layer
- heat dissipation
- seat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 51
- 230000017525 heat dissipation Effects 0.000 title claims abstract description 21
- 229910003460 diamond Inorganic materials 0.000 claims abstract description 39
- 239000010432 diamond Substances 0.000 claims abstract description 39
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052802 copper Inorganic materials 0.000 claims abstract description 37
- 239000010949 copper Substances 0.000 claims abstract description 37
- 238000001179 sorption measurement Methods 0.000 claims abstract description 36
- 230000032683 aging Effects 0.000 claims abstract description 12
- 229910052737 gold Inorganic materials 0.000 claims description 11
- 239000010931 gold Substances 0.000 claims description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 8
- 239000011148 porous material Substances 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims 2
- 230000000694 effects Effects 0.000 abstract description 10
- 238000010521 absorption reaction Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 230000008859 change Effects 0.000 abstract description 2
- 230000002349 favourable effect Effects 0.000 abstract description 2
- 230000006872 improvement Effects 0.000 description 8
- 238000003466 welding Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0433—Sockets for IC's or transistors
- G01R1/0441—Details
- G01R1/0458—Details related to environmental aspects, e.g. temperature
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The utility model provides a chip test seat with high heat dissipation, which comprises a copper seat and a diamond layer, wherein the diamond layer is arranged in a chip aging test area of the copper seat, and the copper seat and the diamond layer are provided with through adsorption holes. According to the utility model, the heat dissipation effect is improved by arranging the diamond layer on the copper seat, and the adsorption holes are arranged to fix the test chip and increase the heat dissipation of the chip, so that the heat dissipation effect of the aging test seat is improved, and the chip is better protected to finish the aging test. The setting of various absorption holes can be to the fixed requirement of difference, realizes that better chip test is fixed to it is convenient to change, easy operation promotes the work efficiency of chip test, is favorable to automated production.
Description
Technical Field
The utility model belongs to the technical field of chip burn-in test equipment, and particularly relates to a chip test seat with high heat dissipation.
Background
The ultimate goal of the chip burn-in test is to predict the life of the product, evaluate or predict the durability of the product produced by the manufacturer; with the rapid growth of semiconductor technology and the increasing complexity of chips year by year, chip testing is increasingly challenging throughout the entire design development and production process, burn-in testing is an important test to eliminate early failure products prior to delivery to customers.
The aging test seat in the prior art adopts a copper seat, has poor heat dissipation performance and is easy to discard the tested chip; because the chip is placed on the copper seat during the test, the movement of the chip is easily caused in the test process, so that the problems of poor conductive connection and the like occur, the test result is inaccurate, the pressing or clamping structure is often required to be added, the installation and the replacement are inconvenient, and the test efficiency is affected.
Disclosure of Invention
The utility model provides a chip test seat with high heat dissipation, which can effectively solve the problems.
The utility model is realized in the following way:
the utility model provides a chip test seat of high heat dissipation, includes copper seat and diamond layer, the chip ageing test district of copper seat is located to the diamond layer, be equipped with the absorption hole that runs through on copper seat and the diamond layer.
As a further improvement, a welding layer is arranged between the diamond layer and the copper seat for connection, at least opposite surfaces of the copper seat and the diamond layer are plated with a gold layer, and the adsorption holes penetrate through the welding layer and the gold layer.
As a further improvement, a nano silver paste layer is arranged between the copper seat and the diamond layer, and the adsorption holes penetrate through the nano silver paste layer.
As a further improvement, the adsorption holes of the diamond layer are plated with a gold layer.
As a further improvement, the adsorption hole is arranged in the middle of the chip aging test area of the copper seat and the diamond layer.
As a further improvement, the pore diameter of the adsorption pores is 100-200 micrometers.
As a further improvement, the adsorption holes are arranged at four corners of the chip aging test area of the copper seat and the diamond layer.
As a further improvement, the adsorption holes are arranged on one or two pairs of opposite sides of the chip aging test areas of the copper seat and the diamond layer, and the adsorption holes are elongated or spaced holes.
The beneficial effects of the utility model are as follows: according to the utility model, the heat dissipation effect is improved by arranging the diamond layer on the copper seat, and the adsorption holes are arranged to fix the test chip and increase the heat dissipation of the chip, so that the heat dissipation effect of the aging test seat is improved, and the chip is better protected to finish the aging test. The setting of various absorption holes can be to the fixed requirement of difference, realizes that better chip test is fixed to it is convenient to change, easy operation promotes the work efficiency of chip test, is favorable to automated production.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some examples of the present utility model and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a chip test socket with high heat dissipation performance according to the present utility model;
FIG. 2 is a schematic diagram of a structure provided by an embodiment of the present utility model;
FIG. 3 is a schematic view of another embodiment of the present utility model;
FIG. 4 is a cross-sectional view provided by an embodiment of the present utility model;
FIG. 5 is a cross-sectional view of another embodiment of the present utility model;
fig. 6 is a cross-sectional view of another embodiment of the present utility model.
Reference numerals:
1-a copper base; a 2-diamond layer; 3-adsorption holes; 4-a welding layer; 5-gold layer; 6-nanometer silver paste layer.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments. All other embodiments, based on the embodiments of the utility model, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the utility model. Thus, the following detailed description of the embodiments of the utility model, as presented in the figures, is not intended to limit the scope of the utility model, as claimed, but is merely representative of selected embodiments of the utility model.
In the description of the present utility model, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present utility model, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present utility model, the terms "middle," "four corners," "opposite," "upper," and the like refer to an orientation or positional relationship based on that shown in the drawings, for convenience of description and simplicity of description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the utility model.
Referring to fig. 1-6, a chip test seat with high heat dissipation performance comprises a copper seat 1 and a diamond layer 2, wherein the diamond layer 2 is arranged in a chip burn-in test area of the copper seat 1, and the copper seat 1 and the diamond layer 2 are provided with through adsorption holes 3.
Through increasing diamond layer 2 and absorption hole 3, promote the radiating effect of test seat to conveniently fix the chip, accelerate the speed of getting of chip and putting in the chip test, promote work efficiency, just can accomplish the test of a chip in a few seconds. When a plurality of chip tests are required to be simultaneously carried out on the same test seat, a plurality of adsorption holes 3 can be arranged at intervals according to the size of the chip, and the adsorption fixing effect is realized on each chip. In use, the adsorption port 3 is connected to a suction device conduit, such as a vacuum pump.
Further, a welding layer 4 is arranged between the diamond layer 2 and the copper seat 1 for connection, at least opposite surfaces of the copper seat 1 and the diamond layer 2 are plated with a gold layer 5, and the adsorption holes 3 penetrate through the welding layer 4 and the gold layer 5. Because the thickness of the welding layer 4 is thicker and generally reaches 20-30 micrometers, the rapid heat dissipation of the diamond layer 2 and the copper seat 1 is not facilitated, and the adsorption holes 3 are arranged to take away heat in the adsorption process on one hand and adsorb a chip on the test seat on the other hand.
Further, a nano silver paste layer 6 is arranged between the copper seat 1 and the diamond layer 2, and the adsorption holes 3 penetrate through the nano silver paste layer 6. The nano silver paste layer 6 can further remove air between the copper seat 1 and the diamond layer 2, reduce thermal resistance, has quick heat dissipation effect and plays a role in fixation
Further, a gold layer 5 is plated in the adsorption hole 3 of the diamond layer 2. The gold layer 5 may form a conductive path in order to make the bottom of the chip conductive with the test socket.
Further, the adsorption hole 3 is arranged in the middle of the chip burn-in test area of the copper seat 1 and the diamond layer 2. The adsorption holes 3 are arranged in the middle to stabilize the fixing effect and are easier to operate.
Further, the pore diameter of the adsorption pores 3 is 100-200 micrometers. Can achieve better adsorption fixation and heat dissipation effects.
Further, the adsorption holes 3 are arranged at four corners of the chip burn-in test area of the copper seat 1 and the diamond layer 2. Through fixed to the four corners of chip, for the fixed effect in middle part unit position better, avoid taking place to rotate.
Further, the adsorption holes 3 are arranged on one or two pairs of opposite sides of the chip aging test areas of the copper seat 1 and the diamond layer 2, and the adsorption holes 3 are elongated or spaced holes. The arrangement of the adsorption hole 3 structure is more suitable for testing larger chips, and the problem that the middle part needs to be provided with the larger adsorption hole 3 to fix the chips is avoided.
The above description is only of the preferred embodiments of the present utility model and is not intended to limit the present utility model, and various modifications and variations may be made to the present utility model by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.
Claims (8)
1. The chip testing seat with high heat dissipation performance is characterized by comprising a copper seat and a diamond layer, wherein the diamond layer is arranged in a chip aging testing area of the copper seat, and through adsorption holes are formed in the copper seat and the diamond layer.
2. The high heat dissipation chip test socket of claim 1, wherein a solder layer is disposed between the diamond layer and the copper base for connection, at least opposite surfaces of the copper base and the diamond layer are plated with a gold layer, and the adsorption hole penetrates through the solder layer and the gold layer.
3. The high heat dissipation chip test socket of claim 1, wherein a nano silver paste layer is disposed between the copper base and the diamond layer, and the adsorption holes penetrate through the nano silver paste layer.
4. A high thermal dissipation chip test socket as defined in claim 1, 2 or 3, wherein said diamond layer is plated with a gold layer in said adsorption hole.
5. The die pad of claim 1, wherein the suction hole is formed in a middle portion of the die burn-in area of the copper pad and the diamond layer.
6. The high thermal dissipation chip test socket of claim 5, wherein said adsorption hole has a pore size of 100-200 microns.
7. The die pad of claim 1, wherein the adsorption holes are formed at four corners of the die burn-in area of the copper pad and the diamond layer.
8. The die attach pad of claim 1, wherein the attachment holes are formed in one or both of the copper pad and the diamond layer on one or both of the opposite sides of the die burn-in area, and wherein the attachment holes are elongated or spaced apart holes.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320768226.0U CN219657712U (en) | 2023-04-10 | 2023-04-10 | Chip test seat with high heat dissipation |
| DE202024101584.3U DE202024101584U1 (en) | 2023-04-10 | 2024-04-01 | Chip test seat with high heat dissipation |
| JP2024001039U JP3246985U (en) | 2023-04-10 | 2024-04-02 | Chip test seat with high heat dissipation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320768226.0U CN219657712U (en) | 2023-04-10 | 2023-04-10 | Chip test seat with high heat dissipation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219657712U true CN219657712U (en) | 2023-09-08 |
Family
ID=87880828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320768226.0U Active CN219657712U (en) | 2023-04-10 | 2023-04-10 | Chip test seat with high heat dissipation |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP3246985U (en) |
| CN (1) | CN219657712U (en) |
| DE (1) | DE202024101584U1 (en) |
-
2023
- 2023-04-10 CN CN202320768226.0U patent/CN219657712U/en active Active
-
2024
- 2024-04-01 DE DE202024101584.3U patent/DE202024101584U1/en active Active
- 2024-04-02 JP JP2024001039U patent/JP3246985U/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| DE202024101584U1 (en) | 2024-05-06 |
| JP3246985U (en) | 2024-06-07 |
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| GR01 | Patent grant | ||
| GR01 | Patent grant |