CN219609634U - Platform management system and device - Google Patents
Platform management system and device Download PDFInfo
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- CN219609634U CN219609634U CN202320495496.9U CN202320495496U CN219609634U CN 219609634 U CN219609634 U CN 219609634U CN 202320495496 U CN202320495496 U CN 202320495496U CN 219609634 U CN219609634 U CN 219609634U
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Abstract
The utility model is applicable to the technical field of platform management, and provides a platform management system and a device, wherein the platform management system comprises a domestic processor, a crystal oscillator, DDR3 particles, a memory chip, a first flash memory, a second flash memory, a change-over switch, a field programmable gate array, a third flash memory, an analog-to-digital converter, an Ethernet PHY chip, a board-to-board connector and a power module. The platform management system realizes autonomous controllability and reduces potential safety hazards.
Description
Technical Field
The utility model belongs to the technical field of platform management, and particularly relates to a platform management system and device.
Background
With current servers, the BMC (Baseboard Management Controller ) can better help us manage the server for status monitoring, remote maintenance management, etc. The BMC module mainly has the functions of realizing power-on and power-off control of the server, current and voltage detection and health state management. For BMC, BMC chips and BMC firmware are classified, however, the mainstream BMC chips used in the related art are still expected chips, and BMC firmware is generally the firmware of AmI company in the United states.
The main devices in the platform management of the related technology cannot be controlled independently, and potential safety hazards exist.
Disclosure of Invention
The embodiment of the utility model provides a platform management system, which aims to solve the problems that the platform management in the related technology cannot realize autonomous controllability and has potential safety hazard.
In order to solve the technical problems described above, an embodiment of the present utility model provides a platform management system, which includes a domestic processor, a crystal oscillator, DDR3 particles, a memory chip, a first flash memory, a second flash memory, a switch, a field programmable gate array, a third flash memory, an analog-to-digital converter, an ethernet PHY chip, a board-to-board connector, and a power module;
the model of the processor is LS2K0500; the field programmable gate array is GW2A series field programmable gate array;
the crystal oscillator, the DDR3 particles, the memory chip, the first flash memory, the second flash memory, the change-over switch, the field programmable gate array, the third flash memory, the analog-to-digital converter, the Ethernet PHY chip and the board-to-board connector are respectively connected with the processor;
the change-over switch is also connected with the first flash memory, the second flash memory and the field programmable gate array respectively; the field programmable gate array, the analog-to-digital converter and the Ethernet PHY chip are also respectively connected with the board-to-board connector;
the power module is respectively connected with the processor, the DDR3 particles, the memory chip, the first flash memory, the second flash memory, the field programmable gate array, the third flash memory, the analog-to-digital converter, the Ethernet PHY chip and the board-to-board connector.
Still further, the memory chip is model XTSD08GLGEAG.
Still further, the analog-to-digital converter is model CL1689.
Further, the model number of the ethernet PHY chip is YT8521.
Further, the power supply module comprises three first power supply chips, three second power supply chips, a synchronous buck converter and a linear voltage stabilizer;
three first power chips, three second power chips, one synchronous buck converter and one linear voltage stabilizer are respectively connected with the board-to-board connector; the three first power chips are respectively connected with the processor, one of the first power chips is respectively connected with the first flash memory, the second flash memory and the third flash memory, and the other first power chip is connected with one of the second power chips; one of the second power chips is respectively connected with the processor and the DDR3 particles, the other second power chip is connected with the linear voltage stabilizer, the linear voltage stabilizer is connected with the DDR3 particles, and the last second power chip is connected with the field programmable gate array; the synchronous buck converters are respectively connected with two of the second power chips.
Further, the model of the first power chip is SY6301.
Further, the second power chip is SY98003.
Still further, the synchronous buck converter IS model IS6605A.
Further, the linear voltage stabilizer is of the type SGM2054XTD10G.
The embodiment of the utility model also provides a platform management device, which comprises a shell, a bottom plate accommodated in the shell and a platform management system arranged on the bottom plate.
The utility model has the beneficial effects that: the platform management system is composed of a domestic processor, a crystal oscillator, DDR3 particles, a memory chip, a first flash memory, a second flash memory, a change-over switch, a field programmable gate array, a third flash memory, an analog-to-digital converter, an Ethernet PHY chip, a board-to-board connector and a power module, so that the autonomous controllability of the platform management system is realized, and the potential safety hazard is lower.
Drawings
FIG. 1 is a schematic diagram of a platform management system according to an embodiment of the present utility model;
FIG. 2 is a timing diagram of power supply in a platform management system according to an embodiment of the present utility model;
fig. 3 is a schematic diagram of a part of a platform management device according to an embodiment of the present utility model.
100, a platform management system; 1. a processor; 2. DDR3 particles; 3. a memory chip; 4. a first flash memory; 5. the second flash memory, 6, change over switch; 7. a field programmable gate array; 8. a third flash memory; 9. an ethernet PHY chip; 10. a board-to-board connector; 11. a first power chip; 12. a second power chip; 13. a synchronous buck converter; 14. a linear voltage stabilizer; 15. an analog-to-digital converter; 200. a platform management device; 201. a main board; 202. a sub-plate; 203. and (5) a peripheral interface.
Detailed Description
The present utility model will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present utility model more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs. The terminology used herein in the description of the utility model is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. In the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", and the like, if the connected circuits, modules, units, and the like have electrical or data transferred therebetween.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Meanwhile, the term used in the present specification includes any and all combinations of the items listed in association.
The embodiment of the utility model provides a platform management system 100, as shown in fig. 1, which comprises a domestic processor 1, a crystal oscillator, DDR3 particles 2, a memory chip 3, a first flash memory 4, a second flash memory 5, a switch 6, a field programmable gate array 7, a third flash memory 8, an analog-to-digital converter 15, an Ethernet PHY chip 9, a board-to-board connector 10 and a power module.
Specifically, the crystal oscillator, the DDR3 granule 2, the memory chip 3, the first flash memory 4, the second flash memory 5, the switch 6, the field programmable gate array 7, the third flash memory 8, the analog-to-digital converter 15, the ethernet PHY chip 9, and the board-to-board connector 10 are respectively connected to the processor 1.
The change-over switch 6 is also connected with the first flash memory 4, the second flash memory 5 and the field programmable gate array 7 respectively; the field programmable gate array 7, the analog-to-digital converter 15 and the ethernet PHY chip 9 are also connected to the board-to-board connector 10, respectively.
The power supply module is respectively connected with the processor 1, the DDR3 particles 2, the memory chip 3, the first flash memory 4, the second flash memory 5, the field programmable gate array 7, the third flash memory 8, the analog-to-digital converter 15, the Ethernet PHY chip 9 and the board-to-board connector 10; the power module may be directly connected to other devices or may be indirectly connected to other devices.
Of course, other necessary or unnecessary devices may be disposed in the platform management system 100 according to the actual requirements, which are not illustrated herein.
In this embodiment, the model of the processor 1 is LS2K0500 of the scientific and technological corporation in Loongson, which is mainly used for implementing data read-write operation with the user terminal, and is an important chip for ensuring continuous and stable operation of the system.
In this embodiment, the crystal oscillator is manufactured by Yang Xing technology limited and is 50MHz, which is used to provide the system with clock frequency.
In this embodiment, the DDR3 granule 2 is an ultraviolet DDR3, which is mainly used for storing an internal data link table of the system, increasing a data reading rate of the first FLASH memory 4 or the second FLASH memory 5, and the FLASH memory is also called as a FLASH.
In this embodiment, the model of the memory chip 3 (SD NAND) is XTSD08GLGEAG of shenzhen core advanced technology inc, which is mainly used as the stored extended SDIO interface for data storage and reading and writing.
In this embodiment, the first flash memory 4, the second flash memory 5, and the third flash memory 8 are all flash memory grains manufactured by wuhan-sinc integrated circuits, which are mainly used as data storage media for storing data for writing.
In this embodiment, the switch 6 is configured to switch the on states of the first flash memory 4 and the second flash memory 5, that is, control the connection states of the first flash memory 4 and the second flash memory 5 with the processor 1.
In this embodiment, the field programmable gate array 7 is a field programmable gate array 7 of GW2A series of guangdong high cloud semiconductor technology, which is mainly used for controlling the start of BIOS (firmware, basic input output system).
In this embodiment, the analog-to-digital converter 15 is configured to provide a data acquisition channel, and the model is CL1689 with a core interconnect, which can provide an ADC interface of an SPI interface for the system to sample voltage and current.
In this embodiment, the ethernet PHY chip 9 is of the type YT8521 from yutai microelectronic, inc, for providing network output to the system.
In this embodiment, the board-to-board connector 10 is a connection hub between the system and the host, so as to realize data signal transmission and improve the vibration resistance of the system.
In this embodiment, the power module is configured to provide a stable power input to other devices in the system.
Specifically, the power supply module includes three first power supply chips 11, three second power supply chips 12, one synchronous buck converter 13, and one linear regulator 14.
Wherein three of the first power chips 11, three of the second power chips 12, one of the synchronous buck converters 13, and one of the linear regulators 14 are connected to the board-to-board connector 10, respectively; three first power chips 11 are respectively connected with the processor 1, wherein one first power chip 11 is respectively connected with the first flash memory 4, the second flash memory 5 and the third flash memory 8, and the other first power chip 11 is connected with one second power chip 12; one of the second power chips 12 is connected with the processor 1 and the DDR3 particles 2 respectively, the other second power chip 12 is connected with the linear voltage stabilizer 14, the linear voltage stabilizer 14 is connected with the DDR3 particles 2, and the last second power chip 12 is connected with the field programmable gate array 7; the synchronous buck converters 13 are each connected to two of the second power chips 12.
In this embodiment, the first power chip 11 and the second power chip 12 both supply power to the board-to-board connector 10 in a unified manner by 5V, and respectively provide power inputs for the processor 1, the field programmable gate array 7, the first flash memory 4, the second flash memory 5, the third flash memory 8, the DDR3 granule 2, etc., and specific power timings are shown in fig. 2.
According to the embodiment, the platform management system 100 is formed by adopting the domestic processor 1, the crystal oscillator, the DDR3 particles 2, the memory chip 3, the first flash memory 4, the second flash memory 5, the change-over switch 6, the field programmable gate array 7, the third flash memory 8, the analog-to-digital converter 15, the Ethernet PHY chip 9, the board-to-board connector 10 and the power module, so that the autonomous controllability of the platform management system 100 is realized, the potential safety hazard is lower, in addition, the platform management system 100 can realize the remote monitoring of the health management state of the server, the labor cost and the time cost are saved, the space-crossing coordination work and the like.
The present utility model also provides a platform management device 200, which includes a housing, a base plate accommodated in the housing, and a platform management system 100 mounted on the base plate as in the above embodiment.
As shown in fig. 3, the chassis includes a main board 201 and a sub-board 202 mounted on the main board 201, and the platform management system 100 in the above embodiment is mounted on the sub-board 202; in addition, the board-to-board connector 10 is connected to a peripheral interface 203 provided on the main board 201 through another connector to be connected to an external host terminal through the peripheral interface 203.
Since the platform management device 200 in the present embodiment includes the platform management system 100 in the above embodiment, the technical effects achieved by the platform management system 100 in the above embodiment can be achieved, and will not be described herein.
The foregoing description of the preferred embodiments of the utility model is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the utility model.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the utility model, which are described in detail and are not to be construed as limiting the scope of the utility model. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the utility model, which are all within the scope of the utility model. Accordingly, the scope of protection of the present utility model is to be determined by the appended claims.
Claims (10)
1. The platform management system is characterized by comprising a domestic processor, a crystal oscillator, DDR3 particles, a storage chip, a first flash memory, a second flash memory, a change-over switch, a field programmable gate array, a third flash memory, an analog-to-digital converter, an Ethernet PHY chip, a board-to-board connector and a power module;
the model of the processor is LS2K0500; the field programmable gate array is GW2A series field programmable gate array;
the crystal oscillator, the DDR3 particles, the memory chip, the first flash memory, the second flash memory, the change-over switch, the field programmable gate array, the third flash memory, the analog-to-digital converter, the Ethernet PHY chip and the board-to-board connector are respectively connected with the processor;
the change-over switch is also connected with the first flash memory, the second flash memory and the field programmable gate array respectively; the field programmable gate array, the analog-to-digital converter and the Ethernet PHY chip are also respectively connected with the board-to-board connector;
the power module is respectively connected with the processor, the DDR3 particles, the memory chip, the first flash memory, the second flash memory, the field programmable gate array, the third flash memory, the analog-to-digital converter, the Ethernet PHY chip and the board-to-board connector.
2. The platform management system of claim 1, wherein the memory chip is model XTSD08GLGEAG.
3. The platform management system of claim 1, wherein the analog-to-digital converter is model CL1689.
4. The platform management system of claim 1, wherein the ethernet PHY chip is model YT8521.
5. The platform management system according to any one of claims 1 to 4 wherein the power module comprises three first power chips, three second power chips, a synchronous buck converter, and a linear regulator;
three first power chips, three second power chips, one synchronous buck converter and one linear voltage stabilizer are respectively connected with the board-to-board connector; the three first power chips are respectively connected with the processor, one of the first power chips is respectively connected with the first flash memory, the second flash memory and the third flash memory, and the other first power chip is connected with one of the second power chips; one of the second power chips is respectively connected with the processor and the DDR3 particles, the other second power chip is connected with the linear voltage stabilizer, the linear voltage stabilizer is connected with the DDR3 particles, and the last second power chip is connected with the field programmable gate array; the synchronous buck converters are respectively connected with two of the second power chips.
6. The platform management system of claim 5, wherein the first power chip is model SY6301.
7. The platform management system of claim 5, wherein the second power chip is model SY98003.
8. The platform management system according to claim 5 wherein said synchronous buck converter IS model IS6605A.
9. The platform management system of claim 5, wherein the linear voltage regulator is model SGM2054XTD10G.
10. A platform management device comprising a housing, a base plate received in the housing, and a platform management system according to any one of claims 1 to 9 mounted to the base plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320495496.9U CN219609634U (en) | 2023-03-13 | 2023-03-13 | Platform management system and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320495496.9U CN219609634U (en) | 2023-03-13 | 2023-03-13 | Platform management system and device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219609634U true CN219609634U (en) | 2023-08-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202320495496.9U Active CN219609634U (en) | 2023-03-13 | 2023-03-13 | Platform management system and device |
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| Country | Link |
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| CN (1) | CN219609634U (en) |
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- 2023-03-13 CN CN202320495496.9U patent/CN219609634U/en active Active
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