CN211860143U

CN211860143U - Multi-network port mainboard supporting POE protocol

Info

Publication number: CN211860143U
Application number: CN202020931723.4U
Authority: CN
Inventors: 王利东
Original assignee: Shenzhen Zhiao Technology Co ltd
Current assignee: Shenzhen Zhiao Technology Co ltd
Priority date: 2020-05-28
Filing date: 2020-05-28
Publication date: 2020-11-03
Anticipated expiration: 2030-05-28

Abstract

The multi-network-port mainboard supporting the POE protocol mainly comprises a central processing unit, a bus analog output module, a packet switching IC chip differential clock buffer, a mainboard SIO chip, an LVDS interface, a pulse width modulation controller, a POE chip, an LAN interface, a filter chip and an Ethernet controller which are electrically connected; the utility model discloses a support POE agreement to make the network terminal equipment of access need not to arrange solitary power cord and installation adapter, reduced wiring work load and erection equipment, thereby improved the job stabilization nature of mainboard.

Description

Multi-network port mainboard supporting POE protocol

Technical Field

The utility model relates to a softrouter mainboard especially relates to a support many net gapes mainboard of POE agreement.

Background

Poe (power Over ethernet) refers to a technology that, without any change to the existing ethernet wiring infrastructure, can provide dc power for some IP-based network terminal devices while transmitting data signals to such devices. POE, also known as Power over local area network (POL) or Active Ethernet (Active Ethernet), sometimes referred to simply as Power over Ethernet, is a recent standard specification for simultaneously transferring data and electrical Power using existing standard Ethernet transmission cables, and maintains compatibility with existing Ethernet systems and users.

To the little application scene of network data, like office monitoring, the cloth net requires that the erection equipment is as few as possible, the wiring is succinct as far as possible, and support POE technical soft route mainboard, when arranging the access of network terminal equipment, as long as a net twine of RJ45 can let equipment get into operating condition, not only remove the work of installation adapter from, need not solitary DC power supply, it is more succinct also to make the line of walking, the customer is when arranging the application, not only reduce corresponding work load, and the less probability of going out the problem of the equipment of installation is also lower. Therefore, a soft routing motherboard supporting the POE protocol is urgently needed to meet the networking requirement of an application scenario with small network data.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a support POE agreement's many net gapes mainboard to make the network terminal equipment who inserts need not to arrange solitary power cord and installation adapter, thereby reduced wiring work load and erection equipment.

In order to achieve the above purpose, the utility model adopts the technical scheme that: providing a multi-port mainboard supporting a POE protocol, wherein the multi-port mainboard comprises a central processing unit, a bus analog output module, a packet switching IC chip differential clock buffer, a mainboard SIO chip, an LVDS interface, a pulse width modulation controller, a POE chip, a LAN interface, a filter chip and an Ethernet controller which are electrically connected; the central processing unit is a low-power processor; the bus analog quantity output module is used for converting a digital signal output by the central processing unit into an adjustable continuous voltage and current signal through digital-analog conversion and outputting the adjustable continuous voltage and current signal to hardware or software connected with the mainboard; the differential clock buffer of the packet switching IC chip is used for coordinating and buffering the central processing unit and the working clock of the external equipment of the mainboard so as to realize synchronous transmission of data; the mainboard SIO chip provides a control processing function for a standard I/O interface on the mainboard; the LVDS interface is used for driving the liquid crystal display screen; the pulse width modulation controller is used for controlling an analog circuit by a digital signal output by the central processing unit; the POE chip is a power supply module supporting a POE protocol so as to realize power supply through the Ethernet; the LAN interface is a gigabit R45 Ethernet interface with POE function, the LAN interface is used for connecting network terminal equipment with a local area network, and the LAN interface also provides power supply for the connected network terminal equipment; the filtering chip is an integrated circuit network transformer filtering chip and is used for filtering the power supply input by the LAN interface; the Ethernet controller is a network card and is used for connecting the network terminal equipment with a network.

Furthermore, the main board further comprises a first memory slot, a second memory slot, a FLASH memory and a FLASH memory chip, wherein the first memory slot is used for inserting a DDR memory bank, the second memory slot is used for inserting a DIMM memory bank, the FLASH memory is used for storing the setting information of the main board, and the FLASH memory chip is used for data reading, writing and transmission of the central processing unit.

Furthermore, the main board further comprises a 2-pin power supply socket, a 3-pin power supply socket, a 4-pin power supply socket, a direct-current power supply interface and a driving screen backlight power supply interface; the 2-pin power supply socket, the 3-pin power supply socket and the 4-pin power supply socket are used for the elements of the mainboard provide working power supply, the direct-current power supply interface is used for connecting a direct-current power supply to provide power for the mainboard, and the driving screen backlight power supply interface is used for providing backlight power for the liquid crystal display screen connected with the LVDS interface.

Furthermore, the mainboard further comprises an MSATA interface, an SATA interface and a JSATA interface, wherein the MSATA interface is used for accessing the small solid state hard disk, the SATA interface is used for accessing the SATA hard disk, and the JSATA interface is used for accessing the IDE hard disk or the SATA hard disk.

Furthermore, the mainboard further comprises a JCOMS1 jumper interface, a first COM interface, a second COM interface, a GPIO interface and an RJ45 interface; the JCOMS1 jumper interface is used for connecting the first COM interface and the second COM interface; the first COM interface and the second COM interface are used for connecting equipment with a UART serial port; the GPIO interface is a port expander and is used for controlling or acquiring information of an external device; the RJ45 interface is used to access a gigabit network.

Furthermore, the mainboard further comprises a WIFI interface, an SIM card slot, a first USB expansion interface, a second USB expansion interface, a third USB expansion interface and a USB interface; the WIFI interface is used for accessing a WIFI network card so as to provide a function of connecting a network through a wireless communication protocol; the SIM card slot is used for placing an SIM card so as to enable the mainboard to be connected with a network through a mobile signal; the USB expansion interface is used for connecting a USB device using a Freescale language writing interface; the USB interface is used for connecting equipment supporting USB2.0 or USB 1.1.

Furthermore, the mainboard also comprises a CPU fan interface, a first system fan interface, a second system fan interface, a third system fan interface and a mainboard memory battery; the CPU fan interface is used for accessing a CPU fan so as to prevent the central processing unit from being overhigh in temperature and further influence the normal working state of the central processing unit; the first system fan interface, the second system fan interface and the third system fan interface are used for being connected with a cooling fan, so that the temperature of the mainboard is prevented from being too high, and the normal working state of elements of the mainboard is further influenced; the mainboard memory battery is used for providing a protection power supply for the mainboard.

Furthermore, the main board also comprises a switch interface, a VGA interface circuit, a VGA interface, a reset switch button, a power switch button and a hard disk read-write indicator lamp interface; the switch interface comprises a restart switch interface, a power indicator light interface, a hard disk indicator light interface and a power switch interface; the VGA interface is used for connecting a VGA video display, and the VGA interface circuit supplies power for the VGA interface; the reset switch button is used for restarting an operating system of the central processing unit; the power switch button is used for connecting or disconnecting the mainboard with an external power supply; the hard disk reading and writing indicator light interface is used for accessing a hard disk reading and writing indicator light.

Further, the LAN interfaces include a first LAN interface, a second LAN interface, a third LAN interface, a fourth LAN interface, a fifth LAN interface, and a sixth LAN interface, the filter chips include a first filter chip, a second filter chip, a third filter chip, a fourth filter chip, a fifth filter chip, and a sixth filter chip, and the ethernet controllers include a first ethernet controller, a second ethernet controller, a third ethernet controller, a fourth ethernet controller, a fifth ethernet controller, and a sixth ethernet controller;

the first LAN interface is electrically connected to the first filter chip and the first ethernet controller, and provides network connection and POE power supply functions for the network terminal device connected to the first LAN interface;

the second LAN interface is electrically connected to the second filter chip and the second ethernet controller, and provides network connection and POE power supply functions for the network terminal device connected to the second LAN interface;

the third LAN interface is electrically connected with the third filtering chip and the third ethernet controller, and provides network connection and POE power supply functions for the network terminal equipment connected with the third LAN interface;

the fourth LAN interface is electrically connected to the fourth filter chip and the fourth ethernet controller, and provides network connection and POE power supply functions for the network terminal device connected to the fourth LAN interface;

the fifth LAN interface is electrically connected to the fifth filter chip and the fifth ethernet controller, and provides network connection and POE power supply functions for the network terminal device connected to the fifth LAN interface;

the sixth LAN interface is electrically connected to the sixth filter chip and the sixth ethernet controller, and provides network connection and POE power supply functions for the network terminal device connected to the sixth LAN interface.

Further, the flash memory chip includes a first flash memory chip, a second flash memory chip, a third flash memory chip, a fourth flash memory chip, a fifth flash memory chip, and a sixth flash memory chip.

The utility model has the advantages that the utility model provides a support POE agreement's many net gapes mainboard, including central processing unit, bus analog output module, packet switching IC chip difference clock buffer, mainboard SIO chip, LVDS interface, pulse width modulation controller, POE chip, LAN interface, filtering chip and ethernet controller according to electric connection; the utility model discloses a support POE agreement to make the network terminal equipment of access need not to arrange solitary power cord and installation adapter, reduced wiring work load and erection equipment, thereby improved the job stabilization nature of mainboard.

Drawings

The invention is further described below with reference to the accompanying drawings of the specification:

fig. 1 is a schematic structural diagram of the present invention.

The labels in the above figures are: 1. a central processing unit; 2. a bus analog output module; 3. a packet-switched IC chip differential clock buffer; 4. a motherboard SIO chip; 5. 2-pin power supply sockets; 6. an LVDS interface; 7. driving a screen backlight power supply interface; 8. a CPU fan interface; 9. a first system fan interface; 10. a pulse width modulation controller; 11. 4-pin power supply sockets; 12. a DC power supply interface; 13. JCOMS1 jumper interfaces; 14. a first memory slot; 15. a second memory slot; 16. a motherboard memory cell; 17. a first USB expansion interface; 18. a second system fan interface; 19. a first COM interface; 20. 3 pin power supply sockets; 21. a FLASH memory; 22. a switch interface; 23. a first serial port control chip; 24. an MSATA interface; 25. an SATA interface; 26. a JSATA interface; 27. a second COM interface; 28. a WIFI interface; 29. a second USB expansion interface; 30. a third USB expansion interface; 31. a SIM card slot; 32. a VGA interface circuit; 33. a VGA interface; 35. a GPIO interface; 36. a third system fan interface; 37. a reset switch button; 38. a power switch button; 39. an RJ45 interface; 40. a second serial port control chip; 41. a USB interface; 42. a hard disk reading and writing indicator light interface; 43. a first flash memory chip; 44. a second flash memory chip; 45. a third flash memory chip; 46. a fourth flash memory chip; 47. a fifth flash memory chip; 48. a sixth flash memory chip; 100. POE chip; 101. a first LAN interface; 102. a first filter chip; 103. a first Ethernet controller; 201. a second LAN interface; 202. a second filter chip; 203. a second Ethernet controller; 301. a third LAN interface; 302. a third filter chip; 303. a third Ethernet controller; 401. a fourth LAN interface; 402. a fourth filter chip; 403. a fourth Ethernet controller; 501. a fifth LAN interface; 502. a fifth filter chip; 503. a fifth Ethernet controller; 601. a sixth LAN interface; 602. a sixth filter chip; 603. a sixth Ethernet controller.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The same or similar reference numerals in the drawings of the present embodiment correspond to the same or similar components; in the description of the present invention, it should be understood that if there are the terms "upper", "lower", "left", "right", etc. indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of the description, but it is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore the terms describing the positional relationship in the drawings are only for illustrative purposes and are not to be construed as limitations of the present patent, and those skilled in the art can understand the specific meanings of the terms according to specific situations.

The technical solution of the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.

Fig. 1 shows a preferred embodiment of the present invention.

Referring to fig. 1, the multi-port motherboard supporting the POE protocol according to this embodiment includes a central processing unit 1, a bus analog output module 2, a packet switching IC chip differential clock buffer 3, a motherboard SIO chip 4, an LVDS interface 6, a pulse width modulation controller 10, a POE chip 100, a LAN interface, a filter chip, and an ethernet controller, which are electrically connected;

the central processing unit 1 is a low-power processor;

the bus analog quantity output module 2 is used for converting a digital signal output by the central processing unit 1 into an adjustable continuous voltage and current signal through digital-analog conversion and outputting the adjustable continuous voltage and current signal to hardware or software connected with the mainboard;

the packet switching IC chip differential clock buffer 3 is used for coordinating and buffering the central processing unit 1 and the working clock of the external equipment of the mainboard so as to realize synchronous transmission of data;

the mainboard SIO chip 4 provides a control processing function for a standard I/O interface on the mainboard;

the LVDS interface 6 is used for driving the liquid crystal display screen;

the pulse width modulation controller 10 is used for controlling the analog circuit by the digital signal output by the central processing unit 1;

the POE chip 100 is a power supply module supporting a POE protocol, so as to implement power supply over an ethernet network;

the LAN interface is a gigabit R45 Ethernet interface with POE function, the LAN interface is used for connecting the network terminal equipment with the local area network, and the LAN interface also provides power supply for the connected network terminal equipment;

the filtering chip is an integrated circuit network transformer filtering chip and is used for filtering the power supply input by the LAN interface;

the Ethernet controller is a network card and is used for connecting the network terminal equipment with a network.

The multi-network-port mainboard supporting the POE protocol provided by the technical scheme comprises a central processing unit 1, a bus analog output module 2, a packet switching IC chip differential clock buffer 3, a mainboard SIO chip 4, an LVDS interface 6, a pulse width modulation controller 10, a POE chip 100, an LAN interface, a filter chip and an Ethernet controller which are electrically connected; through supporting POE agreement to make the network terminal equipment who inserts need not to arrange solitary power cord and installation adapter, reduced wiring work load and erection equipment, thereby improved the job stabilization nature of mainboard.

Preferably, the model of the central processing unit 1 is INTELN2600, and the model is characterized by low power consumption, small heat productivity and strong software compatibility; the model of the bus analog output module 2 is TGP; the model of the packet switching IC chip differential clock buffer 3 is ASM 1184E; the model of the mainboard SIO chip 4 is IT 8786E; the model number of the pulse width modulation controller 10 is ISL 95836; the POE chip 100 has a model number IP 804.

As an embodiment of the present invention, this mainboard still includes first memory slot 14, second memory slot 15, FLASH memory 21 and FLASH memory chip, and first memory slot 14 is used for inserting the DDR memory bank, and second memory slot 15 is used for inserting DIMM memory bank, and FLASH memory 21 is used for preserving the setting information of this mainboard, the FLASH memory chip is used for central processing unit 1's data to read and write and transmission.

Preferably, the FLASH memory 21 is of the type SST25VF 080B.

Specifically, the flash memory chips include a first flash memory chip 43, a second flash memory chip 44, a third flash memory chip 45, a fourth flash memory chip 46, a fifth flash memory chip 47, and a sixth flash memory chip 48; the first flash chip 43, the second flash chip 44, the third flash chip 45, the fourth flash chip 46, the fifth flash chip 47, and the sixth flash chip 48 are model numbers SST25VF040B/NC, which employ a four-wire SPI compatible interface, allowing for a low pin count package, taking up less board space, and ultimately reducing the overall system cost.

As an implementation manner of the present invention, the main board further includes a 2-pin power supply socket 5, a 3-pin power supply socket 20, a 4-pin power supply socket 11, a dc power supply interface 12, and a driving panel backlight power supply interface 7; the 2-pin power supply socket 5, the 3-pin power supply socket 20 and the 4-pin power supply socket 11 are used for providing working power for elements of the mainboard, the direct-current power supply interface 12 is used for connecting a direct-current power supply to provide power for the mainboard, and the driving screen backlight power supply interface 7 is used for providing backlight power for the liquid crystal display screen connected with the LVDS interface 6.

As an embodiment of the present invention, the motherboard further includes an MSATA interface 2524, an SATA interface 25, and a JSATA interface 2625, the MSATA interface 2524 is used for accessing the small solid state hard disk, the SATA interface 25 is used for accessing the SATA hard disk, and the JSATA interface 2625 is used for accessing the IDE hard disk or the SATA hard disk.

As an implementation manner of the present invention, the motherboard further includes a JCOMS1 jumper interface 13, a first COM interface 19, a second COM interface 27, a GPIO interface 35, and an RJ45 interface 39; the JCOMS1 jumper interface 13 is used for connecting the first COM interface 19 and the second COM interface 27; the first COM interface 19 and the second COM interface 27 are used for connecting a device with a UART serial port; the GPIO interface 35 is a port expander, and is used to control or collect information of an external device; the RJ45 interface 39 is used to access a gigabit network.

Specifically, the main board further comprises a first serial port control chip 23 electrically connected with the first COM interface 19 and a second serial port control chip 40 electrically connected with the second COM interface 27, wherein the first serial port control chip 23 and the second serial port control chip 40 are a multi-channel RS-232 driver and receiver and have the model of GD 75232.

As an embodiment of the present invention, the main board further includes a WIFI interface 28, a SIM card slot 31, a first USB expansion interface 17, a second USB expansion interface 29, a third USB expansion interface 30, and a USB interface 41; the WIFI interface 28 is used for accessing a WIFI network card to provide a function of connecting a network through a wireless communication protocol; the SIM card slot 31 is used for placing a SIM card so that the main board is connected to a network through a mobile signal; the USB expansion interface is used for connecting a USB device using a Freescale language writing interface; the USB interface 41 is used to connect devices supporting USB2.0 or USB 1.1.

As an implementation manner of the present invention, the motherboard further includes a CPU fan interface 8, a first system fan interface 9, a second system fan interface 18, a third system fan interface 36, and a motherboard memory battery 16; the CPU fan interface 8 is used for accessing a CPU fan so as to prevent the central processing unit 1 from being overhigh in temperature and further influence the normal working state of the central processing unit 1; the first system fan interface 9, the second system fan interface 18 and the third system fan interface 36 are used for connecting a heat dissipation fan, so that the temperature of the motherboard is prevented from being too high, and the normal working state of elements of the motherboard is prevented from being influenced; the motherboard memory cell 16 is used to provide a protection power supply for the motherboard.

As an implementation manner of the present invention, the motherboard further includes a switch interface 22, a VGA interface 33 circuit 32, a VGA interface 33, a reset switch button 37, a power switch button 38, and a hard disk read-write indicator light interface 42; the switch interface 22 comprises a restart switch interface 22, a power indicator light interface, a hard disk indicator light interface and a power switch interface 22; the VGA interface 33 is used for connecting a VGA video display, and the VGA interface 33 circuit 32 supplies power to the VGA interface 33; the reset switch button 37 is used for restarting the operating system of the central processing unit 1; the power switch button 38 is used for connecting or disconnecting the mainboard with an external power supply; the hard disk read-write indicator light interface 42 is used for accessing a hard disk read-write indicator light.

Preferably, VGA interface 33 circuit 32 is of the type CM2009, which provides ESD protection for all video signals, level shifting for DDC signals, and buffering for SYNC signals.

As an embodiment of the present invention, the LAN interface includes a first LAN interface 101, a second LAN interface 201, a third LAN interface 301, a fourth LAN interface 401, a fifth LAN interface 501, and a sixth LAN interface 601, the filter chip includes a first filter chip 102, a second filter chip 202, a third filter chip 302, a fourth filter chip 402, a fifth filter chip 502, and a sixth filter chip 602, and the ethernet controller includes a first ethernet controller 103, a second ethernet controller 203, a third ethernet controller 303, a fourth ethernet controller 403, a fifth ethernet controller 503, and a sixth ethernet controller 603;

the first LAN interface 101 is electrically connected to the first filter chip 102 and the first ethernet controller 103, and provides network connection and POE power supply functions for the network terminal device connected to the first LAN interface 101;

the second LAN interface 201 is electrically connected to the second filter chip 202 and the second ethernet controller 203, and provides network connection and POE power supply functions for the network terminal device connected to the second LAN interface 201;

the third LAN interface 301 is electrically connected to the third filter chip 302 and the third ethernet controller 303, and provides network connection and POE power supply functions for the network terminal device connected to the third LAN interface 301;

the fourth LAN interface 401 is electrically connected to the fourth filter chip 402 and the fourth ethernet controller 403, and provides network connection and POE power supply functions for the network terminal device connected to the fourth LAN interface 401;

the fifth LAN interface 501 is electrically connected to the fifth filter chip 502 and the fifth ethernet controller 503, and provides network connection and POE power supply functions for the network terminal device connected to the fifth LAN interface 501;

the sixth LAN interface 601 is electrically connected to the sixth filtering chip 602 and the sixth ethernet controller 603, and provides network connection and POE power supply functions for the network terminal device connected to the sixth LAN interface 601.

Specifically, the models of the first filter chip 102, the second filter chip 202, the third filter chip 302, the fourth filter chip 402, the fifth filter chip 502, and the sixth filter chip 602 are EG24a 005S; the first ethernet controller 103, the second ethernet controller 203, the third ethernet controller 303, the fourth ethernet controller 403, the fifth ethernet controller 503 and the sixth ethernet controller 603 are of the type Intel I211.

The embodiments of the present invention have been described in detail, but the invention is not limited to the embodiments, and those skilled in the art can make many equivalent modifications or substitutions without departing from the spirit of the present invention, and the equivalent modifications or substitutions are included in the scope of protection defined by the claims of the present application.

Claims

1. Support many network interfaces mainboard of POE agreement, characterized by: the system comprises a central processing unit, a bus analog output module, a packet switching IC chip differential clock buffer, a mainboard SIO chip, an LVDS interface, a pulse width modulation controller, a POE chip, a LAN interface, a filter chip and an Ethernet controller which are electrically connected;

the central processing unit is a low-power processor;

the bus analog quantity output module is used for converting a digital signal output by the central processing unit into an adjustable continuous voltage and current signal through digital-analog conversion and outputting the adjustable continuous voltage and current signal to hardware or software connected with the mainboard;

the differential clock buffer of the packet switching IC chip is used for coordinating and buffering the central processing unit and the working clock of the external equipment of the mainboard so as to realize synchronous transmission of data;

the mainboard SIO chip provides a control processing function for a standard I/O interface on the mainboard;

the LVDS interface is used for driving the liquid crystal display screen;

the pulse width modulation controller is used for controlling an analog circuit by a digital signal output by the central processing unit;

the POE chip is a power supply module supporting a POE protocol so as to realize power supply through the Ethernet;

the LAN interface is a gigabit R45 Ethernet interface with POE function, the LAN interface is used for connecting network terminal equipment with a local area network, and the LAN interface also provides power supply for the connected network terminal equipment;

2. The multi-port motherboard supporting POE protocol of claim 1, wherein: the mainboard further comprises a first memory slot, a second memory slot, a FLASH memory and a FLASH memory chip, wherein the first memory slot is used for inserting the DDR memory bank, the second memory slot is used for inserting the DIMM memory bank, the FLASH memory is used for storing the setting information of the mainboard, and the FLASH memory chip is used for reading, writing and transmitting data of the central processing unit.

3. The multi-port motherboard supporting POE protocol of claim 1, wherein: the main board further comprises a 2-pin power supply socket, a 3-pin power supply socket, a 4-pin power supply socket, a direct-current power supply interface and a driving screen backlight power supply interface; the 2-pin power supply socket, the 3-pin power supply socket and the 4-pin power supply socket are used for the elements of the mainboard provide working power supply, the direct-current power supply interface is used for connecting a direct-current power supply to provide power for the mainboard, and the driving screen backlight power supply interface is used for providing backlight power for the liquid crystal display screen connected with the LVDS interface.

4. The multi-port motherboard supporting POE protocol of claim 1, wherein: the mainboard further comprises an MSATA interface, an SATA interface and a JSATA interface, the MSATA interface is used for accessing the small solid state hard disk, the SATA interface is used for accessing the SATA hard disk, and the JSATA interface is used for accessing the IDE hard disk or the SATA hard disk.

5. The multi-port motherboard supporting POE protocol of claim 1, wherein: the mainboard further comprises a JCOMS1 jumper interface, a first COM interface, a second COM interface, a GPIO interface and an RJ45 interface; the JCOMS1 jumper interface is used for connecting the first COM interface and the second COM interface; the first COM interface and the second COM interface are used for connecting equipment with a UART serial port; the GPIO interface is a port expander and is used for controlling or acquiring information of an external device; the RJ45 interface is used to access a gigabit network.

6. The multi-port motherboard supporting POE protocol of claim 1, wherein: the mainboard further comprises a WIFI interface, an SIM card slot, a first USB expansion interface, a second USB expansion interface, a third USB expansion interface and a USB interface; the WIFI interface is used for accessing a WIFI network card so as to provide a function of connecting a network through a wireless communication protocol; the SIM card slot is used for placing an SIM card so as to enable the mainboard to be connected with a network through a mobile signal; the USB expansion interface is used for connecting a USB device using a Freescale language writing interface; the USB interface is used for connecting equipment supporting USB2.0 or USB 1.1.

7. The multi-port motherboard supporting POE protocol of claim 1, wherein: the mainboard also comprises a CPU fan interface, a first system fan interface, a second system fan interface, a third system fan interface and a mainboard memory battery; the CPU fan interface is used for accessing a CPU fan so as to prevent the central processing unit from being overhigh in temperature and further influence the normal working state of the central processing unit; the first system fan interface, the second system fan interface and the third system fan interface are used for being connected with a cooling fan, so that the temperature of the mainboard is prevented from being too high, and the normal working state of elements of the mainboard is further influenced; the mainboard memory battery is used for providing a protection power supply for the mainboard.

8. The multi-port motherboard supporting POE protocol of claim 1, wherein: the main board also comprises a switch interface, a VGA interface circuit, a VGA interface, a reset switch button, a power switch button and a hard disk read-write indicator lamp interface; the switch interface comprises a restart switch interface, a power indicator light interface, a hard disk indicator light interface and a power switch interface; the VGA interface is used for connecting a VGA video display, and the VGA interface circuit supplies power for the VGA interface; the reset switch button is used for restarting an operating system of the central processing unit; the power switch button is used for connecting or disconnecting the mainboard with an external power supply; the hard disk reading and writing indicator light interface is used for accessing a hard disk reading and writing indicator light.

9. The multi-port motherboard supporting POE protocol of claim 1, wherein: the LAN interface comprises a first LAN interface, a second LAN interface, a third LAN interface, a fourth LAN interface, a fifth LAN interface and a sixth LAN interface, the filter chip comprises a first filter chip, a second filter chip, a third filter chip, a fourth filter chip, a fifth filter chip and a sixth filter chip, and the ethernet controller comprises a first ethernet controller, a second ethernet controller, a third ethernet controller, a fourth ethernet controller, a fifth ethernet controller and a sixth ethernet controller;

10. The multi-port motherboard supporting POE protocol of claim 2, wherein: the flash memory chip comprises a first flash memory chip, a second flash memory chip, a third flash memory chip, a fourth flash memory chip, a fifth flash memory chip and a sixth flash memory chip.