CN219435869U

CN219435869U - 5 inch TVS and STD device chip structure

Info

Publication number: CN219435869U
Application number: CN202320659451.0U
Authority: CN
Inventors: 王天宇; 杨杰; 李大伟
Original assignee: Taicang Tianyu Electronics Co ltd
Current assignee: Taicang Tianyu Electronics Co ltd
Priority date: 2023-03-29
Filing date: 2023-03-29
Publication date: 2023-07-28
Anticipated expiration: 2033-03-29

Abstract

The utility model discloses a chip structure of a 5-inch TVS and STD device, which comprises the following components: the chip body comprises an N-type substrate, an oxide layer is arranged at the bottom of the N-type substrate, the bottom metal layer penetrates through the oxide layer and then contacts with the bottom N diffusion area, the bottom metal layer comprises a protruding layer extending out of the surface of the oxide layer, the area of the bottom metal layer is smaller than that of the chip body, the bottom of the chip body is brushed with a first conductive adhesive layer, the first conductive adhesive layer covers the bottom metal layer, the chip body is adhered to the packaging frame, a first groove is formed in the packaging frame, the first conductive adhesive layer contacts with the bottom surface of the first groove, a through hole is formed in the bottom surface of the first groove, and second conductive adhesive is filled in the through hole. Compared with the prior art, the utility model effectively avoids the short circuit generated in the packaging process of the chip used in the TVS device or the STD device, and improves the packaging yield.

Description

5 inch TVS and STD device chip structure

Technical Field

The utility model relates to the technical field of diode chips, in particular to a chip structure of a 5-inch TVS and STD device.

Background

A TVS is a high performance protection device in the form of a diode. When the two poles of the TVS diode are impacted by reverse transient high energy, the high resistance between the two poles can be changed into low resistance at the speed of the magnitude of minus 12 seconds of 10, the surge power of thousands of watts is absorbed, the voltage clamp between the two poles is positioned at a preset value, and the precise components in the electronic circuit are effectively protected from being damaged by various surge pulses. The common rectifying diode (STD device) has significant unidirectional conductivity.

Circuit protection is typically implemented in a circuit using TVS devices or STD devices, the core of which is the chip. Because the metal layer on the back of the chip is easy to generate Ag batting during dicing, short circuit is easy to be caused when the overflow height of the conductive adhesive is too high in the chip packaging process of the traditional diode device, and the packaging yield is affected.

Disclosure of Invention

The utility model aims at: the chip structure of the TVS and STD device with 5 inches is provided, so that the chip used in the TVS device or the STD device is effectively prevented from generating short circuit in the packaging process, and the packaging yield is improved.

In order to achieve the above purpose, the present utility model adopts the following technical scheme: a 5 inch TVS and STD device chip structure comprising: the chip body comprises an N-type substrate, a top N diffusion area and a top P diffusion area are arranged on one side of the N-type substrate, a bottom N diffusion area and a bottom P diffusion area are arranged on the opposite side of the N-type substrate, a top metal layer is arranged on the upper side of the N-type substrate, an oxide layer is arranged at the bottom of the N-type substrate, the bottom metal layer penetrates through the oxide layer and then contacts the bottom N diffusion area, the bottom metal layer comprises a protruding layer extending out of the surface of the oxide layer, the area of the bottom metal layer is smaller than that of the chip body, a first conductive adhesive layer is brushed at the bottom of the chip body, the first conductive adhesive layer covers the bottom metal layer, the chip body is adhered to the packaging frame, a first groove is formed in the packaging frame and contacts the bottom surface of the first groove, a through hole is formed in the bottom surface of the first groove, and second conductive adhesive is filled in the through hole.

As a further description of the above technical solution:

the first groove bottom surface is provided with a roughened surface layer.

As a further description of the above technical solution:

the package frame is provided with a package body.

As a further description of the above technical solution:

the package is a ceramic cover.

As a further description of the above technical solution:

the thickness of the protruding layer is less than 5um.

As a further description of the above technical solution:

the depth of the first groove is equal to the thickness of the first conductive adhesive layer.

In summary, due to the adoption of the technical scheme, the beneficial effects of the utility model are as follows:

1. according to the utility model, the area of the bottom metal layer on the chip body is effectively controlled to be small, the length and the width of the bottom metal layer are smaller than those of the chip body, ag flocculation is avoided during dicing, short circuit caused by glue overflow of the chip body used in the TVS device or the STD device in the packaging process is effectively avoided, and the packaging yield is improved.

2. According to the utility model, the first groove is arranged on the packaging frame, so that the thickness of the whole packaged chip body can be effectively reduced after the chip body is adhered and fixed.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present utility model and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a chip structure of a 5-inch TVS and STD device.

Fig. 2 is a schematic diagram of a package frame in a 5 inch TVS and STD device chip structure.

Legend description:

1. a chip body; 11. an N-type substrate; 12. a top N diffusion region; 13. a top P diffusion region; 14. a bottom N diffusion region; 15. a bottom P diffusion region; 16. a top metal layer; 17. a bottom metal layer; 171. a protruding layer; 18. an oxide layer; 19. a first conductive adhesive layer; 2. a package frame; 21. a first groove; 211. a through hole; 212. a second conductive adhesive; 213. roughening the surface layer; 3. and (5) packaging the package.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

Referring to fig. 1-2, the present utility model provides a technical solution: a 5 inch TVS and STD device chip structure comprising: the chip comprises a chip body 1 and a packaging frame 2, wherein the chip body 1 comprises an N-type substrate 11, a top N diffusion region 12 and a top P diffusion region 13 are arranged on one side of the N-type substrate 11, a bottom N diffusion region 14 and a bottom P diffusion region 15 are arranged on the opposite side of the N-type substrate 11, a top metal layer 16 is arranged on the upper side of the N-type substrate 11, an oxide layer 18 is arranged at the bottom of the N-type substrate 11, the bottom metal layer 17 passes through the oxide layer 18 and then contacts the bottom N diffusion region 14, the bottom metal layer 17 comprises a protruding layer 171 protruding out of the surface of the oxide layer 18, the area of the bottom metal layer 17 is smaller than that of the chip body 1, a first conductive adhesive layer 19 is brushed at the bottom of the chip body 1, the first conductive adhesive layer 19 covers the bottom metal layer 17, the chip body 1 is adhered on the packaging frame 2, a first groove 21 is arranged on the packaging frame 2, the first conductive adhesive layer 19 contacts the bottom surface of the first groove 21, a through hole 211 is arranged on the bottom surface of the first groove 21, and the second conductive adhesive 212 is filled in the through hole 211.

The first groove 21 is provided with a roughened surface layer 213 on the bottom surface, and the roughened surface layer 213 is formed by roughening treatment for improving the adhesion fixing effect of the chip body 1.

The packaging frame 2 is provided with a packaging body 3, and the packaging body 3 is a ceramic cover. The package 3 is used for protecting the chip body 1.

The thickness of the protruding layer 171 is less than 5um.

The depth of the first groove 21 is equal to the thickness of the first conductive adhesive layer 19, so that the overflow height is effectively controlled, and short circuit is avoided.

Working principle: on the one hand, the area of the bottom metal layer on the chip body is effectively controlled to be small, the length and the width of the bottom metal layer are smaller than those of the chip body, ag (silver) batting is avoided during scribing, short circuit caused by glue overflow of the chip body used in the TVS (transient voltage driver) device or the STD device in the packaging process is effectively avoided, and the packaging yield is improved. On the other hand, the first groove 21 on the packaging frame 2 is arranged, so that the thickness of the whole packaged chip body 1 can be effectively reduced after the chip body is adhered and fixed.

The foregoing is only a preferred embodiment of the present utility model, but the scope of the present utility model is not limited thereto, and any person skilled in the art, who is within the scope of the present utility model, should make equivalent substitutions or modifications according to the technical scheme of the present utility model and the inventive concept thereof, and should be covered by the scope of the present utility model.

Claims

1. A 5 inch TVS and STD device chip structure comprising: chip body (1) and encapsulation frame (2), chip body (1) are including N type substrate (11), N type substrate (11) one side is provided with top N diffusion district (12) and top P diffusion district (13), opposite side is provided with bottom N diffusion district (14) and bottom P diffusion district (15) on N type substrate (11), N type substrate (11) upside is provided with top metal layer (16), N type substrate (11) bottom is provided with oxide layer (18), bottom metal layer (17) pass behind oxide layer (18) contact bottom N diffusion district (14), bottom metal layer (17) are including stretching out oxide layer (18) surperficial bulge layer (171), the area of bottom metal layer (17) is less than the area of chip body (1), chip body (1) bottom is brushed first conductive adhesive layer (19), first conductive adhesive layer (19) cover bottom metal layer (17), adhesive layer (1) are passed contact bottom N diffusion district (14), first adhesive layer (21) are provided with groove (21) on the encapsulation frame (21), the through holes (211) are filled with second conductive adhesive (212).

2. A 5 inch TVS and STD device chip structure as claimed in claim 1, wherein said first recess (21) has a roughened surface layer (213) provided on the bottom surface thereof.

3. The 5-inch TVS and STD device chip structure of claim 1, wherein said package frame (2) is provided with a package body (3).

4. A 5 inch TVS and STD device chip structure as claimed in claim 3, wherein said package (3) is a ceramic cap.

5. The 5 inch TVS and STD device chip structure of claim 1, wherein said protruding layer (171) has a thickness of less than 5um.

6. A 5 inch TVS and STD device chip structure as claimed in claim 1, wherein the depth of said first recess (21) is equal to the thickness of said first conductive glue layer (19).