CN219393403U - Semiconductor structure and integrated circuit - Google Patents
Semiconductor structure and integrated circuit Download PDFInfo
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- CN219393403U CN219393403U CN202320182325.0U CN202320182325U CN219393403U CN 219393403 U CN219393403 U CN 219393403U CN 202320182325 U CN202320182325 U CN 202320182325U CN 219393403 U CN219393403 U CN 219393403U
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Abstract
A semiconductor structure and integrated circuit are disclosed, the semiconductor structure including a substrate having a first doping type; an epitaxial layer on the substrate, the epitaxial layer having a first doping type; the base region and the emitter region are positioned in the epitaxial layer, the emitter region is in contact with the base region, the emitter region has a first doping type, the base region has a second doping type, and the first doping type is opposite to the second doping type; the field oxide layer is positioned on the epitaxial layer and is used for limiting the base region; a base poly on the base region and an emitter poly on the emitter region, the base poly having a second doping type and the emitter poly having a first doping type; and the dielectric layer is positioned on the base region and isolates the emitter polycrystal from the base polycrystal. The self-alignment process is utilized to carry out photoetching on the polysilicon and the metal simultaneously, so that the base electrode polycrystal is completely aligned with the base electrode and the emitter electrode polycrystal is completely aligned with the emitter electrode, and the problems of thickness loss of the polysilicon, occurrence of mechanical deflection of a contact hole and the like are avoided.
Description
Technical Field
The present utility model relates to semiconductor devices, and more particularly, to a semiconductor structure and an integrated circuit.
Background
The radio frequency transistor is characterized by small characteristic size, low breakdown voltage, extremely high characteristic frequency, small noise, but large manufacturing process difficulty compared with the common bipolar transistor. The low-noise amplifier is generally applied to high-frequency broadband low-noise amplifiers such as VHF (very high frequency) wireless communication, UHF (ultra high frequency) wireless communication, CATV (cable television), wireless remote control, radio frequency modules and the like, and the application occasions are mainly used under low-voltage, small-signal, small-current and low-noise conditions.
The radio frequency transistor has thin epitaxial layer, low junction depth of the polycrystalline emitter and small doping concentration of the base region, so that the requirements on layout size, surface state, polycrystalline growth and junction depth uniformity are very high, and several technological parameters such as polycrystalline thickness, injection range, CD and OVERLAY, pad oxygen thickness, etching film and the like are required to be controlled.
However, in the traditional manufacturing process, the problems of serious dry etching damage of a base region hole, polycrystalline thickness loss of a polycrystalline emitter, easiness in mechanical deflection of a contact hole, small contact area between metal and polycrystalline and the like can occur, so that the problems of large fluctuation of an amplification factor, poor large current capacity, low characteristic frequency, large noise and the like of a radio-frequency transistor device are caused.
Disclosure of Invention
The utility model aims to provide a semiconductor structure and an integrated circuit, which can improve the contact area of metal and polycrystal and the characteristic frequency of the semiconductor structure.
According to a first aspect of the present utility model, there is provided a semiconductor structure comprising: a substrate having a first doping type; an epitaxial layer on the substrate, the epitaxial layer having a first doping type; the base region and the emitter region are positioned in the epitaxial layer, wherein the emitter region is in contact with the base region, the emitter region has a first doping type, the base region has a second doping type, and the first doping type is opposite to the second doping type; the field oxide layer is positioned on the epitaxial layer and is used for limiting a base region; a base poly on the base region and an emitter poly on the emitter region, the base poly having a second doping type and the emitter poly having a first doping type; and the dielectric layer is positioned on the base region and isolates the emitter polycrystal from the base polycrystal.
Preferably, the base region includes an intrinsic base region and an extrinsic base region, and the doping concentration of the extrinsic base region is higher than that of the intrinsic base region.
Preferably, the extrinsic base regions are located on both sides of and in contact with the intrinsic base region, and the intrinsic base region surrounds and is in contact with the emitter region.
Preferably, the extrinsic base regions and the emitter regions are located in the intrinsic base region and alternately spaced apart, and the extrinsic base regions are located outermost.
Preferably, the junction depth of the intrinsic base region and the extrinsic base region is 0.5 μm to 5 μm, and the junction depth of the extrinsic base region is deeper than that of the intrinsic base region.
Preferably, the thickness of the base poly and the emitter poly is
Preferably, the thickness of the field oxide layer is
Preferably, the thickness of the dielectric layer is
Preferably, the thickness of the epitaxial layer is 1 μm to 50 μm, and the resistivity is 0.1 Ω·cm to 100 Ω·cm.
Preferably, the semiconductor structure further comprises: a base on the base poly and an emitter on the emitter poly, the base being in perfect alignment with the base poly and the emitter being in perfect alignment with the emitter poly; the passivation layer is positioned on the field oxide layer, the dielectric layer, the base electrode and the emitter; and a collector electrode positioned on a side of the substrate away from the surface of the epitaxial layer.
Preferably, the first doping type is N-type, and the second doping type is P-type; or the first doping type is P type, and the second doping type is N type.
Preferably, the semiconductor structure is a radio frequency transistor.
According to a second aspect of the present utility model, there is provided an integrated circuit comprising at least one of the semiconductor structures described above.
Preferably, the integrated circuit is a BICMOS circuit or a BCD circuit.
According to the semiconductor structure and the integrated circuit provided by the embodiment of the utility model, the base polycrystalline and the emitter polycrystalline are formed by adopting the same layer of polycrystalline silicon on the base region and the emitter region, the base and the emitter are formed by adopting the same layer of metal on the base polycrystalline and the emitter polycrystalline, the base polycrystalline and the base are completely aligned and the emitter polycrystalline and the emitter are completely aligned by utilizing the self-alignment process to carry out photoetching on the polycrystalline silicon and the metal at the same time, the cost is reduced, the problems of thickness loss of the polycrystalline silicon, occurrence of offset of a contact hole and the like are avoided, the contact area of the metal and the polycrystalline silicon is improved, the characteristic frequency of the semiconductor structure is improved, the fluctuation of current amplification coefficient is reduced, the high current capacity is improved, and the noise of a device is reduced.
Further, the base electrode polycrystal plays an ohmic role and connects the base electrode with the base electrode; the formation of the base electrode polycrystal can reduce the photoetching times and the cost.
Furthermore, the base region comprises an intrinsic base region and an extrinsic base region, a certain distance is reserved between the emitter region and the extrinsic base region, and the extrinsic base region can reduce base resistance, improve frequency and reduce noise.
Further, the base electrode, the emitter electrode and the collector electrode comprise a titanium-titanium nitride layer, a metal layer and a titanium nitride layer which are sequentially stacked from bottom to top, so that the reflectivity of the metal layer can be reduced, photoetching is facilitated, and the risk of mutual dissolution of aluminum and silicon is reduced.
Drawings
The above and other objects, features and advantages of the present utility model will become more apparent from the following description of embodiments of the present utility model with reference to the accompanying drawings, in which:
fig. 1 shows a schematic structural diagram of a semiconductor structure provided according to an embodiment of the present utility model;
FIGS. 2 a-2 h are schematic structural views illustrating steps of a method for fabricating a semiconductor structure according to an embodiment of the present utility model;
fig. 3 is a schematic structural diagram of a semiconductor structure according to another embodiment of the present utility model.
Detailed Description
Various embodiments of the present utility model will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.
The utility model may be embodied in various forms, some examples of which are described below.
Fig. 1 shows a schematic structural diagram of a semiconductor structure according to an embodiment of the present utility model. The semiconductor structure is, for example, a rf transistor, and the NPN rf transistor is taken as an example in this embodiment, but not limited thereto.
Referring to fig. 1, the semiconductor structure includes a substrate 101, an epitaxial layer 102 on the substrate 101, a base region and an emitter region 107 in the epitaxial layer 102, a field oxide layer 103 and a dielectric layer 105 on the epitaxial layer 102, a base poly 108 on the base region, and an emitter poly 109 on the emitter region.
In this embodiment, the substrate 101 may be any suitable type of semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, or the like. The substrate 101, the epitaxial layer 102 and the emitter region 107 have a first doping type; the base region has a second doping type, which is opposite to the first doping type. The embodiment of the utility model is described by taking the first doping type as N-type doping and the second doping type as P-type doping as an example, but the utility model is not limited to the example. The substrate 101 is a heavily doped structure and the epitaxial layer 102 is a lightly doped structure.
In this embodiment, the thickness of the epitaxial layer 102 is 1 μm to 50 μm, and the resistivity is 0.1 Ω·cm to 100 Ω·cm.
The field oxide layer 103 is used to define a base region, and the thickness of the field oxide layer 103 is
A dielectric layer 105 is located over the base region for isolating the emitter poly 108 from the base poly 109. Dielectric layer 105 is an oxide layer formed by LPCVD or PECVD deposition and growth of the oxide layer, and the thickness of dielectric layer 105 is
In this embodiment, the base region includes an intrinsic base region 104 and an extrinsic base region 106, the doping types of the intrinsic base region 104 and the extrinsic base region 106 are both the second doping type, and the doping concentration of the extrinsic base region 106 is higher than the doping concentration of the intrinsic base region 104. The junction depth of the intrinsic base region 104 and the extrinsic base region 106 is 0.5 μm to 5 μm, and the junction depth of the extrinsic base region 106 is deeper than the junction depth of the intrinsic base region 104. In other embodiments, the extrinsic base regions 106 may not be formed if noise requirements are not high.
The extrinsic base regions 106 are located on both sides of the intrinsic base region 104 and are in contact with the intrinsic base region 104, and the intrinsic base region 104 surrounds the emitter region 107 and is in contact with the emitter region 107. The emitter region 107 is spaced apart from the extrinsic base region 106. The extrinsic base region 106 may reduce base resistance, improve the frequency of the semiconductor structure, and reduce noise.
The doping type of the emitter region 107 is a first doping type. The emitter region 107 is formed by impurity diffusion in polysilicon. A base poly 108 and an emitter poly 109 are formed on the extrinsic base region 106 and the emitter region 107, respectively, the base poly 108 being of the second doping type and the emitter poly 109 being of the first doping type. An opening is provided in the dielectric layer 105 through which the base poly 108 contacts the extrinsic base region 106 and through which the emitter poly 109 contacts the emitter region 107.
The semiconductor structure further includes a base 110 located on the base poly 108 and an emitter 111 located on the emitter poly 109.
In this embodiment, base poly 108 acts as an ohmic contact, connecting base region and base 110.
Specifically, base poly 108, base 110, and emitter poly 109 and emitter 111 are formed by self-aligning and simultaneously etching the polysilicon and metal such that base 110 is fully aligned with base poly 108 and emitter 111 is fully aligned with emitter poly 109. Removal by photolithographic etching is required without providing the base poly 108, however, this increases the number of photolithographic etching times, resulting in increased costs. Therefore, the formation of the base electrode polycrystal can reduce the photoetching etching times and the cost.
The semiconductor structure further includes a passivation layer 112 overlying the field oxide layer 103, the dielectric layer 105, the base 110, and the emitter 111, and a collector 113 located on a side surface of the substrate 101 remote from the epitaxial layer 102.
The base electrode 110, the emitter electrode 111 and the collector electrode 113 are metal layers, and the metal layers of the base electrode 110 and the emitter electrode 111 are, for example, aluminum or aluminum copper or aluminum silicon copper, and the metal layer of the collector electrode 113 is, for example, titanium, nickel, aluminum alloy, gold or tin, but not limited thereto.
In a preferred embodiment, the base 110, the emitter 111 and the collector 113 include a titanium-titanium nitride layer, a metal layer and a titanium nitride layer sequentially stacked from bottom to top, which can reduce the reflectivity of the metal layer, facilitate photolithography, and reduce the risk of mutual dissolution of aluminum and silicon.
In an alternative embodiment, the first doping type is P-type doping, the second doping type is N-type doping, and the corresponding semiconductor structure is a PNP radio frequency transistor.
The embodiment of the utility model also provides an integrated circuit comprising the semiconductor structure. The integrated circuit is, for example, a Bipolar-complementary metal oxide semiconductor hybrid (Bipolar and complementary metal oxide semiconductor, biCMOS) circuit or a Bipolar-complementary metal oxide semiconductor-double diffused metal oxide semiconductor hybrid (BCD) circuit.
The semiconductor structure and the integrated circuit of the embodiment of the utility model adopt the same layer of polysilicon to form the base electrode polycrystal and the emitter electrode polycrystal on the base region and the emitter region, adopt the same layer of metal to form the base electrode polycrystal and the emitter electrode polycrystal on the base electrode polycrystal and the emitter electrode polycrystal, utilize the self-alignment technology to carry out photoetching on the polysilicon and the metal simultaneously so as to lead the base electrode polycrystal to be completely aligned with the base electrode polycrystal and the emitter electrode polycrystal to be completely aligned with the emitter electrode polycrystal, reduce the cost, avoid the problems of thickness loss of the polysilicon, occurrence of offset of a contact hole and the like, improve the contact area of the metal and the polysilicon, improve the characteristic frequency of the semiconductor structure, reduce the fluctuation of current amplification coefficient, improve the large current capacity and reduce the noise of devices.
Furthermore, the base region comprises an intrinsic base region and an extrinsic base region, a certain distance is reserved between the emitter region and the extrinsic base region, and the extrinsic base region can reduce base resistance, improve frequency and reduce noise.
Further, the base electrode polycrystal plays an ohmic role and connects the base electrode with the base electrode; the formation of the base electrode polycrystal can reduce the photoetching times and the cost.
Further, the base electrode, the emitter electrode and the collector electrode comprise a titanium-titanium nitride layer, a metal layer and a titanium nitride layer which are sequentially stacked from bottom to top, so that the reflectivity of the metal layer can be reduced, photoetching is facilitated, and the risk of mutual dissolution of aluminum and silicon is reduced.
Fig. 2 a-2 g are schematic structural diagrams illustrating steps of a method for manufacturing a semiconductor structure according to a first embodiment of the present utility model.
In step S01, an epitaxial layer is formed on a substrate and a first oxide layer is formed on the epitaxial layer.
Referring to fig. 2a, an epitaxial layer 102 is formed on a substrate 101 and a first oxide layer 121 is formed on the epitaxial layer 101.
In this embodiment, the substrate 101 may be any suitable type of semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, or the like. The substrate 101 and the epitaxial layer 102 have a first doping type.
The embodiment of the utility model is described by taking the first doping type as N-type doping and the second doping type as P-type doping as an example, but the utility model is not limited to the example. The substrate 101 is a heavily doped structure and the epitaxial layer 102 is a lightly doped structure. The thickness of the epitaxial layer 102 is 1 μm to 50 μm, and the resistivity is 0.1 Ω·cm to 100 Ω·cm. Growing a first oxide layer 121 on the epitaxial layer 102, the first oxide layer 121 having a thickness ofThe growth temperature is, for example, 900℃to 1250 ℃.
In step S02, a field oxide layer 103 and a second oxide layer 122 are formed on the epitaxial layer and a base region is formed in the epitaxial layer, wherein the field oxide layer 103 defines a region of the base region.
Referring to fig. 2b, a patterned photoresist is formed on the first oxide layer 121, and the first oxide layer 121 is etched to form a base window, the remaining first oxide layer 121 is used as the field oxide layer 103, and the thickness of the field oxide layer 103 isAfter removing the photoresist, a second oxide layer 122 is grown on the epitaxial layer 102 in the base region window at a high temperature, the thickness of the second oxide layer 122 is +.>The growth temperature is, for example, 800℃to 1250 ℃. The epitaxial layer 102 is subjected to ion implantation through the base window to form an intrinsic base region 104, wherein the implanted ions are boron or BF 2 + The implantation energy is 20 keV-150 keV, the implantation dosage is 1E11cm -2 ～1E16cm -2 。
A patterned photoresist is formed on the second oxide layer 122, and is etched to form a concentrated base window through which an extrinsic base 106 is formed by ion implantation, which is boron or BF 2 + The implantation energy is 20 keV-150 keV, the implantation dosage is 1E14cm -2 ～1E16cm -2 。
The intrinsic base region 104 and the extrinsic base region 106 extend downward from the surface of the epitaxial layer 102. The intrinsic base region 104 and the extrinsic base region 106 are doped with a second doping type, the extrinsic base region 106 having a higher doping concentration than the intrinsic base region 104.
In step S03, a dielectric layer 105 is formed on the base region.
Referring to fig. 2c, the second oxide layer 122 is removed, and a third oxide layer 123 is grown on the base region by LPCVD or PECVD deposition, the thickness of the third oxide layer 123 beingIn a practical process, when the second oxide layer 123 is grown on the base region, the second oxide layer 123 is also grown on the field oxide layer 103, so that the field oxide layer 103 becomes thicker (not shown in the figure). And adopting high-temperature annealing at 800-1000 ℃ to control the junction depth of the intrinsic base region 104 and the extrinsic base region 106 to be 0.5-5 mu m, wherein the junction depth of the extrinsic base region 106 is deeper than the junction depth of the intrinsic base region 104.
Referring to fig. 2d, the third oxide layer 123 is dry etched to reduce the thickness of the third oxide layer 123, and then the third oxide layer 123 is wet etched to form the dielectric layer 105 and the opening in the dielectric layer 105. In this step, the dry etching process and then the wet etching process are adopted, so that the dry etching damage on the surface of the epitaxial layer 102 can be effectively avoided.
In step S04, an emitter region is formed and base poly and emitter poly are formed on the base region and the emitter region.
Referring to fig. 2e, polysilicon 130 is grown on field oxide layer 103 and dielectric layer 105, the thickness of polysilicon 130 beingThe growth temperature is, for example, 500℃to 800 ℃.
Referring to fig. 2f, a photoresist is formed on the polysilicon 130, and the photoresist is etched to form a base window, and the polysilicon 130 is implanted with a second conductivity type impurity, such as boron or BF, through the base window to form the base polysilicon 108 2 + The implantation energy is 20 keV-150 keV, the implantation dosage is 1E11cm -2 ～1E16cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The photoresist is removed. Then forming photoresist on the polysilicon 130, etching the photoresist to form an emitter window, implanting first conductivity type impurities such as arsenic, phosphorus or a combination of arsenic and phosphorus into the polysilicon 130 through the emitter window to form an emitter polysilicon 109, wherein the implantation energy is 20-200 keV, and the implantation dosage is 1E14cm -2 ～5E16cm -2 . After removing the photoresist, a Rapid Thermal Anneal (RTA), for example, a rapid thermal anneal at 900-1200 ℃ for 1-60 s, is performed to appropriately push the first conductivity type impurities implanted into the polysilicon 130 into the intrinsic base region 104, forming the emitter region 107. At the same time, the rapid thermal anneal also allows for more complete diffusion of the second conductivity type impurities in the base poly 108.
The extrinsic base regions 106 are located on both sides of the intrinsic base region 104 and are in contact with the intrinsic base region 104, and the intrinsic base region 104 surrounds the emitter region 107 and is in contact with the emitter region 107. The emitter region 107 is spaced apart from the extrinsic base region 106. The extrinsic base region 106 may reduce base resistance and increase the frequency of the semiconductor structure.
In step S05, a base and an emitter are formed, and a passivation layer and a collector are formed.
Referring to fig. 2g, a metal layer is grown on the polysilicon 130, and the thickness of the metal layer is 0.5 μm to 5 μm. The metal layer and polysilicon 130 are etched at a time to form base poly 108, emitter poly 109, and base 110 and emitter 111 such that base 110 and base poly 108 are fully aligned and emitter 111 and emitter poly 109 are fully aligned.
Referring to fig. 2h, a passivation layer 112 is formed on the field oxide layer 103, the dielectric layer 105, the base 110, and the emitter 111 such that the base 110 and the emitter 111 are spaced apart from each other. The passivation layer 112 has a thickness of, for example, 0.5um to 5um. And thinning the substrate 101 and forming a collector 113 on the back surface (the surface on the side away from the epitaxial layer 102) of the substrate 101. The thickness of the collector 113 is, for example, 0.5um to 5um.
Fig. 3 is a schematic structural diagram of a semiconductor structure according to another embodiment of the present utility model. In contrast to the embodiment shown in fig. 1, the extrinsic base regions 106 and the emitter regions 107 in this embodiment are alternately arranged at intervals, and the extrinsic base regions 106 are located outermost.
The rest of the present embodiment is the same as the previous embodiment, and will not be described here again.
Embodiments in accordance with the present utility model, as described above, are not intended to be exhaustive or to limit the utility model to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the utility model and the practical application, to thereby enable others skilled in the art to best utilize the utility model and various modifications as are suited to the particular use contemplated. The scope of the utility model should be determined by the following claims.
Claims (14)
1. A semiconductor structure, comprising:
a substrate having a first doping type;
an epitaxial layer on the substrate, the epitaxial layer having a first doping type;
the base region and the emitter region are positioned in the epitaxial layer, wherein the emitter region is in contact with the base region, the emitter region has a first doping type, the base region has a second doping type, and the first doping type is opposite to the second doping type;
the field oxide layer is positioned on the epitaxial layer and is used for limiting a base region;
a base poly on the base region and an emitter poly on the emitter region, the base poly having a second doping type and the emitter poly having a first doping type;
and the dielectric layer is positioned on the base region and isolates the emitter polycrystal from the base polycrystal.
2. The semiconductor structure of claim 1, wherein the base region comprises an intrinsic base region and an extrinsic base region, the extrinsic base region having a higher doping concentration than the intrinsic base region.
3. The semiconductor structure of claim 2, wherein the extrinsic base regions are located on either side of and in contact with the intrinsic base region, the intrinsic base region surrounding and in contact with the emitter region.
4. The semiconductor structure of claim 2, wherein the extrinsic base regions and the emitter regions are located in the intrinsic base region and are alternately spaced apart, and the extrinsic base regions are located outermost.
5. The semiconductor structure of claim 2, wherein a junction depth of the intrinsic base region and the extrinsic base region is 0.5 μm to 5 μm, the extrinsic base region having a junction depth deeper than a junction depth of the intrinsic base region.
6. The semiconductor structure of claim 1, wherein a thickness of the base poly and the emitter poly is
7. The semiconductor structure of claim 1, wherein the field oxide layer has a thickness of
8. The semiconductor structure of claim 1, wherein the dielectric layer has a thickness of
9. The semiconductor structure of claim 1, wherein the epitaxial layer has a thickness of 1 μm to 50 μm and a resistivity of 0.1 Ω -cm to 100 Ω -cm.
10. The semiconductor structure of claim 1, further comprising:
a base on the base poly and an emitter on the emitter poly, the base being in perfect alignment with the base poly and the emitter being in perfect alignment with the emitter poly;
the passivation layer is positioned on the field oxide layer, the dielectric layer, the base electrode and the emitter;
and a collector electrode positioned on a side of the substrate away from the surface of the epitaxial layer.
11. The semiconductor structure of claim 1, wherein the first doping type is N-type and the second doping type is P-type; or the first doping type is P type, and the second doping type is N type.
12. The semiconductor structure of claim 1, wherein the semiconductor structure is a radio frequency transistor.
13. An integrated circuit comprising at least one semiconductor structure as claimed in any one of claims 1 to 12.
14. The integrated circuit of claim 13, wherein the integrated circuit is a BICMOS circuit or a BCD circuit.
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| CN202320182325.0U CN219393403U (en) | 2023-01-13 | 2023-01-13 | Semiconductor structure and integrated circuit |
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