CN219329013U

CN219329013U - Power supply control circuit and solid state disk

Info

Publication number: CN219329013U
Application number: CN202223211788.XU
Authority: CN
Inventors: 孙成思; 李振华; 刘冲
Original assignee: Biwin Storage Technology Co Ltd
Current assignee: Biwin Storage Technology Co Ltd
Priority date: 2022-11-29
Filing date: 2022-11-29
Publication date: 2023-07-11
Anticipated expiration: 2032-11-29

Abstract

The utility model discloses a power supply control circuit and a solid state disk. The input end of the delay unit is electrically connected with the power supply, the output end of the delay unit is electrically connected with the control unit, and the delay unit is used for delaying the voltage change speed of the output end of the delay unit; the control unit is electrically connected with the enabling end of each voltage conversion unit and is used for sequentially controlling each voltage conversion unit to start (or stop) working in sequence in the rising (or falling) process of the voltage of the output end of the delay unit; the input end of each voltage conversion unit is electrically connected with a power supply, the output ends are respectively electrically connected with different power supply output ends, the sampling end of at least one voltage conversion unit is electrically connected with a resistance value adjusting unit, and the resistance value adjusting unit is used for adjusting the partial pressure duty ratio of the sampling end. The technical scheme of the utility model can realize power on and off time sequence control on multiple power supply output ends and realize the bias voltage test function of each power supply circuit.

Description

Power supply control circuit and solid state disk

Technical Field

The present utility model relates to the field of chip power technologies, and in particular, to a power supply control circuit and a solid state disk.

Background

In the prior art, multiple paths of working voltages are arranged in the processing chip, and in order to ensure reliable operation of the chip, the power-on and power-off of each path of working voltage usually need to follow a certain time sequence, otherwise, excessive current at the power-on stage, abnormal device starting and irreversible damage to the chip can occur when the product is used.

In the prior art, in order to realize the time sequence of power up and power down, a PMIC (Power Management IC, integrated power management circuit) power chip is generally adopted for driving, but the power chip generally only meets the power-on requirement of the chip, and when the chip needs to be subjected to ageing verification, the bias test of the chip cannot be realized, and the function is single.

Disclosure of Invention

The utility model provides a power supply control circuit and a solid state disk, and aims to solve the problem that the pull bias of voltage and the upper and lower power sequence control requirements cannot be met simultaneously in the prior art.

In order to achieve the above object, a first aspect of the present utility model provides a power supply control circuit, including a delay unit, a control unit, at least two voltage conversion units, and at least one resistance adjustment unit; wherein,,

the input end of the delay unit is electrically connected with a power supply, the output end of the delay unit is electrically connected with the control unit, and the delay unit is used for delaying the voltage change speed of the output end of the delay unit;

the control unit is electrically connected with the enabling ends of the voltage conversion units and is used for sequentially controlling the voltage conversion units to start working in sequence in the rising process of the voltage of the output end of the delay unit and sequentially controlling the voltage conversion units to stop working in sequence in the falling process of the voltage of the output end of the delay unit;

the input end of each voltage conversion unit is electrically connected with a power supply, the output end of each voltage conversion unit is electrically connected with different power supply output ends, the sampling end of at least one voltage conversion unit is electrically connected with the resistance value adjusting unit, and the resistance value adjusting unit is used for adjusting the partial pressure duty ratio of the sampling end.

In some embodiments, the control unit includes a plurality of sub-control units, each of the sub-control units corresponds to each of the voltage conversion units one by one, the sub-control units are electrically connected between an enabling end of the corresponding voltage conversion unit and an output end of the delay unit, and when the output voltage of the delay unit reaches a respective voltage threshold, the output signal controls the corresponding voltage conversion unit to start working; the voltage threshold values of the sub-control units are different.

In some embodiments, the sub-control units each include a voltage comparator, a v+ pin of the voltage comparator is electrically connected to an output end of the delay unit, a V-pin receives a reference voltage provided by a power supply, and an output pin is electrically connected to an enable end of the corresponding voltage conversion unit; the reference voltages of the V-pins of the voltage comparators are different.

In some embodiments, the resistance value adjusting unit includes a gear change switch and a pull-down unit, the pull-down unit having a plurality of gears of different pull-down resistance values, the gear change switch being electrically connected between the sampling end and the pull-down unit for switching the gear of the pull-down unit.

In some embodiments, the pull-down unit includes at least a standard gear resistor, a pull-down gear resistor, and a pull-up gear resistor; the gear change-over switch is a jump cap regulating switch and comprises a first jump wire pin, a second jump wire pin, a third jump wire pin and a jump wire cap electrically connected with the sampling end, wherein the first jump wire pin is grounded through the standard gear resistor, the second jump wire pin is grounded through the pull-down gear resistor, and the third jump wire pin is grounded through the pull-up gear resistor.

In some embodiments, the delay unit includes a first resistor and a first capacitor, one end of the first resistor is an input end of the delay unit, the other end of the first resistor is an output end of the delay unit, and the other end of the first resistor is grounded through the first capacitor.

In some embodiments, the at least two voltage conversion units include a first voltage conversion unit and a second voltage conversion unit, and a sampling end of the second voltage conversion unit is electrically connected with the resistance value adjusting unit;

the first voltage conversion unit comprises an LDO chip, a first pull-up resistor, a first voltage dividing resistor and a second voltage dividing resistor, wherein an enabling pin of the LDO chip is an enabling end of the first voltage conversion unit, an input pin of the LDO chip is electrically connected with a power supply through the first pull-up resistor, an output pin of the LDO chip is electrically connected with an output end of the first voltage conversion unit, a sampling pin of the LDO chip is a sampling end of the first voltage conversion unit, an output pin of the LDO chip is electrically connected with a sampling pin of the LDO chip through the first voltage dividing resistor, and a sampling pin of the LDO chip is grounded through the second voltage dividing resistor;

the second voltage conversion unit comprises a DC-DC chip, a second pull-up resistor and a third voltage dividing resistor, an enabling pin of the DC-DC chip is an enabling end of the second voltage conversion unit, an input pin of the DC-DC chip is electrically connected with a power supply through the second pull-up resistor, an output pin of the DC-DC chip is electrically connected with an output end of the second voltage conversion unit, a sampling pin of the DC-DC chip is a sampling end of the second voltage conversion unit, and an output pin of the DC-DC chip is electrically connected with a sampling pin of the DC-DC chip through the third voltage dividing resistor.

In some embodiments, the second voltage conversion unit further includes a filter inductor and a filter capacitor, wherein one end of the filter inductor is electrically connected to the output pin of the DC-DC chip, the other end of the filter inductor is electrically connected to the power supply output terminal, and the filter capacitor is connected in parallel with the third voltage dividing resistor.

In some embodiments, the output end of the voltage conversion unit is connected with a filtering circuit for filtering clutter.

The second aspect of the utility model provides a solid state disk, which comprises the power supply control circuit.

Compared with the prior art, the technical scheme of the utility model has the following beneficial effects:

(1) The power supply control circuit provided by the utility model comprises a delay unit, wherein the delay unit is used for delaying the voltage change speed of the output end of the delay unit, namely, the control unit electrically connected with the output end of the delay unit can receive different input voltages at different time points, and further, when the input voltage rises to reach a certain voltage threshold value in the control unit, the control unit can enable the voltage conversion unit corresponding to the input voltage to start to work and output the power supply voltage; or when the input voltage is lower than the voltage threshold value, the voltage conversion unit corresponding to the input voltage is cut off and enabled, and the operation is stopped. Therefore, the power-on and power-off time sequence control of different power supply circuits is achieved through a simple circuit design.

(2) The power supply control circuit provided by the utility model further comprises at least one resistance adjusting unit, wherein the resistance adjusting unit is used for adjusting the partial pressure duty ratio of the sampling end of the voltage converting unit, and the voltage converting unit can further adjust the output voltage of the voltage converting unit based on different partial pressure duty ratios. Therefore, closed-loop regulation of the output power supply voltage is formed, and in the practical application process, a user can adjust the accessed resistance value of the resistance value regulating unit and finally adjust the power supply voltage.

Drawings

FIG. 1 is a schematic diagram of a power control circuit according to an embodiment of the utility model;

FIG. 2 is a second block diagram of a power control circuit according to an embodiment of the present utility model;

fig. 3 is a schematic circuit diagram of a power supply control circuit according to an embodiment of the utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present utility model are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.

It will also be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present utility model.

Referring to fig. 1-3, the present utility model proposes a power supply control circuit, which includes a delay unit 10, a control unit 20, at least two voltage conversion units (including a first voltage conversion unit 310 and a second voltage conversion unit 320 in the drawings) and at least one resistance adjustment unit 40; wherein,,

the input end of the delay unit 10 is electrically connected with a power supply, the output end of the delay unit 10 is electrically connected with the control unit 20, and the delay unit 10 is used for delaying the voltage change speed of the output end of the delay unit;

the control unit 20 is electrically connected to the enable ends of the voltage conversion units, and is used for sequentially controlling the voltage conversion units to start working in sequence during the rising process of the output end voltage of the delay unit 10, and sequentially controlling the voltage conversion units to stop working in sequence during the falling process of the output end voltage of the delay unit 10;

the input end of each voltage conversion unit is electrically connected with a power supply, the output end of each voltage conversion unit is electrically connected with different power supply output ends respectively, the sampling end of at least one voltage conversion unit is electrically connected with a resistance value adjusting unit 40, and the resistance value adjusting unit 40 is used for adjusting the partial pressure duty ratio of the sampling end.

According to the technical scheme provided by the utility model, the voltage conversion unit is electrically connected with a power supply and is used for converting and generating the power supply voltage. The technical scheme of the utility model is provided with at least two voltage conversion units for providing two groups of different power supply voltages based on the actual situation that a processing chip in the prior art usually has multiple paths of working voltages.

Next, a delay unit 10 and a control unit 20 electrically connected to the output end of the delay unit 10 are provided, and the output end of the control unit 20 is connected to the enable end of the voltage conversion unit. The delay unit 10 has an effect of delaying the voltage change speed of the output end thereof, that is, the control unit 20 electrically connected with the output end of the delay unit 10 receives different input voltages at different time nodes, so that the control unit 20 can control different voltage conversion units to start or stop working based on the different input voltages of the different time nodes, thereby achieving the power-on and power-off time sequence control of the multi-path power supply circuit.

In addition, a resistance value adjusting unit 40 is further provided, and as the name implies, the resistance value adjusting unit 40 can change the resistance values with different sizes, so that the user can freely select based on the actual requirements. The resistance value adjusting unit 40 adjusts the partial pressure ratio of the sampling end of the voltage converting unit by adjusting the resistance value, and further adjusts the output end voltage of the voltage converting unit in closed loop adjustment to meet the actual use requirement, such as being applicable to bias voltage test operation requiring different power supply voltages.

In summary, the power supply control circuit provided by the application not only can meet the power on and off time sequence control of different power supply circuits, but also can control different voltage outputs of different power supply circuits through circuit structure design, and meets the actual use requirements of the power supply control circuit such as bias voltage test operation.

Referring to fig. 2 and 3, in some embodiments, the control unit 20 includes a plurality of sub-control units (including a first sub-control unit 210 and a second sub-control unit 220 in the drawings), where each sub-control unit corresponds to each voltage conversion unit one by one, the sub-control units are electrically connected between an enable end of the corresponding voltage conversion unit and an output end of the delay unit 10, and when the output voltage of the delay unit 10 reaches a respective voltage threshold, each sub-control unit controls the corresponding voltage conversion unit to start working by using an output signal; the voltage threshold values of the respective sub-control units are different in magnitude.

In this embodiment, the sub-control units are electrically connected between the enabling end of the corresponding voltage conversion unit and the output end of the delay unit 10, so that the input voltages received by the sub-control units at the same time point are the same, and each sub-control unit is provided with a different voltage threshold value, and after the input voltages of the sub-control units are compared with each voltage threshold value, the working states of the corresponding voltage conversion units can be controlled correspondingly under the preset condition.

In some embodiments, the sub-control units each include a voltage comparator, a v+ pin of the voltage comparator is electrically connected to an output end of the delay unit 10, the V-pin receives a reference voltage provided by a power supply, and the output pin is electrically connected to an enable end of the corresponding voltage conversion unit; the reference voltages of the V-pins of the voltage comparators are different.

In this embodiment, the power supply provides a reference voltage to the V-pins of the voltage comparators, and in some embodiments, the V-pins of the voltage comparators are electrically connected to the same output terminal of the power supply, and different voltage dividing modules are disposed between the V-pins of the voltage comparators and the output terminal of the power supply, so that the V-pins of the voltage comparators receive the reference voltages with different magnitudes (i.e. the voltage threshold is provided through the V-pins).

The at least two voltage converting units include a first voltage converting unit 310 and a second voltage converting unit 320, and the sub-control unit includes a first voltage comparator U1 having an output terminal electrically connected to the first voltage converting unit 310, and a second voltage comparator U3 having an output terminal electrically connected to the second voltage converting unit 320. The V-pin of the first voltage comparator U1 provides a first voltage threshold, and the V-pin of the second voltage comparator U3 provides a second voltage threshold. In the power-up process, the voltage at the output end of the delay unit 10 starts to rise from 0, when the first voltage threshold is reached, the first voltage comparator U1 enables to control the first voltage conversion unit 310 to start working and output the first supply voltage, while the voltage at the output end of the delay unit 10 continues to rise, and when the second voltage threshold is reached, the second voltage comparator U3 enables to control the second voltage conversion unit 320 to start working and output the second supply voltage. Because the voltage at the output terminal of the delay unit 10 is changed from the first voltage threshold to the second voltage threshold, a certain time interval is provided, so that different power-on time sequence control is formed. Further, during power-down, the voltage at the output end of the delay unit 10 gradually decreases from a maximum value to 0, when the voltage at the output end of the delay unit 10 decreases to a second voltage threshold value, the second voltage comparator U3 stops enabling the second voltage conversion unit 320, the second voltage conversion unit 320 stops working, and when the voltage at the output end of the delay unit 10 continues to decrease below a first voltage threshold value, the first voltage comparator U1 stops enabling the first voltage conversion unit 310, and the first voltage conversion unit 310 stops working, so as to form different power-down timing control.

In some embodiments, the resistance adjusting unit 40 includes a gear change switch K and a pull-down unit, wherein the pull-down unit has a plurality of gears with different pull-down resistances, and the gear change switch K is electrically connected between the sampling end and the pull-down unit for switching the gear of the pull-down unit.

Further, the pull-down unit at least comprises a standard gear resistor R8, a pull-down gear resistor R7 and a pull-up gear resistor R9; the gear change-over switch K is a jump cap regulating switch and comprises a first jump wire pin, a second jump wire pin, a third jump wire pin and a jump wire cap electrically connected with the sampling end, wherein the first jump wire pin is grounded through a standard gear resistor R8, the second jump wire pin is grounded through a pull-down gear resistor R7, and the third jump wire pin is grounded through a pull-up gear resistor R9.

In the embodiment, the circuit paths of the sampling end and the resistors with different gears are further realized through the connection of the jumper caps and the different jumper pins, so that the purpose of adjusting the voltage division duty ratio of the sampling end is achieved. It can be understood that when the standard gear resistor R8 is connected, the output voltage of the output end of the voltage conversion unit is the normal working voltage; when the pull-down gear resistor R7 is connected, the output voltage of the output end of the voltage conversion unit is lower than the normal working voltage; when the pull-up gear resistor R9 is connected, the output voltage of the output end of the voltage conversion unit is higher than the normal working voltage. And further, the resistance value adjusting unit 40 is used for meeting the practical application requirements of the pulling bias test operation.

In some embodiments, the delay unit 10 includes a first resistor R1 and a first capacitor C1, one end of the first resistor R1 is an input end of the delay unit 10, the other end of the first resistor R1 is an output end of the delay unit 10, and the other end of the first resistor R1 is grounded through the first capacitor C1.

In this embodiment, a simple RC delay circuit is formed by the first resistor R1 and the first capacitor C1, and the RC delay process is a charging and discharging process of the first capacitor C1, according to a capacitance charging and discharging formula:

vt=v0+ (V1-V0) [ 1-exp (a t/R C) ]

Wherein V0 is an initial voltage value on the capacitor, V1 is a voltage value that the capacitor can be charged or discharged finally, vt is a voltage value on the capacitor at time t, and r×c is a time constant of the RC delay circuit. The parameter of the other one of the RC delay circuits can be calculated by configuring any two of three variable quantities of the input voltage of the RC delay circuit, the first resistor R1 and the first capacitor C1.

In some embodiments, the at least two voltage conversion units include a first voltage conversion unit 310 and a second voltage conversion unit 320, and a sampling end of the second voltage conversion unit 320 is electrically connected to the resistance adjustment unit 40.

The first voltage conversion unit 310 includes an LDO chip U2, a first pull-up resistor R2, a first voltage dividing resistor R3, and a second voltage dividing resistor R4, an enable pin of the LDO chip U2 is an enable end of the first voltage conversion unit 310, an input pin of the LDO chip U2 is electrically connected to a power supply through the first pull-up resistor R2, an output pin of the LDO chip U2 is electrically connected to an output end of the first voltage conversion unit 310, a sampling pin of the LDO chip U2 is a sampling end of the first voltage conversion unit 310, and an output pin of the LDO chip U2 is electrically connected to a sampling pin thereof through the first voltage dividing resistor R3, and a sampling pin of the LDO chip U2 is grounded through the second voltage dividing resistor R4.

The second voltage conversion unit 320 includes a DC-DC chip U4, a second pull-up resistor R5, and a third voltage dividing resistor R6, an enable pin of the DC-DC chip U4 is an enable end of the second voltage conversion unit 320, an input pin of the DC-DC chip U4 is electrically connected to a power supply through the second pull-up resistor R5, an output pin of the DC-DC chip U4 is electrically connected to an output end of the second voltage conversion unit 320, a sampling pin of the DC-DC chip U4 is a sampling end of the second voltage conversion unit 320, and an output pin of the DC-DC chip U4 is electrically connected to a sampling pin thereof through the third voltage dividing resistor R6.

In this embodiment, the resistance adjusting unit 40 is electrically connected to the sampling end of the second voltage converting unit 320, and the first voltage converting unit 310 employs the LDO chip U2, and the second voltage converting unit 320 employs the DC-DC chip U4. The LDO chip U2 is generally used for a circuit with a smaller input/output voltage difference, and the first voltage converting unit 310 outputs a stable voltage in combination with feedback adjustment of the first voltage dividing resistor R3 and the second voltage dividing resistor R4.

Based on the circuit structure design, the working process of the first voltage conversion unit 310 is as follows: the first voltage comparator U1 enables the LDO chip U2, the LDO chip U2 starts to operate, the power voltage is input through the input pin of the LDO chip U2 and is output to the output end of the first voltage converting unit 310 through the output pin after being converted by the LDO chip U2, and the sampling pin of the LDO chip U2 can feedback and regulate the output of the LDO chip U2 by sampling the voltage of the second voltage dividing resistor R4.

Similarly, the second voltage converting unit 320 operates as follows: the second voltage comparator U3 enables the DC-DC chip U4, the DC-DC chip U4 starts to operate, the power voltage is input through the input pin of the DC-DC chip U4 and is output to the output end of the first voltage conversion unit 310 through the output pin after being converted by the DC-DC chip U4, and the sampling pin of the DC-DC chip U4 can feedback and regulate the output of the DC-DC chip U4 by sampling the voltage of the resistance value regulating unit 40.

In some embodiments, the second voltage converting unit 320 further includes a filter inductor L1 and a filter capacitor C2, where one end of the filter inductor L1 is electrically connected to the output pin of the DC-DC chip U4, the other end is electrically connected to the output end of the second voltage converting unit 320, and the filter capacitor C2 is connected in parallel with the third voltage dividing resistor R6.

In some embodiments, the output terminal of the voltage conversion unit is connected to a filter circuit, and the filter circuit includes a capacitor disposed at the output terminal of the voltage conversion unit, where the capacitor is provided with a plurality of capacitors for filtering output clutter to form a stable output.

The power supply control of the LPDDR5 chip will be specifically described below.

LPDDR full scale Low Power Double Data Rate is a communication standard formulated by JEDEC solid state technology society for low power consumption memories, and is specially used for mobile electronic products, namely "low power consumption memories". While LPDDR5 is the latest standard, there are three sets of voltages inside LPDDR 5: VDD1, VDD2 and VDDQ; when the aging verification is performed on the LPDDR5 chip, the bias pulling test is mainly performed on the VDDQ. In combination with specific requirements, an up-down power sequence circuit suitable for LPDDR5 chip bias test is provided, and the structure of the up-down power sequence circuit mainly aims at two power supply circuits, namely VDD2 and VDDQ, and specifically referring to fig. 3, the up-down power sequence circuit comprises:

the RC delay unit 10 includes a first resistor R1 and a first capacitor C1, where the resistance value of the first resistor R1 is 1k, the capacitance value of the capacitor C1 is 10uf, and the connection structure of the RC delay unit 10 can be set with reference to the RC delay unit 10. The input voltage at one end of the first resistor R1 is 1.8V.

R*C＝R2*C1＝1000×0.01＝10ms

I.e. the RC delay unit 10 takes 10ms for the subsequent circuit to rise from voltage 0 to voltage 1.8V.

The control unit 20 includes a first voltage comparator U1 and a second voltage comparator U3, v+ pins of the first voltage comparator U1 and the second voltage comparator U3 are connected to an output end of the RC delay unit 10, V-pins are connected to a power supply, and an output voltage of the power supply is 3.3V, wherein a voltage dividing module is connected between the power supply and the V-pins of the voltage comparators, so that the V-pin of the first voltage comparator U1 can provide a reference voltage of 1.1V, and the V-pin of the second voltage comparator U3 can provide a reference voltage of 1.7V.

The voltage conversion unit includes a first voltage conversion unit 310 and a second voltage conversion unit 320, where the circuit structures of the first voltage conversion unit 310 and the second voltage conversion unit 320 are set with reference to the above circuit structures, and are not described herein, the input voltages of the LDO chip U2 and the DC-DC chip U4 are 3.3v, the sampling pin of the DC-DC chip U4 is connected to the resistance adjustment unit 40, the resistance of the first voltage dividing resistor R3 is 30Ω, the resistance of the second voltage dividing resistor R4 is 100deg.Ω, the resistance of the third voltage dividing resistor R6 is 300Ω, the resistance of the standard gear resistor R8 is 1.5k, the resistance of the pull-down gear resistor R7 is 1.2k, and the resistance of the pull-up gear resistor R9 is 1k.

It is understood that the power supply circuit of the first voltage converting unit 310 is a VDD2 power supply circuit, and the power supply circuit of the second voltage converting unit 320 is a VDDQ power supply circuit.

According to the voltage output formula vout=k (1+ra/RB), the supply voltage of VDD2 is calculated:

k=0.8 is a constant value determined based on the LDO regulator chip U2, and VDD 2=1.05v is a normal supply voltage of the VDD2 supply circuit in the LPDDR5 chip.

And according to the voltage output formula vout=k (1+ra/RB), the supply voltages of three VDDQ groups can be obtained by calculation:

wherein k=0.4 is a constant value determined based on the DC-DC chip U4; vddq1=0.48V is a pull-down test voltage, vddq2=0.5V is a normal operation voltage, and vddq3=0.52V is a pull-up test voltage.

Therefore, for the power supply control of the LPDDR5 chip, the working principle is as follows: firstly, the power-on start-up voltage of 1.8V is provided by a power supply, 1.8V is charged through the RC delay unit 10, when the voltage of the V+ end in the first voltage comparator U1 and the second voltage comparator U3 reaches 1.1V, the enabling pin of the LDO chip U2 is pulled up, the VDD2 normally outputs 1.05V to supply power to the VDD2, and the voltage of 1.05V is determined by the first voltage dividing resistor R3 and the second voltage dividing resistor R4. When the V+ end in the first voltage comparator U1 and the second voltage comparator U3 reaches 1.7V, the enabling pin of the DC-DC chip U4 is pulled high, and 0.5V is normally output to supply power to the VDDQ when the sampling pin of the DC-DC chip U4 is connected with the standard gear resistor R8, so that sequential power-up is realized. Similarly, the sampling pin of the DC-DC chip U4 can be connected with a pull-down gear resistor R7 and a pull-up gear resistor R9, and voltage switching is realized through a jump cap, so that the voltage output is respectively pulled up to 0.52V or pulled down to 0.48V.

When the chip is powered down, the output voltage of the RC delay unit 10 is firstly reduced to below 1.7V, the voltage of the V+ terminal of the second voltage comparator U3 is lower than the voltage of the V-terminal, the DC-DC chip U4 stops working, and the VDDQ is firstly powered off. The voltage of the output end of the RC delay circuit is continuously reduced, when the voltage is lower than 1.1V, the voltage of the V+ end of the first voltage comparator U1 is lower than the voltage of the V-end, the LDO chip U2 stops working, and the VDD2 is powered down, so that sequential power failure is realized.

The utility model further provides a solid state disk, which comprises a power supply control circuit, and the specific structure of the power supply control circuit refers to the embodiment, and because the solid state disk adopts all the technical schemes of all the embodiments of the power supply control circuit, the solid state disk at least has all the beneficial effects brought by the technical schemes of the embodiments, and the detailed description is omitted.

The above description of the preferred embodiments of the present utility model should not be taken as limiting the scope of the utility model, but rather should be understood to cover all modifications, variations and adaptations of the present utility model using its general principles and the following detailed description and the accompanying drawings, or the direct/indirect application of the present utility model to other relevant arts and technologies.

Claims

1. The power supply control circuit is characterized by comprising a delay unit, a control unit, at least two voltage conversion units and at least one resistance value adjusting unit; wherein,,

2. The power supply control circuit according to claim 1, wherein the control unit comprises a plurality of sub-control units, each sub-control unit corresponds to each voltage conversion unit one by one, the sub-control units are electrically connected between an enabling end of the corresponding voltage conversion unit and an output end of the delay unit, and each sub-control unit controls the corresponding voltage conversion unit to start working when the output voltage of the delay unit reaches a respective voltage threshold value; the voltage threshold values of the sub-control units are different.

3. The power supply control circuit according to claim 2, wherein the sub-control units each comprise a voltage comparator, a v+ pin of the voltage comparator is electrically connected to an output end of the delay unit, the V-pin receives a reference voltage provided by a power supply, and the output pin is electrically connected to an enable end of a corresponding voltage conversion unit; the reference voltages of the V-pins of the voltage comparators are different.

4. The power supply control circuit according to claim 1, wherein the resistance value adjusting unit includes a shift position changeover switch and a pull-down unit having a plurality of shift positions of different pull-down resistance values, the shift position changeover switch being electrically connected between the sampling end and the pull-down unit for switching selection of the shift position of the pull-down unit.

5. The power supply control circuit of claim 4, wherein the pull-down unit comprises at least a standard gear resistor, a pull-down gear resistor, and a pull-up gear resistor; the gear change-over switch is a jump cap regulating switch and comprises a first jump wire pin, a second jump wire pin, a third jump wire pin and a jump wire cap electrically connected with the sampling end, wherein the first jump wire pin is grounded through the standard gear resistor, the second jump wire pin is grounded through the pull-down gear resistor, and the third jump wire pin is grounded through the pull-up gear resistor.

6. The power supply control circuit according to claim 1, wherein the delay unit includes a first resistor and a first capacitor, one end of the first resistor is an input end of the delay unit, the other end of the first resistor is an output end of the delay unit, and the other end of the first resistor is grounded through the first capacitor.

7. The power supply control circuit according to claim 1, wherein the at least two voltage conversion units include a first voltage conversion unit and a second voltage conversion unit, and a sampling end of the second voltage conversion unit is electrically connected to the resistance value adjustment unit;

8. The power supply control circuit according to claim 7, wherein the second voltage conversion unit further includes a filter inductance and a filter capacitance, one end of the filter inductance is electrically connected to the output pin of the DC-DC chip, the other end is electrically connected to the power supply output terminal, and the filter capacitance is connected in parallel with the third voltage dividing resistor.

9. The power supply control circuit according to claim 1, wherein the output end of the voltage conversion unit is connected to a filter circuit for filtering noise.

10. A solid state disk, wherein the solid state disk comprises the power supply control circuit of any one of claims 1-9.