CN219181489U

CN219181489U - Small-size dual-output low-noise frequency demultiplier

Info

Publication number: CN219181489U
Application number: CN202223487651.7U
Authority: CN
Inventors: 叶远龙
Original assignee: Zhuhai Pusisaite Technology Co ltd
Current assignee: Zhuhai Pusisaite Technology Co ltd
Priority date: 2022-12-26
Filing date: 2022-12-26
Publication date: 2023-06-13
Anticipated expiration: 2032-12-26

Abstract

The utility model discloses a small-volume dual-output low-noise frequency reducer, which comprises a polarization probe module, a radio frequency module, a phase-lock device module and an output module, wherein the polarization probe module comprises a V polarization probe and an H polarization probe, the radio frequency module comprises a first radio frequency unit and a second radio frequency unit, the first radio frequency unit is connected with the V polarization probe, the second radio frequency unit is connected with the H polarization probe, the output module comprises a first output unit and a second output unit, the first output unit comprises a first voltage stabilizing circuit, the first voltage stabilizing circuit is connected with the phase-lock device module, the second output unit comprises a second voltage stabilizing circuit, the second voltage stabilizing circuit is connected with the phase-lock device module, and the phase-lock device module is respectively connected with the first output unit and the second output unit. The utility model reduces the application of peripheral electronic circuits, reduces the power consumption, greatly reduces the cost of the frequency demultiplier, greatly enhances the market competitiveness of the double-output frequency demultiplier and can be widely applied to the technical field of satellite communication.

Description

Small-size dual-output low-noise frequency demultiplier

Technical Field

The utility model relates to the technical field of satellite communication, in particular to a small-size dual-output low-noise frequency demultiplier.

Background

With the development of science and technology and life, communication is increasingly popularized, satellite television is also in higher proportion, and the satellite television is used as a frequency demultiplier in satellite television receiving equipment, and with electronic semiconductor devices and circuit designs are becoming mature. From the traditional DRO medium oscillation design to the current PLL phase-locked loop circuit design, the design of the frequency demultiplier is more and more concise and stable. However, the raw materials and manufacturing cost of the current frequency reducer are high, and the competitive power of the product in the market is seriously affected.

Disclosure of Invention

Accordingly, an object of the embodiments of the present utility model is to provide a small-sized dual-output low-noise frequency demultiplier, which reduces the cost of die-casting materials by reducing the frequency demultiplier from the aspect of the mechanism.

The embodiment of the utility model provides a small-volume dual-output low-noise frequency reducer, which comprises a polarization probe module, a radio frequency module, a phase-lock device module and an output module, wherein the polarization probe module comprises a V polarization probe and an H polarization probe, the radio frequency module comprises a first radio frequency unit and a second radio frequency unit, the first radio frequency unit is connected with the V polarization probe, the second radio frequency unit is connected with the H polarization probe, the output module comprises a first output unit and a second output unit, the first output unit comprises a first voltage stabilizing circuit, the first voltage stabilizing circuit is connected with the phase-lock device module, the second output unit comprises a second voltage stabilizing circuit, the second voltage stabilizing circuit is connected with the phase-lock device module, and the phase-lock device module is respectively connected with the first output unit and the second output unit.

Optionally, the first radio frequency unit and the second radio frequency unit each include a chip KTD354.

Optionally, the phase-lock module includes a chip KTD1052M and a chip KTD1052M peripheral circuit.

Optionally, the phase-lock module includes a signal reference circuit, and the signal reference circuit is connected with the chip KTD 1052M.

Optionally, the first voltage stabilizing circuit and the second voltage stabilizing circuit each comprise a 78L06 chip.

Optionally, the polarized probe module, the radio frequency module, the phase lock module and the output module are all integrated on a PCB board.

Optionally, the raw materials for manufacturing the PCB board comprise FR4 board.

Optionally, the first output unit and the second output unit each comprise separate circuits.

The embodiment of the utility model has the following beneficial effects: the embodiment of the utility model provides a small-volume dual-output low-noise frequency reducer, which comprises a polarization probe module, a radio frequency module, a phase-lock device module and an output module, wherein the polarization probe module comprises a V polarization probe and an H polarization probe, the radio frequency module comprises a first radio frequency unit and a second radio frequency unit, the first radio frequency unit is connected with the V polarization probe, the second radio frequency unit is connected with the H polarization probe, the output module comprises a first output unit and a second output unit, the first output unit comprises a first voltage stabilizing circuit, the first voltage stabilizing circuit is connected with the phase-lock device module, the second output unit comprises a second voltage stabilizing circuit, the second voltage stabilizing circuit is connected with the phase-lock device module, and the phase-lock device module is respectively connected with the first output unit and the second output unit. The front-stage signal is amplified through the radio frequency module, low noise is achieved, other peripheral bias circuits are not needed to provide working voltage for the front-stage signal, the processing of the phase-locked device module is achieved, the circuit is simple, the number of connecting devices is small, the signal transmission loss is small, the output is more accurate through the two independent first output units and the second output units, the application of peripheral electronic circuits is reduced, the power consumption is reduced, the cost of the frequency demultiplier is greatly reduced, and the market competitiveness of the dual-output frequency demultiplier is greatly enhanced.

Drawings

FIG. 1 is a schematic block diagram of a small-sized dual-output low-noise frequency demultiplier according to an embodiment of the present utility model;

FIG. 2 is a diagram of an overall architecture of a low-volume dual-output low-noise down converter according to an embodiment of the present utility model;

FIG. 3 is a schematic diagram of a small-sized dual-output low-noise frequency demultiplier according to an embodiment of the present utility model;

fig. 4 is a schematic circuit diagram of a small-sized dual-output low-noise frequency demultiplier according to an embodiment of the present utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

In embodiments of the utility model, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present utility model, unless otherwise indicated, the meaning of "a plurality" is two or more.

Referring to fig. 1, an embodiment of the present utility model provides a small-sized dual-output low-noise frequency reducer, including a polarization probe module, a radio frequency module, a phase-lock module and an output module, where the polarization probe module includes a V-polarization probe and an H-polarization probe, the radio frequency module includes a first radio frequency unit and a second radio frequency unit, the first radio frequency unit is connected with the V-polarization probe, the second radio frequency unit is connected with the H-polarization probe, the output module includes a first output unit and a second output unit, the first output unit includes a first voltage stabilizing circuit, the first voltage stabilizing circuit is connected with the phase-lock module, the second output unit includes a second voltage stabilizing circuit, the second voltage stabilizing circuit is connected with the phase-lock module, and the phase-lock module is respectively connected with the first output unit and the second output unit.

The V-polarized probe is used for receiving satellite signals and carrying out vertical polarization, and the H-polarized probe is used for receiving satellite signals and carrying out horizontal polarization.

The first radio frequency unit is used for receiving the satellite signals with vertical polarization and amplifying the received satellite signals, and the second radio frequency unit is used for receiving the satellite signals with horizontal polarization and amplifying the received satellite signals.

The phase-lock device module is used for receiving the signal output by the first radio frequency unit and the signal output by the second radio frequency unit, processing the received signals and outputting the processed signals.

The first output unit and the second output unit are used for receiving the signals output by the phase-lock module and outputting the signals for the user side to use.

Specifically, satellite signals are received and polarized by a V-polarized probe and an H-polarized probe and then are respectively and correspondingly input to a first radio frequency unit and a second radio frequency unit of a radio frequency module to amplify the satellite signals, the amplified satellite signals are input to a phase-lock module, the phase-lock module correspondingly processes the input satellite signals to obtain required local oscillation frequencies, demodulates the required intermediate frequency signals, outputs the amplified intermediate frequency signals from a first output unit and a second output unit in two ways, a first voltage stabilizing circuit provides voltage stabilizing power supply for the first output unit, and a second voltage stabilizing circuit provides voltage stabilizing power supply for the second output unit.

Referring to fig. 1-4, optionally, the first radio frequency unit and the second radio frequency unit each include a chip KTD354.

Specifically, the chip KTD354 is a front-stage high-gain low-noise amplifier, and has the advantages of simple circuit, few connection devices, small signal transmission loss and the like. Satellite signals are received by the V/H polarization probe and then input into a radio frequency chip IC2 (KTD 354) and an IC4 (KTD 354) for low-noise amplification, so that high-gain and low-noise radio frequency signals are obtained; the satellite signal vertically polarized by the V-polarized probe is input to the 1 st pin of the radio frequency chip IC2 (KTD 354), and the satellite signal is output from the 3 rd pin of the radio frequency chip IC2 (KTD 354) after being amplified in a front stage; the satellite signal vertically polarized by the H-polarized probe is input to the 1 st pin of the radio frequency chip IC4 (KTD 354), and the satellite signal is output from the 3 rd pin of the radio frequency chip IC4 (KTD 354) after being amplified in a front stage.

Specifically, the chip KTD1052M is a dual-channel down converter applied to a tuner in a satellite television receiving system, and can mix and filter a 10.7-12.75G radio frequency signal into a 0.95-1.45G intermediate frequency signal through a 10.75GHz local oscillator signal, the chip integrates two on-chip radio frequency amplifiers, four image rejection mixers, a 4*2 switch matrix, two intermediate frequency amplifiers, two fixed frequency VCOs (voltage controlled oscillators, voltage controlled oscillator) and PLLs (Phase Locked Loop, phase-locked loops), a TP (Test Point, an external FET (Field Effect Transistor, field effect transistor) power supply circuit and the like, and the signal input end can output voltage; the chip KTD1052M processes the output polarized satellite signals to obtain double local oscillation frequencies of 10.75GHz, demodulates the intermediate frequency signals required by demodulation, and outputs the intermediate frequency signals in two ways after internal amplification; the performance is stable, the integration is high, the number of peripheral devices is small, a low-gain amplifying circuit is built in, and signal radiation and saturation distortion inside a chip are reduced to a great extent. The decoupling capacitor C5 is connected with a pin DECZ of the chip KTD1052M, the decoupling capacitor C7 is connected with a pin NEG of the chip KTD1052M, the decoupling capacitor C4 is connected with a pin DEC1 of the chip KTD1052M, and the decoupling capacitor C6 is connected with a pin CAP of the chip KTD 1052M; the signal reference circuit comprises an SMD1, a crystal oscillator SDM1 is a 25MHz crystal oscillator, and capacitors C8 and C9 are decoupling capacitors of the signal reference circuit and are used for filtering noise; the positions of V polarization and H polarization can be changed by changing the resistances of pins 2 and 3 of the chip KTD1052M to ground (namely, the original V polarization input is changed into H polarization, and the H polarization is converted into a V polarization mode); the output gain of the whole machine is adjusted by changing the resistances of pins 2 and 4 of the chip KTD1052M to the ground.

Specifically, the 78L06 chip is a three-terminal voltage-stabilizing tube, which has very high resistance until the critical reverse breakdown voltage, and the terminal voltage is almost unchanged in a certain current range when the voltage-stabilizing tube breaks down reversely, so that the voltage-stabilizing property is shown; the chip IC1 and the chip IC5 provide stable independent voltages for the output module; pin 3 (OUT) of chip IC1-78L06 is connected with pin GC of chip KTD1052M, pin 1 (IN) of chip IC1-78L06 is connected to output port 1 of the first output unit, capacitor C2 is decoupling capacitor of output end of chip IC1-78L06, filter noise of output end, capacitor C3 is decoupling capacitor of input end of chip IC1-78L06, filter noise of input end; the capacitor C1 is a coupling capacitor of the first output unit, and a signal output by the chip KTD1052M is output to an output port 1 of the first output unit after passing through the coupling capacitor; pin 1 (IN) of chip IC5-78L06 is connected to output port 2 of the second output unit, capacitor C10 is a decoupling capacitor of the output end of chip IC1-78L06, filters noise of the output end, capacitor C11 is a decoupling capacitor of the input end of chip IC1-78L06, filters noise of the input end; the capacitor C12 is a coupling capacitor of the first output unit, and the signal output by the chip KTD1052M is output to the output port 2 of the second output unit after passing through the coupling capacitor.

Specifically, the radio frequency amplification adopts an integrated chip KTD354, the phase lock device module adopts a KTD1052M chip, the V/H polarization probe, the V/H polarization radio frequency amplification circuit, the KTD1052M chip and the output module are integrated on a PCB, so that the traditional discrete devices are reduced, and the problem of mismatching among all the partial circuits is solved; meanwhile, the distance of signal transmission is shortened after integration.

Specifically, simultaneously, because the distance of signal transmission after integrating shortens for the panel requirement of PCB reduces, traditional panel needs high frequency panel LNB33, through this design, and ordinary FR4 panel can be used to the panel can reach basic same performance.

Specifically, the output port 1 and the output port 2 are respectively provided with an independent voltage stabilizing circuit, a first voltage stabilizing circuit and a second voltage stabilizing circuit, mutually independent chips IC1-78L06 and IC5-78L06, independent coupling capacitors C1 and C12, and the output of signals is not interfered with each other.

Referring to fig. 2, when satellite signal reception is performed, the down converter is externally connected with a switch, wherein a horizontal polarization signal interface of the switch is connected with a second radio frequency unit, and a vertical polarization signal interface of the switch is connected with a first radio frequency unit. The switch can receive the horizontal polarization signal after the frequency reduction processing, can also receive the vertical polarization signal after the frequency reduction processing, meets different signal receiving demands, outputs the intermediate frequency signal of the satellite television signal through two paths, meets the requirement of multiple paths, is beneficial to reducing the cost, simplifies the circuit and greatly improves the performance of the frequency lifter.

The working principle of the utility model is as follows: satellite television signal information is received by the LNB integrated main body, and the satellite signal is received by two modes of horizontal polarization or vertical polarization; the radio frequency integrated chip KTD354 is amplified and then is input into a corresponding polarized input end of the integrated phase-locked device KTD1052M for processing, the dual local oscillation frequencies of 9.75 GHz-10.6 GHz of the required local oscillation are obtained after processing, and the intermediate frequency signals required by demodulation are output in two paths after internal amplification.

The embodiment of the utility model has the following beneficial effects: the embodiment of the utility model provides a small-volume dual-output low-noise frequency reducer, which comprises a polarization probe module, a radio frequency module, a phase-lock device module and an output module, wherein the polarization probe module comprises a V polarization probe and an H polarization probe, the radio frequency module comprises a first radio frequency unit and a second radio frequency unit, the first radio frequency unit is connected with the V polarization probe, the second radio frequency unit is connected with the H polarization probe, the output module comprises a first output unit and a second output unit, the first output unit comprises a first voltage stabilizing circuit, the first voltage stabilizing circuit is connected with the phase-lock device module, the second output unit comprises a second voltage stabilizing circuit, the second voltage stabilizing circuit is connected with the phase-lock device module, and the phase-lock device module is respectively connected with the first output unit and the second output unit. The front-stage signal is amplified through the radio frequency module, so that the noise is low, other peripheral bias circuits are not needed to provide working voltage for the front-stage signal, the circuit is concise, the number of connecting devices is small, and the signal transmission loss is small; the phase-locked device module is stable in performance, high in integration, few in peripheral devices and low in gain amplification circuit, signal radiation and saturation distortion inside a chip are reduced to a great extent, output is more accurate through the two independent first output units and the two independent second output units, application of peripheral electronic circuits is reduced, power consumption is reduced, cost of the frequency demultiplier is greatly reduced, and market competitiveness of the double-output frequency demultiplier is greatly enhanced.

While the preferred embodiment of the present utility model has been described in detail, the utility model is not limited to the embodiment, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the utility model, and these modifications and substitutions are intended to be included in the scope of the present utility model as defined in the appended claims.

Claims

1. The utility model provides a dual output low noise frequency demultiplier of small volume, its characterized in that includes polarization probe module, radio frequency module, phase-lock ware module and output module, polarization probe module includes V polarization probe and H polarization probe, radio frequency module includes first radio frequency unit and second radio frequency unit, first radio frequency unit with V polarization probe is connected, second radio frequency unit with H polarization probe is connected, output module includes first output unit and second output unit, first output unit includes first voltage stabilizing circuit, first voltage stabilizing circuit with phase-lock ware module is connected, second output unit includes second voltage stabilizing circuit, second voltage stabilizing circuit with phase-lock ware module is connected, phase-lock ware module respectively with first output unit and second output unit are connected.

2. The low-volume dual-output low-noise down converter of claim 1, wherein said first and second radio frequency units each comprise a chip KTD354.

3. The low-volume dual-output low-noise down converter of claim 1, wherein the phase-lock module comprises a chip KTD1052M and a chip KTD1052M peripheral circuit.

4. A low-volume dual-output low-noise down converter according to claim 3, wherein the phase-lock module comprises a signal reference circuit, the signal reference circuit being connected to the chip KTD 1052M.

5. The low-volume dual-output low-noise down converter of claim 1, wherein the first voltage stabilizing circuit and the second voltage stabilizing circuit each comprise a 78L06 chip.

6. The low-volume dual-output low-noise down converter of claim 1, wherein the polarized probe module, the radio frequency module, the phase lock module, and the output module are all integrated on a PCB board.

7. The low-volume dual-output low-noise down converter of claim 6, wherein the PCB board is made of raw materials including FR4 board.

8. The low-volume dual-output low-noise down converter of any of claims 1-7, wherein said first output unit and said second output unit each comprise separate circuits.