CN216016996U

CN216016996U - Double-output frequency reduction circuit and frequency reducer

Info

Publication number: CN216016996U
Application number: CN202121589977.3U
Authority: CN
Inventors: 叶远龙
Original assignee: Zhuhai Pusisaite Technology Co ltd
Current assignee: Zhuhai Pusisaite Technology Co ltd
Priority date: 2021-07-13
Filing date: 2021-07-13
Publication date: 2022-03-11
Anticipated expiration: 2031-07-13

Abstract

The utility model discloses a double-output frequency-reducing circuit and a frequency demultiplier, which comprise a phase-locking integrated module, a horizontal polarization amplification module, a vertical polarization amplification module, a first output frequency-selecting module, a second output frequency-selecting module, a positioning signal access module and a microstrip power-dividing module, wherein the horizontal polarization amplification module, the vertical polarization amplification module, the first output frequency-selecting module and the second output frequency-selecting module are connected with the phase-locking integrated module, the first output frequency-selecting module is connected with a first output interface, the second output frequency-selecting module is connected with a second output interface, the positioning signal access module is connected with a positioning signal receiving antenna, the microstrip power-dividing module is connected with the positioning signal access module, and the microstrip power-dividing module is connected with the first output interface and the second output interface. The satellite positioning signal can be received by arranging the positioning signal access module, and the satellite positioning signal and the output signal of the phase locking integrated module adopt a channel common-path output mode, so that the frequency demultiplier can be managed according to the satellite positioning signal.

Description

Double-output frequency reduction circuit and frequency reducer

Technical Field

The utility model relates to the technical field of frequency demultipliers, in particular to a double-output frequency demultiplier circuit and a frequency demultiplier.

Background

With the development of science and technology and life and the popularization of communication transmission, the proportion of families watching satellite televisions is higher and higher, wherein a frequency demultiplier is a necessary device for watching the satellite televisions. However, due to the lack of effective tracking management measures for the frequency demultipliers, the installation environment of the satellite receiving equipment is disordered, and the watching of the satellite television is seriously influenced.

SUMMERY OF THE UTILITY MODEL

The present invention is directed to solving at least one of the problems of the prior art. Therefore, the utility model provides a double-output frequency reducing circuit and a frequency demultiplier, which can realize satellite positioning and are convenient to manage.

In a first aspect, a dual-output frequency-reducing circuit according to an embodiment of the present invention includes a phase-locked integrated module having a first input terminal, a second input terminal, a first output terminal, and a second output terminal; the horizontal polarization amplification module is connected with the first input end of the phase-locking integrated module; the vertical polarization amplification module is connected with the second input end of the phase-locking integrated module; the input end of the first output frequency selection module is connected with the first output end of the phase-locking integrated module, and the output end of the first output frequency selection module is connected with a first output interface; the input end of the second output frequency selection module is connected with the second output end of the phase-locking integrated module, and the output end of the second output frequency selection module is connected with a second output interface; the input end of the positioning signal access module is connected with a positioning signal receiving antenna; and the input end of the microstrip power dividing module is connected with the output end of the positioning signal access module, the first output end of the microstrip power dividing module is connected with the first output interface, and the second output end of the microstrip power dividing module is connected with the second output interface.

The dual-output frequency reducing circuit provided by the embodiment of the utility model at least has the following beneficial effects:

the satellite positioning signal can be received by arranging the positioning signal access module, and the satellite positioning signal and the output signal of the phase locking integrated module adopt a channel common-path output mode, so that the frequency demultiplier can be managed according to the satellite positioning signal.

According to some embodiments of the present invention, the positioning signal access module includes a first positioning signal amplifier, a first frequency-selective filter, and a second positioning signal amplifier, which are connected in sequence, an input end of the first positioning signal amplifier is connected to the positioning signal receiving antenna, and an output end of the second positioning signal amplifier is connected to the microstrip power division module.

According to some embodiments of the utility model, the first positioning signal amplifier and the second positioning signal amplifier both employ a Beidou satellite signal amplifier.

According to some embodiments of the utility model, the first frequency selective filter is a beidou sound table filter.

According to some embodiments of the present invention, a first coupling capacitor is connected between each of the positioning signal receiving antenna, the first positioning signal amplifier, the first frequency-selective filter, the second positioning signal amplifier, and the microstrip power dividing module.

According to some embodiments of the present invention, the microstrip power dividing module includes a microstrip power divider, a first resistor is connected between a first output end and a second output end of the microstrip power divider, a second coupling capacitor is connected between the first output end and the first output interface of the microstrip power divider, and a third coupling capacitor is connected between the second output end and the second output interface of the microstrip power divider.

According to some embodiments of the utility model, the first output frequency-selecting module and the second output frequency-selecting module are identical in structure, and the first output frequency-selecting module comprises a multi-stage LC filter circuit.

According to some embodiments of the present invention, at least one of the first output interface and the second output interface is connected to a voltage stabilizing module, an input end of the voltage stabilizing module is correspondingly connected to at least one of the first output interface and the second output interface, and an output end of the voltage stabilizing module is respectively connected to the phase-locked integration module and the positioning signal access module.

According to some embodiments of the present invention, the voltage regulation module includes a voltage regulation chip, an input terminal of the voltage regulation chip is connected to a first microstrip inductor and a first filter capacitor, and an output terminal of the voltage regulation chip is connected to a second filter capacitor and a diode, wherein an anode of the diode is connected to the voltage regulation chip.

According to some embodiments of the present invention, the horizontally polarized amplification module and the vertically polarized amplification module have the same structure, the horizontally polarized amplification module includes a first-stage amplification circuit, a second-stage amplification circuit, and a high-pass filter circuit, which are connected in sequence, an input end of the first-stage amplification circuit is connected to the horizontally polarized probe, and an output end of the high-pass filter circuit is connected to a first input end of the phase-locked integrated module.

In a second aspect, a frequency down converter according to an embodiment of the present invention includes the dual-output frequency down circuit described above.

Additional aspects and advantages of the utility model will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the utility model.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a schematic block diagram of a dual output down-conversion circuit according to an embodiment of the present invention;

fig. 2 is a circuit schematic diagram of the dual-output down-conversion circuit shown in fig. 1.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

In the description of the present invention, "a plurality" means one or more, "a plurality" means two or more, and greater than, less than, more than, etc. are understood as excluding the present number, and "greater than", "lower than", "inner", etc. are understood as including the present number. If the description of "first", "second", etc. is used for the purpose of distinguishing technical features, it is not intended to indicate or imply relative importance or to implicitly indicate the number of indicated technical features or to implicitly indicate the precedence of the indicated technical features.

In the description of the present invention, unless otherwise explicitly limited, the terms "disposed," "connected," and the like are to be construed broadly, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention by combining the detailed contents of the technical solutions.

Referring to fig. 1, the present embodiment discloses a down converter, which includes a dual-output down converter circuit, the dual-output down converter circuit includes a phase-locked integrated module 100, a horizontal polarization amplification module 200, a vertical polarization amplification module 300, a first output frequency-selecting module 400, a second output frequency-selecting module 500, a positioning signal access module 600, and a microstrip power-dividing module 700, the phase-locked integrated module 100 has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the horizontal polarization amplification module 200 is connected to the first input terminal of the phase-locked integrated module 100, the vertical polarization amplification module 300 is connected to the second input terminal of the phase-locked integrated module 100, the input terminal of the first output frequency-selecting module 400 is connected to the first output terminal of the phase-locked integrated module 100, the output terminal of the first output frequency-selecting module 400 is connected to a first output interface 410, the input terminal of the second output frequency-selecting module 500 is connected to the second output terminal of the phase-locked integrated module 100, the output end of the second output frequency selection module 500 is connected to a second output interface 420, the input end of the positioning signal access module 600 is connected to a positioning signal receiving antenna 610, the input end of the microstrip power dividing module 700 is connected to the output end of the positioning signal access module 600, the first output end of the microstrip power dividing module 700 is connected to the first output interface 410, and the second output end of the microstrip power dividing module 700 is connected to the second output interface 420.

The working principle of the embodiment is as follows:

when the phase-locked loop is used, a horizontal polarization amplification module 200 receives a horizontal polarization signal, or a vertical polarization amplification module 300 receives a vertical polarization signal, the horizontal polarization amplification module 200 or the vertical polarization amplification module 300 outputs a corresponding signal to the phase-locked integrated module 100, the phase-locked integrated module 100 performs conversion, phase discrimination, filtering, oscillation and frequency mixing on the horizontal polarization signal or the vertical polarization signal, and outputs independent intermediate frequency signals to a first output frequency selection module 400 and a second output frequency selection module 500, the frequency band of the intermediate frequency signals is 950MHz to 1750MHz, the first output frequency selection module 400 and the second output frequency selection module 500 perform band-pass frequency selection and filtering on the corresponding intermediate frequency signals, so as to obtain effective intermediate frequency signals with the frequency band of 950MHz to 1450MHz, and correspondingly output the effective intermediate frequency signals to the first output interface 410 or the second output interface 420. Meanwhile, the positioning signal receiving antenna 610 is configured to receive a satellite positioning signal, amplify, select a frequency, and filter the satellite positioning signal through the positioning signal access module 600 to obtain an effective positioning signal, and divide the positioning signal into two balanced signals through the microstrip power dividing module 700, where the two balanced signals are respectively coupled to the first output interface 410 and the second output interface 420, so that channel common-path output of the satellite positioning signal and an output signal of the phase-locked integration module 100 is realized and the signals are not interfered with each other.

The positioning signal access module 600 is arranged in this embodiment, and can receive a satellite positioning signal, so that after the installation of the frequency demultiplier is completed, the installation area of the frequency demultiplier can be determined according to the satellite positioning signal, and the frequency demultiplier can be authorized to be used only under the condition that the installation area of the frequency demultiplier is located in a specified area range, so that the frequency demultiplier can be managed according to the satellite positioning signal.

In this embodiment, the phase-lock integrated module 100 employs a single phase-lock chip, which has high integration level, stability and reliability, and can save a large number of peripheral devices and reduce the area of the PCB, thereby reducing the design size and the production cost.

In this embodiment, the positioning signal access module 600 includes a first positioning signal amplifier 601, a first frequency-selective filter 602, and a second positioning signal amplifier 603, which are connected in sequence, an input end of the first positioning signal amplifier 601 is connected to the positioning signal receiving antenna 610, and an output end of the second positioning signal amplifier 603 is connected to the microstrip power dividing module 700. The first positioning signal amplifier 601 performs primary amplification on the satellite positioning signal, the first frequency-selective filter 602 performs frequency-selective filtering on the amplified satellite positioning signal to obtain a satellite positioning signal with a frequency band meeting the requirement, and then the satellite positioning signal is secondarily amplified by the second positioning signal amplifier 603.

The first positioning signal amplifier 601 and the second positioning signal amplifier 603 both adopt Beidou satellite signal amplifiers, the type of the Beidou satellite signal amplifiers is SW7125, the amplifiers of the signals are low-noise and high-gain amplifiers, the working frequency band of the amplifiers is 1550-1615 MHz, the receiving sensitivity is high, a peripheral circuit is simple, and the area of a PCB can be greatly saved. Matched with the Beidou satellite signal amplifier, the positioning signal receiving antenna 610 adopts a Beidou signal receiving antenna and can receive satellite positioning signals of corresponding frequency bands. The satellite positioning signal passes through the first frequency-selecting filter 602 to obtain a positioning signal with the frequency of 1561 +/-2 MHz, wherein the first frequency-selecting filter 602 adopts a Beidou sound meter filter, the model number of the Beidou sound meter filter is NDFG002, the stability and the reliability are high, the insertion loss is low, the deep standing band interference attenuation characteristic is high, the peripheral circuit structure is simple, the area of a PCB (printed circuit board) can be effectively saved, and the miniaturization design is realized.

In order to improve the performance of the positioning signal access module 600, a first coupling capacitor is connected between each positioning signal receiving antenna 610, the first positioning signal amplifier 601, the first frequency-selecting filter 602, the second positioning signal amplifier 603, and the microstrip power dividing module 700. For example, referring to fig. 1 and fig. 2, the antenna BD-ANT is used as the positioning signal receiving antenna 610, the chip IC4, the chip IC5 and the chip IC3 are respectively used as the first positioning signal amplifier 601, the first frequency-selective filter 602 and the second positioning signal amplifier 603, a capacitor C23 is connected between the positioning signal receiving antenna 610 and the first positioning signal amplifier 601, a capacitor C37 is connected between the first positioning signal amplifier 601 and the first frequency-selective filter 602, a capacitor C42 is connected between the first frequency-selective filter amplifier and the second positioning signal amplifier 603, and a capacitor C22 is connected between the second positioning signal amplifier 603 and the microstrip power dividing module 700. Through setting up first coupling capacitance, can reduce the direct current component in the circuit, reduce the interference of circuit, obtain more accurate satellite positioning signal.

Referring to fig. 2, in the present embodiment, the microstrip power dividing module 700 includes a microstrip power divider, a first resistor, such as a resistor R10, is connected between a first output terminal and a second output terminal of the microstrip power divider, a second coupling capacitor, such as a capacitor C16 and a capacitor C18, is connected between the first output terminal and the first output interface 410 of the microstrip power divider, and a third coupling capacitor, such as a capacitor C24 and a capacitor C33, is connected between the second output terminal and the second output interface 420 of the microstrip power divider. The microstrip power divider can be realized by the microstrip lines arranged on the PCB, has the characteristic of small volume, can effectively reduce the area of the PCB, and realizes the miniaturization design.

The first output frequency selection module 400 and the second output frequency selection module 500 have the same structure, the first output frequency selection module 400 comprises a multistage LC filter circuit, wherein the inductance of the LC filter circuit adopts a microstrip inductor, the capacitance comprises a capacitor C5, a capacitor C6, a capacitor C8, a capacitor C9 and a capacitor C10, signals in the 1450 MHz-2150 MHz frequency band can be effectively inhibited and filtered through the multistage LC filter circuit, an effective intermediate frequency signal in the 950-1450 MHz frequency band is obtained, and the intermediate frequency signal and the satellite positioning signal are enabled not to interfere with each other.

At least one of the first output interface 410 and the second output interface 420 is connected to a voltage stabilizing module, an input end of the voltage stabilizing module is correspondingly connected to at least one of the first output interface 410 and the second output interface 420, and an output end of the voltage stabilizing module is respectively connected to the phase-locked integrated module 100 and the positioning signal access module 600. The voltage stabilizing module provides stable working voltage for the phase-locking integrated module 100 and the positioning signal access module 600, so that fluctuation of the working voltage can be reduced, and the stability of the circuit can be improved.

Referring to fig. 2, the voltage stabilizing module includes a voltage stabilizing chip, such as a chip IC1, an input terminal of the voltage stabilizing chip is connected to the first microstrip inductor and the first filter capacitor, an output terminal of the voltage stabilizing chip is connected to the second filter capacitor and the diode, and an anode of the diode is connected to the voltage stabilizing chip. The first microstrip inductor and the first filter capacitor form a filter circuit, which is beneficial to improving the stability of the input signal of the voltage stabilization chip.

Referring to fig. 1, the structure of the horizontal polarization amplification module 200 is the same as that of the vertical polarization amplification module 300, the horizontal polarization amplification module 200 includes a first-stage amplification circuit 210, a second-stage amplification circuit 220 and a high-pass filter circuit 230, which are connected in sequence, an input end of the first-stage amplification circuit 210 is connected to the horizontal polarization probe, and an output end of the high-pass filter circuit 230 is connected to a first input end of the phase-locked integrated module 100.

The technical solution of the embodiment of the present invention is described in detail with reference to fig. 2 as a specific embodiment.

Satellite signals are received by the horizontal polarization probe and then input to a first-stage MOS tube Q1 for low-noise amplification, VGS voltage of an MOS tube Q1 is provided by a current-limiting resistor R6 after being filtered by a capacitor C19, and VDS voltage of the MOS tube Q1 is provided by a current-limiting resistor R4 after being filtered by a capacitor C17; the amplified signal is coupled to a second-stage MOS tube Q2 by a capacitor C12, the VGS voltage of the MOS tube Q2 is provided by a current-limiting resistor R1 after being filtered by a capacitor C4, the VDS voltage is provided by a filter capacitor C7 and a current-limiting resistor R2, and the signal is secondarily amplified by the MOS tube Q2. The signal after the secondary amplification is output to the first microstrip line high-pass filter circuit through the coupling capacitor C13, and the first microstrip line high-pass filter circuit filters out-of-band signals and noise, so as to obtain an effective signal and output the effective signal to the 32 nd pin of the phase-locked chip IC 2.

Satellite signals are received by the vertical polarization probe and then input to a first-stage MOS tube Q4 for low-noise amplification, VGS voltage of an MOS tube Q4 is provided by a current-limiting resistor R15 after being filtered by a capacitor C26, and VDS voltage of the MOS tube Q4 is provided by a current-limiting resistor R14 after being filtered by a capacitor C25; the amplified signal is coupled to a second-stage MOS transistor Q3 through a capacitor C34, VGS voltage of the MOS transistor Q3 is filtered by the capacitor C40 and provided by a current-limiting resistor R18, and VDS of the MOS transistor Q3 is provided by a filter capacitor C41 and a current-limiting resistor R17, so that the signal is amplified for the second time. The signal after the secondary amplification is output to a second microstrip line high-pass filter circuit through a coupling capacitor C31, and the second microstrip line high-pass filter circuit filters out-of-band signals and noise; thereby obtaining a valid signal and outputting it to pin 9 of the phase locked chip IC 2.

The horizontal polarization signal and the vertical polarization signal are respectively input to a 32 th pin and a 9 th pin of the phase-locked chip IC2, and then phase discrimination, filtering, oscillation operation and the like are carried out to obtain a 10.75GHz local oscillator. Meanwhile, after internal frequency mixing and amplification of the phase-locked chip IC2, the intermediate frequency signals of 950 MHz-1750 MHZ are output through a 26 th pin and a 15 th pin respectively. The first path of intermediate frequency signal enters the first output frequency selection module 400 through the coupling capacitor C14, and is filtered by a multistage LC filter circuit composed of a capacitor C8, a capacitor C6, a capacitor C5, a capacitor C9, a capacitor C10 and a first microstrip inductor, and is coupled to the first output interface 410 through a capacitor C11. The main power supply of the first branch is provided by a filter capacitor C3, a filter capacitor C2, a voltage stabilizing chip IC1 and an isolation diode D1.

The second path of intermediate frequency signal enters the second output frequency selection module 500 through the coupling capacitor C27, and is filtered by a multistage LC filter circuit formed by the capacitor C35, the capacitor C32, the capacitor C36, the capacitor C29, the capacitor C38 and the second microstrip inductor, so that a bandwidth signal of 1450 MHz-1750 MHz is obtained. And coupled to the second output interface 420 by C39. The main power supply of the second branch is provided by a filter capacitor C44, a filter capacitor C43, a voltage stabilizing chip IC6 and an isolation diode D2.

The antenna BD-ANT receives Beidou positioning signals, the Beidou signals are input to the chip IC4 through the capacitor C23 and the matching inductor L1 to be subjected to signal amplification, and the working voltage of the chip IC4 is divided by the resistor R8 and is input to the 4 th pin and the 5 th pin of the chip IC4 after being filtered through the capacitor C30. The amplified signal is output from the 6 th pin of the chip IC4, and is coupled to the 1 st pin of the chip IC5 through the capacitor C37 for filtering and frequency selection. The output of the 4 th pin of the chip IC5 is coupled to the chip IC3 through the capacitor C42 and the matching inductor L2 for the second amplification. The signal after the second amplification is output from the 6 th pin of the chip IC3 through the capacitor C22 and the capacitor C20. The processed Beidou positioning signal is subjected to balanced branching with the microstrip power divider through the resistor R10, is coupled to the first output interface 410 through the capacitor C18 and the capacitor C16, and is coupled to the second output interface 420 through the capacitor C24 and the capacitor C33, so that common-path output of the satellite television signal and the Beidou satellite positioning signal is realized.

The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.

Claims

1. A dual output frequency down circuit, comprising:

a phase-locked integrated module (100) having a first input, a second input, a first output, and a second output;

the horizontal polarization amplification module (200) is connected with a first input end of the phase-locking integrated module (100);

the vertical polarization amplification module (300) is connected with the second input end of the phase-locking integrated module (100);

the input end of the first output frequency selection module (400) is connected with the first output end of the phase-locked integrated module (100), and the output end of the first output frequency selection module (400) is connected with a first output interface (410);

the input end of the second output frequency selection module (500) is connected with the second output end of the phase-locked integrated module (100), and the output end of the second output frequency selection module (500) is connected with a second output interface (420);

the positioning signal access module (600) is connected with the input end of the positioning signal access module, and the input end of the positioning signal access module is connected with a positioning signal receiving antenna (610);

an input end of the microstrip power dividing module (700) is connected to an output end of the positioning signal access module (600), a first output end of the microstrip power dividing module (700) is connected to the first output interface (410), and a second output end of the microstrip power dividing module (700) is connected to the second output interface (420).

2. The dual-output frequency reducing circuit of claim 1, wherein the positioning signal access module (600) comprises a first positioning signal amplifier (601), a first frequency-selective filter (602), and a second positioning signal amplifier (603) connected in sequence, an input terminal of the first positioning signal amplifier (601) is connected to the positioning signal receiving antenna (610), and an output terminal of the second positioning signal amplifier (603) is connected to the microstrip power dividing module (700).

3. The dual-output frequency reducing circuit of claim 2, wherein the first positioning signal amplifier (601) and the second positioning signal amplifier (603) both employ Beidou satellite signal amplifiers.

4. The dual-output frequency down-conversion circuit of claim 2, wherein the first frequency selective filter (602) is a Beidou meter filter.

5. The dual-output frequency reducing circuit according to any one of claims 2 to 4, wherein a first coupling capacitor is connected between each two of the positioning signal receiving antenna (610), the first positioning signal amplifier (601), the first frequency-selective filter (602), the second positioning signal amplifier (603), and the microstrip power dividing module (700).

6. The dual-output frequency reducing circuit according to any one of claims 1 to 4, wherein the microstrip power divider module (700) comprises a microstrip power divider, a first resistor is connected between a first output terminal and a second output terminal of the microstrip power divider, a second coupling capacitor is connected between the first output terminal of the microstrip power divider and the first output interface (410), and a third coupling capacitor is connected between the second output terminal of the microstrip power divider and the second output interface (420).

7. The dual-output frequency-reducing circuit according to any of claims 1 to 4, wherein the first output frequency-selecting module (400) and the second output frequency-selecting module (500) are identical in structure, and the first output frequency-selecting module (400) comprises a multi-stage LC filter circuit.

8. The dual-output frequency down-conversion circuit according to any one of claims 1 to 4, wherein at least one of the first output interface (410) and the second output interface (420) is connected to a voltage stabilizing module, an input end of the voltage stabilizing module is correspondingly connected to at least one of the first output interface (410) and the second output interface (420), and an output end of the voltage stabilizing module is respectively connected to the phase-locked integrated module (100) and the positioning signal access module (600).

9. The dual-output frequency reducing circuit of claim 1, wherein the horizontally polarized amplifying module (200) and the vertically polarized amplifying module (300) have the same structure, the horizontally polarized amplifying module (200) comprises a first-stage amplifying circuit (210), a second-stage amplifying circuit (220) and a high-pass filtering circuit (230) connected in sequence, an input of the first-stage amplifying circuit (210) is connected to a horizontally polarized probe, and an output of the high-pass filtering circuit (230) is connected to a first input of the phase-locked integrated module (100).

10. A frequency down converter comprising the dual output frequency down circuit of any of claims 1 to 9.