CN219086859U

CN219086859U - Digital high-power charger efficiency improving circuit

Info

Publication number: CN219086859U
Application number: CN202221597109.4U
Authority: CN
Inventors: 李东
Original assignee: Huizhou Anbao Technology Co ltd
Current assignee: Huizhou Anbao Technology Co ltd
Priority date: 2022-06-23
Filing date: 2022-06-23
Publication date: 2023-05-26
Anticipated expiration: 2032-06-23

Abstract

The utility model discloses a digital high-power charger efficiency improving circuit, which comprises a rectifying circuit, a PFC circuit, a power supply circuit, an LLC circuit, a feedback circuit and a control circuit of a singlechip, wherein 100-240VAC voltage is input, the power supply circuit provides a 15VDC voltage for an LDO voltage stabilizing circuit and then stabilizes the voltage to 5V for the singlechip, the control circuit of the singlechip detects the model provided by the feedback circuit and outputs different PWM to a half-bridge LLC, so that the pulse width of a driving signal for controlling LLC MOS is changed, and the voltage and the current can be adjusted. And the reaction is on 40V-75V, 10A, 750W power, when not using the technical scheme of the utility model originally, output 40V,10A,400W of low pressure separately, power working efficiency 88%, when after adding the utility model, output 40V,10A,400W too, power working efficiency 95%, the efficiency is improved by 7.95% than originally. The high-frequency loss of the power supply in the charging process is reduced, and the power supply efficiency is greatly improved.

Description

Digital high-power charger efficiency improving circuit

Technical Field

The utility model relates to the technical field of switching converters, in particular to a circuit for improving the efficiency of a digital high-power charger.

Background

High frequency switching power supplies have evolved from the advent to the present time, and their utility has now progressed widely. Following the rapid development of modern power electronic technology, more and more high-frequency technology is applied to high-frequency switching power supplies, and the functions of the switching power supplies in all aspects are greatly improved. With the continuous progress of the switching frequency of the high-frequency switching power supply, a plurality of negative effects are brought, and the switching tube hard switch of the common topological circuit is replaced by a soft switch in order to reduce the loss of switching elements and passive elements. Unlike conventional PWM (pulse width modulation) "hard switching", LLC is a resonant circuit that achieves constant output voltage by controlling the switching frequency (frequency modulation). The advantages are that: zero-voltage switching-on (ZVS) of the primary side two main MOS switches and zero-current switching-off (ZCS) of the secondary side rectifying diode are realized, and the switching loss of a power supply can be reduced and the efficiency and the power density of the power converter can be improved through a soft switching technology. When a high-power switching power supply, such as a 750W switching power supply, outputs 75V10A, the efficiency of the power LLC can reach 93 percent at the lowest. However, when the voltage output is low, the power supply loss is larger than before. If 45V10A and 450W are output, LLC efficiency is only 88%, which indicates that the technical scheme cannot achieve the same high efficiency as that of high-voltage output in a full-voltage section.

The existing llc resonant converter cannot keep the same efficiency under the full output voltage, and the highest efficiency can be achieved only under a certain output voltage point. The LLC resonant converter is enabled to work at a resonant point all the time, and the 0 loss in the switching process is kept, so that the maximum efficiency is achieved.

Disclosure of Invention

The utility model aims to provide a digital high-power charger efficiency improving circuit for solving the problems in the background technology.

In order to achieve the above purpose, the present utility model provides the following technical solutions: a digital high-power charger efficiency improvement circuit is characterized in that: the control circuit of the singlechip outputs different PWM signals to the LLC circuit through information change transmitted by a feedback circuit, so that pulse width of a driving signal for controlling output MOS is changed, and output adjustment can be performed;

the resonant converter comprises a 485 controller, PFC, an LM2904 comparator and three important chips including MS32F031A6A0ZW, LM2904 and NCP1397AG, wherein the 485 controller monitors output voltage, the digital-to-analog conversion circuit controls the potential of the FB pin in the PFC circuit to adjust the PFC voltage, when the output voltage is 45V, the PFC voltage is required to be reduced from 420V to about 380V, the rear half-bridge LLC circuit works at a resonance point, the LLC gain value is increased, the loss of the MOS tube in a high-frequency switch is reduced, and the 485 controller monitors the output voltage, and the LM2904 operational circuit controls the potential of the FB pin in the PFC circuit to adjust the PFC voltage.

Furthermore, the rectifying circuit is provided with a current operational amplifier, and the current operational amplifier is provided with a reference voltage by a 431 stabilized power supply and is compared with the reference voltage provided by the singlechip.

Further, the power supply MCU circuit is powered by 3.3v, the main circuit is connected with 4 diodes in series through a high-frequency transformer, the diodes are provided with four ports, 1 resistor is connected in series respectively, the resistor is connected with a capacitor, the resistor is connected with 4 capacitors in parallel after rectification, and the output is output through an inductive relay after a filter circuit is formed.

Further, the PFC circuit supplies power to the half-bridge LLC circuit through the PFC voltage circuit to provide output for the rear section.

Furthermore, the rectifying circuit at the front end comprises an EMI filtering element, and 300V direct current is obtained through bridge rectification to provide voltage for the PFC at the back end.

Further, the charger detects the voltage of the output end by the 485 controller, and then adjusts PFC voltage through digital-to-analog conversion according to the detection result, so that LLC works at a resonance point, loss is reduced, and the maximum gain effect is obtained.

Compared with the prior art, the utility model has the beneficial effects that:

1. the 485 controller detects the battery voltage (output voltage) and sends the battery voltage (output voltage) to the MCU to adjust PFC voltage so that the half-bridge LLC continuously works near a resonance point, the half-bridge LLC always keeps zero voltage on, zero current is turned off, the loss of a tube in the switching process is reduced, and the working efficiency of the charger is improved

2. And the reaction is on 40V-75V, 10A, 750W power, when not using the technical scheme of the utility model originally, output 40V,10A,400W of low pressure separately, power working efficiency 88%, when after adding the utility model, output 40V,10A,400W too, power working efficiency 95%, the efficiency is improved by 7.95% than originally. The high-frequency loss of the power supply in the charging process is reduced, and the power supply efficiency is greatly improved.

Drawings

FIG. 1 is a schematic diagram of a system flow;

FIG. 2; the scheme is a section flow circuit schematic diagram

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

Referring to fig. 1-2, the present utility model provides a technical solution: a digital high-power charger efficiency improving circuit comprises a rectifying circuit, a PFC circuit, a power supply circuit, an LLC circuit, a feedback circuit and a control circuit of a singlechip. The voltage of 100-240VAC is input, a circuit provides a 15VDC voltage to an LDO voltage stabilizing circuit and then stabilizes the voltage to 5V or 3.3V to a singlechip, a control circuit of the singlechip outputs different PWM signals to an LLC circuit through information change transmitted by a feedback circuit, so that the pulse width of a driving signal for controlling an output MOS is changed, and the output adjustment can be carried out;

Preferably, the rectifying circuit has a current operational amplifier, and the current operational amplifier is provided with a reference voltage by a 431 stabilized power supply and is compared with the reference voltage provided by the singlechip

Preferably, the power supply MCU circuit is powered by 3.3v, the main circuit is connected with 4 diodes in series through a high-frequency transformer, the diodes are provided with four ports, 1 resistor is connected in series respectively, the resistor is connected with a capacitor, the resistor is connected with 4 capacitors in parallel after rectification, and the output is output through an inductive relay after a filter circuit is formed.

Preferably, the PFC circuit supplies power to the half-bridge LLC circuit via a PFC voltage circuit to provide an output for the subsequent stage.

Preferably, the obtained information is fed back to the MCU through the LM2904 comparator feedback circuit, and the change of the voltage and the current of the output end is controlled in real time.

Preferably, the charger detects the voltage of the output end by the 485 controller, and then adjusts PFC voltage through digital-to-analog conversion according to the detection result, so that LLC works at a resonance point, loss is reduced, and the maximum gain effect is obtained.

Working principle: when the power supply is switched on with 100-240VAC, one path of PFC circuits such as U7 and the like is conveyed through the rectifying circuit. The circuit provides a 15VDC voltage for the LDO voltage stabilizing circuit and then stabilizes the voltage to 5V or 3.3V for the singlechip; the other path supplies power to the MCU through the starting resistor. The MCU obtains the feedback information of the rear end and outputs different PWM duty ratios, and changes the pulse width of a driving signal for controlling the output MOS, thereby changing the output current and the voltage. And the 485 controller monitors the output voltage and controls the potential of the FB pin in the PFC circuit through the digital-to-analog conversion circuit so as to adjust the PFC voltage. For example, when the output voltage is 45V, PFC voltage is reduced from 420V to 380V, so that the rear half-bridge LLC circuit works at a resonance point, the LLC gain value is increased, and the loss of the MOS tube in the high-frequency switch is reduced.

Although embodiments of the present utility model have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the utility model, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A digital high-power charger efficiency improvement circuit is characterized in that: the control circuit of the singlechip outputs different PWM signals to the circuit through information change transmitted by the feedback circuit, so that pulse width of a driving signal for controlling output MOS is changed, and output adjustment can be performed;

the resonant converter comprises a 485 controller, PFC, an LM2904 comparator and three important chips including MS32F031A6A0ZW, LM2904 and NCP1397AG, wherein the 485 controller monitors output voltage and transmits the output voltage to an MCU of a power supply, the MCU is isolated through an optical coupler, a digital-to-analog conversion circuit controls the potential of an FB pin in a PFC circuit to adjust the PFC voltage, when the output voltage is 45V, the PFC voltage needs to be reduced from 420V to about 380V, a rear half-bridge LLC circuit works at a resonance point, an LLC gain value is increased, loss of an MOS tube in a high-frequency switch is reduced, and the 485 controller monitors the output voltage and controls the potential of the FB pin in the PFC circuit through an LM2904 operation circuit to adjust the PFC voltage.

2. The digital high power charger efficiency enhancement circuit of claim 1, wherein: the rectifying circuit is provided with a current operational amplifier, the current operational amplifier is provided with a reference voltage by a 431 stabilized power supply and is compared with the reference voltage provided by the singlechip, and the VCC end of the comparator is connected with a capacitor in series and the capacitor is grounded.

3. The digital high power charger efficiency enhancement circuit of claim 1, wherein: the MCU circuit of the power supply is powered by 3.3v, the main circuit is rectified by 4 diodes connected in series through a high-frequency transformer, the diodes are provided with four ports, 1 resistor is connected in series respectively, the resistor is connected with a capacitor, the rectified resistor is connected with the 4 capacitors in parallel, and the rectified resistor is output through an inductive relay.

4. The digital high power charger efficiency enhancement circuit of claim 1, wherein: the PFC circuit supplies power to the half-bridge LLC circuit through the PFC voltage circuit to provide output for the rear section.

5. The digital high power charger efficiency enhancement circuit of claim 1, wherein: the front-end rectifying circuit comprises an EMI filtering element, and 300V direct current is obtained through bridge rectification to provide voltage for the back-end PFC.

6. The digital high power charger efficiency enhancement circuit of claim 1, wherein: the obtained information is fed back to the MCU through the LM2904 comparator feedback circuit, and the change of the voltage and the current of the output end is controlled in real time.

7. The digital high power charger efficiency enhancement circuit of claim 1, wherein: the charger detects the voltage of the output end by the 485 controller, and then adjusts PFC voltage through digital-to-analog conversion according to the detection result, so that LLC works at a resonance point, loss is reduced, and the maximum gain effect is obtained.