CN219085961U - Chip packaging structure - Google Patents

Abstract

The application discloses a chip packaging structure, which comprises a carrier plate, a first chip, a second chip and a packaging body, wherein the carrier plate is configured into a first electrode part, a second electrode part and a third electrode part which are insulated from each other, and the first electrode part and the second electrode part are provided with bearing grooves; the first chip is overlapped in the bearing groove, and the first electrode and the second electrode of the first chip are respectively and electrically connected with the first electrode part and the second electrode part; the second chip is overlapped on the first chip and the third electrode part, the first electrode of the second chip is electrically connected with the third electrode of the first chip, the third electrode of the second chip is electrically connected with the third electrode part, and the second electrode of the second chip is electrically connected with the first electrode part; and the packaging body is used for packaging the first chip and the second chip on the carrier plate, and the first electrode part, the second electrode part and the third electrode part are exposed from the packaging body. Based on the above, the chip packaging thickness can be reduced, the production cost can be reduced, the parasitic loss can be reduced, and the product reliability can be improved.

Description

Chip packaging structure

Technical Field

The present disclosure relates to semiconductor packaging, and more particularly, to a chip packaging structure.

Background

With the trend of miniaturization and integration of electronic products, the densification of microelectronic packaging technology has become a mainstream in new generation electronic products. In order to conform to the development of new generation electronic products, especially the development of products such as mobile phones, notebooks, intelligent wearing equipment and the like, chips are developed in the directions of higher density, faster speed, smaller size, lower cost and the like.

In the traditional chip packaging process, the chips are connected with each other mainly through a wire bonding or copper clamp mode. However, the chip connection mode not only can increase the thickness of the packaged product, but also has poor heat dissipation performance and higher production cost, and can generate larger parasitic loss and reduce the reliability of the product.

Therefore, it is needed to create a chip packaging method to simplify the chip packaging structure, thereby reducing the thickness of the chip packaging product, improving the heat dissipation performance, reducing the production cost, reducing the parasitic loss, and improving the product reliability.

Disclosure of Invention

The application mainly provides a chip packaging structure to solve the thickness that current product exists great, heat dispersion is poor, the cost is higher, parasitic loss is big, the low scheduling problem of product reliability.

In order to solve the technical problems, one technical scheme adopted by the application is as follows: provided is a chip packaging structure including: the carrier plate is configured to be divided into a first electrode part, a second electrode part and a third electrode part which are insulated from each other, wherein the first electrode part is provided with a first bearing groove, and the second electrode part is provided with a second bearing groove; the first chip is overlapped on the first bearing groove and the second bearing groove, a first electrode of the first chip is electrically connected with the first electrode part, and a second electrode of the first chip is electrically connected with the second electrode part; the second chip is overlapped on the first chip and the third electrode part, the first electrode of the second chip is electrically connected with the third electrode of the first chip, the third electrode of the second chip is electrically connected with the third electrode part, and the second electrode of the second chip is electrically connected with the first electrode part; and the packaging body is used for packaging the first chip and the second chip on the carrier plate, and the first electrode part, the second electrode part and the third electrode part are exposed from the packaging body.

Optionally, the chip package structure further includes a heat dissipation member, wherein the heat dissipation member is stacked on the second chip, and the heat dissipation member is exposed from the package body.

Optionally, the heat spreader covers at least the second chip and a portion of the third electrode portion.

Optionally, the heat dissipation element is a metal heat dissipation sheet, and the metal heat dissipation sheet is in contact with the second electrode of the second chip to be electrically connected; the chip packaging structure also comprises an electric connection part arranged on the first electrode part, and the electric connection part is connected with the metal radiating fin and the first electrode part.

Optionally, an end surface of the electrical connection portion facing away from the first electrode portion is coplanar with an end surface of the second chip facing away from the carrier plate.

Optionally, the chip packaging structure further includes: and a second electrical connection portion disposed on the first electrode portion, the second electrical connection portion connecting the second electrode of the second chip and the first electrode portion.

Optionally, the carrier plate is a metal plate.

Optionally, the first electrode of the first chip is electrically connected to the first electrode portion in a contact manner, and the second electrode of the first chip is electrically connected to the second electrode portion in a contact manner; the first electrode of the second chip is electrically connected with the third electrode of the first chip in a contact manner, and the third electrode of the second chip is electrically connected with the third electrode part in a contact manner.

Optionally, a space region is provided between the first electrode portion, the second electrode portion and the third electrode portion, and the package is further filled in the space region.

Optionally, the first chip includes a first source layer, a first gate layer and a first drain layer, where the first source layer and the first gate layer are both stacked on the first drain layer and are spaced apart from each other, the first source layer is configured as a first electrode of the first chip, the first gate layer is configured as a second electrode of the first chip, and the first drain layer is configured as a third electrode of the first chip;

and/or the second chip comprises a second source electrode layer, a second gate electrode layer and a second drain electrode layer, wherein the second source electrode layer and the second drain electrode layer are respectively arranged on the second gate electrode layer in a stacked mode and are mutually separated, the second source electrode layer is configured as a first electrode of the second chip, the second gate electrode layer is configured as a second electrode of the second chip, and the second drain electrode layer is configured as a third electrode of the second chip.

The beneficial effects of this application are: in order to solve the above problems, the present application discloses a chip package structure, wherein a carrier plate of the chip package structure is divided into a first electrode portion, a second electrode portion and a third electrode portion which are insulated from each other, the first electrode portion and the second electrode portion are respectively provided with a first carrying groove and a second carrying groove for placing a first chip therein, further, the second chip is stacked on the first chip and the third electrode portion, electrical connection is respectively realized between the first chip, the second chip and the carrier plate, the first chip and the second chip are packaged on the carrier plate by a package body, and the first electrode portion, the second electrode portion and the third electrode portion are exposed from the package body for external electrical connection. Through above-mentioned structure setting, this application need not to utilize modes such as wire bonding connection or copper clip to connect the chip, but directly utilizes the overall arrangement optimization of chip just to realize the electric connection between the chip and the electric connection between chip and the carrier to can greatly simplify chip packaging structure, reduce chip packaging structure thickness, reduction in production cost, reduce parasitic loss, improve product reliability. Meanwhile, as the first chip is buried in the groove arranged on the carrier plate, the heat dissipation of the first chip is easier, and the heat dissipation performance of the chip packaging structure is improved.

Drawings

For a clearer description of embodiments of the present application or of the solutions of the prior art, the drawings that are required to be used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are only some embodiments of the present application, and that other drawings may be obtained, without inventive effort, by a person skilled in the art from these drawings, in which:

FIG. 1 is a schematic cross-sectional structure of a chip package structure of the present application;

FIG. 2 is a schematic plan view of a carrier plate according to the present application;

FIG. 3 is a schematic plan view of a first chip of the present application;

fig. 4 is a schematic plan view of a second chip of the present application.

Detailed Description

The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

The terms "first," "second," "third," and the like in the embodiments of the present application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

In order to solve the technical problems of larger thickness, higher cost, large parasitic loss, low product reliability and the like of the existing product, the application provides a chip packaging structure 100, refer to fig. 1 and fig. 2, fig. 1 is a schematic cross-sectional view of the chip packaging structure 100, and fig. 2 is a schematic plan structure of a carrier 10.

As shown in fig. 1 and 2, the carrier board 10 of the chip package structure 100 is configured as a first electrode portion 11, a second electrode portion 12 and a third electrode portion 13 which are insulated from each other, the first electrode portion 11 and the second electrode portion 12 are respectively provided with a first carrying groove 14 and a second carrying groove 15 for placing the first chip 20, wherein further, the second chip 30 is stacked on the first chip 20 and the third electrode portion 13, the first chip 20 is electrically connected with the second chip 30, the first chip 20, the second chip 30 and the carrier board 10 are electrically connected through the first electrode portion 11, the second electrode portion 12 or the third electrode portion 13, the package body 40 encapsulates the first chip 20 and the second chip 30 on the carrier board 10, and the first electrode portion 11, the second electrode portion 12 and the third electrode portion 13 are exposed from the package body 40 for external electrical connection. Therefore, the chip package structure 100 can realize the electrical connection between the chips and the carrier plate 10 by directly utilizing the contact between the chips and the carrier plate 10 without designing a wire bonding or copper clip structure, thereby greatly realizing the simplified design of the chip package structure 100. Meanwhile, as the first chip is buried in the groove arranged on the carrier plate, the heat dissipation of the first chip is easier, and the heat dissipation performance of the chip packaging structure is improved.

The chip package structure 100 of the present application includes a carrier 10, a first chip 20, a second chip 30, and a package body 40. The carrier 10 is configured as the first electrode 11, the second electrode 12, and the third electrode 13 that are insulated from each other, specifically, an insulating portion may be disposed between the first electrode 11, the second electrode 12, and the third electrode 13, or a space may be disposed between the first electrode 11, the second electrode 12, and the third electrode 13, and the package 40 may be further filled in the space, so long as the first electrode 11, the second electrode 12, and the third electrode 13 that are insulated from each other can be disposed on the carrier 10.

The first electrode portion 11 is provided with a first carrying groove 14, the second electrode portion 12 is provided with a second carrying groove 15, and the first chip 20 is stacked in the first carrying groove 14 and the second carrying groove 15. That is, the first chip 20 may be placed in a groove provided on the carrier 10. Therefore, compared with the conventional manner of placing the chip on the carrier plate 10, the thickness of the chip package structure 100 can be reduced, and meanwhile, the heat generated by the first chip 20 can be dissipated without penetrating through the whole carrier plate 10, so that the heat dissipation effect of the first chip 20 is improved.

Further, the first chip 20 is electrically connected to the first electrode portion 11 and the second electrode portion 12, respectively.

Specifically, the first electrode 21 of the first chip 20 is electrically connected to the first electrode portion 11, and the second electrode 22 of the first chip 20 is electrically connected to the second electrode portion 12.

The application further comprises a second chip 30, the second chip 30 is stacked on the first chip 20 and the third electrode portion 13, and the second chip 30 is electrically connected with the first chip 20 and the third electrode portion 13 respectively. Based on this, the first chip 20 is disposed on the carrier 10, and the second chip 30 is disposed on the first chip 20 and the carrier 10, so that the first chip 20 and the second chip 30 can be electrically connected to each other, and the first chip 20 and the second chip 30 are electrically connected to different conductive portions of the carrier 10. Therefore, the first chip 20, the second chip 30 and the carrier plate 10 can be directly and respectively electrically connected without designing a wire bonding connection or a copper clamp structure, the structure of the chip packaging structure 100 is greatly simplified, the production cost of the chip packaging structure 100 is reduced, the parasitic loss problem caused by the wire bonding connection mode is avoided, and the reliability of products is improved.

Specifically, the first electrode 31 of the second chip 30 is electrically connected to the third electrode 23 of the first chip 20, the third electrode 33 of the second chip 30 is electrically connected to the third electrode portion 13, and the second electrode 32 of the second chip 30 is electrically connected to the first electrode portion 11.

It should be noted that the first electrode 21, the second electrode 22, and the third electrode 23 of the first chip 20 may be a source, a gate, or a drain, respectively, so long as the conduction of the circuit can be achieved. The first electrode 31, the second electrode 32, and the third electrode 33 of the second chip 30 may be a source electrode, a gate electrode, or a drain electrode, respectively, as long as the conduction of the circuit can be achieved. The present application is not particularly limited.

In addition, the present application further provides a package body 40, where the package body 40 encapsulates the first chip 20 and the second chip 30 on the carrier 10, and the first electrode portion 11, the second electrode portion 12, and the third electrode portion 13 are exposed from the package body 40.

Specifically, the package 40 may be an organic material such as a cured resin, a semi-cured resin, a resin, PI, or an inorganic material such as silicon oxide or silicon nitride, as long as the chip molding can be realized.

Alternatively, the package body 40 may encapsulate the first chip 20 and the second chip 30 on the carrier 10, i.e. the side of the second chip 30 facing away from the first chip 20 is still covered by the package body 40.

In the present embodiment, the package body 40 encapsulates the first chip 20 and the second chip 30 on the carrier 10, and the package body 40 is not required to be disposed on the side of the second chip 30 facing away from the first chip 20, so that the second chip 30 dissipates heat through the side.

In some embodiments of the present application, when the first electrode part 11, the second electrode part 12, and the third electrode part 13 are disposed at a distance from each other, the package body 40 is further filled in a spaced region between the first electrode part 11, the second electrode part 12, and the third electrode part 13, so that the first electrode part 11, the second electrode part 12, and the third electrode part 13 are connected to each other to be configured as a whole, and thus are configured as good supporting and sealing effects for the first chip 20, the second chip 30.

In some embodiments of the present application, the chip package structure 100 further includes a heat dissipation element 50, where the heat dissipation element 50 is stacked on the second chip 30 and contacts the second chip 30, and the heat dissipation element 30 is exposed from the package body 40, so that the heat dissipation effect of the chip package structure 100 can be effectively enhanced by using the heat dissipation fin 30 to dissipate heat outwards.

Specifically, the heat sink 50 may be made of aluminum alloy, brass, bronze, or the like, and may be plate-like, multi-plate-like, or the like, so long as it can help the chip dissipate heat, and the present application is not specifically limited thereto.

In some embodiments of the present application, since the second chip 30 is stacked on the first chip 20 and the third electrode portion 13, the present application provides the heat sink 50 to cover at least the second chip 30 and a portion of the third electrode portion 13, whereby an effect of helping the heat dissipation of the chip can be achieved. The larger the area of the covered chip is, the better the heat dissipation effect is, but the cost is increased. Therefore, the coverage area of the heat dissipation element 50 may be specifically set according to the actual needs of the user, which is not specifically limited herein.

Further, in some embodiments of the present application, the heat sink 50 is a metal heat sink that is in contact with the second electrode 32 of the second chip 30 to be electrically connected.

The chip package structure 100 is further provided with a first electrical connection portion 16 on the first electrode portion 11, where one or more first electrical connection portions 16 may be provided according to actual needs, which is not limited in number. In some embodiments, the first electrical connection portion 16 is electrically connected to the metal heat sink and the first electrode portion 11, so as to electrically connect the metal heat sink and the first electrode portion 11, and at the same time, the first electrical connection portion 16 can also function as a support for the metal heat sink, so that the chip package structure 100 is more stable. In other embodiments, the chip package structure 100 may further include a second electrical connection portion (not shown) disposed on the first electrode portion 11, where the second electrical connection portion is electrically connected to the second electrode 32 of the second chip 30 and the first electrode portion 31, respectively, so as to realize electrical connection between the second electrode 32 of the second chip 30 and the first electrode portion 31, and meanwhile, the second electrical connection portion may also support the second chip 30 to enhance structural stability of the chip package structure 100.

Specifically, the first electrical connection portion 16 may be an electrical connection structure such as a metal pad, as long as the second electrode 32 of the metal heat sink or the second chip 30 can be electrically connected to the first electrode portion 11 of the carrier 10, and the present application is not particularly limited.

In some embodiments of the present application, the end surface of the first electrical connection portion 16 facing away from the first electrode portion 11 is coplanar with the end surface of the second chip 30 facing away from the carrier plate 10. That is, the first electrical connection 16 and the second chip 30 are coplanar on a side facing away from the carrier plate 10. For example, when the height of the first chip 20 is equal to the heights of the first carrying groove 14 and the second carrying groove 15, the first electrical connection portion 16 is equal to the height of the second chip 30. For another example, when the height of the first chip 20 is greater than the heights of the first carrying groove 14 and the second carrying groove 15, the height of the first electrical connection portion 16 is the difference between the second chip 30 and the portion of the first chip 20 higher than the first carrying groove 14 and the second carrying groove 15. Based on this, the present application can achieve the technical effect that the first electrical connection portion 16 electrically connects the metal heat sink and the first electrode portion 31 at the same time or electrically connects the second electrode 32 and the first electrode portion 31 of the second chip 30 at the same time, and simultaneously functions to support the metal heat sink or the second chip 30.

In some embodiments of the present application, the carrier 10 is further configured to conduct heat from the first chip 20 and the second chip 30 for heat dissipation. For example, the carrier 10 may be a metal plate, so that heat generated by the chip operation is timely transferred from the carrier 10 to the outside, so as to avoid damage to the chip caused by the excessive temperature or structural deformation of the chip package structure 100.

In some embodiments of the present application, the first electrode 21 of the first chip 20 is electrically connected in contact with the first electrode portion 11, and the second electrode 22 of the first chip 20 is electrically connected in contact with the second electrode portion 12. That is, the first chip 20 is electrically connected to the two electrode portions of the carrier 10 by contact. Therefore, the conventional electrical connection structure such as wire bonding connection or copper clips between the first chip 20 and the carrier plate 10 can be omitted, and the structural simplification of the chip packaging structure 100 can be realized.

At the same time, the first electrode 31 of the second chip 30 is electrically connected in contact with the third electrode 23 of the first chip 20, and the third electrode 33 of the second chip 30 is electrically connected in contact with the third electrode portion 13. That is, the second chip 30 is electrically connected to the first chip 20 and the carrier 10 by contact. Thus, the conventional electrical connection structure such as wire bonding connection or copper clips between the second chip 30 and the first chip 20 and the carrier plate 10 can be omitted, so as to further simplify the structure of the chip package structure 100.

Referring to fig. 3, a schematic planar structure of the first chip 20 is shown.

In some embodiments of the present application, the first chip 20 may include a first source layer, a first gate layer, and a first drain layer, each of which is stacked on the first drain layer and spaced apart from each other, the first source layer configured as the first electrode 21 of the first chip 20, the first gate layer configured as the second electrode 22 of the first chip 20, and the first drain layer configured as the third electrode 23 of the first chip 20. Thus, the circuit conduction inside the first chip 20 and the relatively independent circuit conduction between the first chip 20 and the first electrode portion 11 and the second electrode portion 12 of the carrier plate 10 can be realized.

Referring to fig. 4, a schematic planar structure of the second chip 30 is shown.

Alternatively, the second chip 30 may include a second source layer, a second gate layer, and a second drain layer, each of which is stacked on the second gate layer and spaced apart from each other, the second source layer being configured as the first electrode 31 of the second chip 30, the second gate layer being configured as the second electrode 32 of the second chip 30, and the second drain layer being configured as the third electrode 33 of the second chip 30. Thus, the second chip 30 is electrically connected to the first chip 20 and the third electrode 13 of the carrier 10, and the second chip 30 is electrically connected to the third electrode 13.

In distinction from the prior art, the present application discloses a chip package structure 100, the chip package structure 100 includes a carrier 10, a first chip 20, a second chip 30 and a package body 40, wherein, the carrier 10 is provided with three mutually insulated electrode portions, and the first electrode portion 11 and the second electrode portion 12 are respectively provided with a carrying groove for the first chip 20 to be placed, further, the present application is provided with the second chip 30 on the first chip 20 and the third electrode portion 13, so that the second chip 30 is electrically connected with the first chip 20 and the carrier 10 respectively, on this basis, the package body 40 encapsulates the first chip 20 and the second chip 30 on the carrier 10, so that the first chip 20 and the second chip 30 are configured as a closed and stable chip structure, and the first electrode portion 11, the second electrode portion 12 and the third electrode portion 13 are exposed from the package body 40 for external electrical connection. Based on this, on one hand, the first chip 20 is buried in the carrier plate 10, so that the height of the chip packaging structure 100 is reduced, and the heat dissipation performance of the product is improved; on the other hand, the structure such as wire bonding connection or copper clips required by mutual electric connection among the first chip 20, the second chip 30 and the carrier plate 10 is omitted, the production cost is further reduced, the parasitic loss is reduced, and the reliability of the product is improved. Still further, the first electrical connection portion 16 is disposed on the first electrode portion 11, so that the metal heat sink and the first electrode portion 31 are electrically connected or the second electrode 32 of the second chip 30 and the first electrode portion 31 are electrically connected, and meanwhile, the metal heat sink or the second chip 30 is supported, so that the structural stability of the chip package structure 100 is improved. In addition, the heat dissipation member is further stacked on the second chip 30, so that the technical effect of heat dissipation of the two sides of the chip structure can be achieved, and the heat dissipation performance of the chip package structure 100 is greatly improved.

The above electrical connection parts are only embodiments of the present application, and are not limited to the patent scope of the present application, and all equivalent structures or equivalent processes using the descriptions and the contents of the present application or directly or indirectly applied to other related technical fields are included in the patent protection scope of the present application.

Claims (10)

1. A chip package structure, comprising:

a carrier plate configured as a first electrode part, a second electrode part and a third electrode part which are insulated from each other, wherein the first electrode part is provided with a first carrying groove, and the second electrode part is provided with a second carrying groove;

the first chip is stacked in the first bearing groove and the second bearing groove, a first electrode of the first chip is electrically connected with the first electrode part, and a second electrode of the first chip is electrically connected with the second electrode part;

a second chip stacked on the first chip and the third electrode portion, wherein a first electrode of the second chip is electrically connected with a third electrode of the first chip, a third electrode of the second chip is electrically connected with the third electrode portion, and a second electrode of the second chip is electrically connected with the first electrode portion;

and the packaging body is used for packaging the first chip and the second chip on the carrier plate, and the first electrode part, the second electrode part and the third electrode part are exposed from the packaging body.

2. The chip package structure of claim 1, further comprising a heat sink stacked on the second chip, the heat sink being exposed from the package body.

3. The chip package structure according to claim 2, wherein the heat sink covers at least the second chip and a part of the third electrode portion.

4. The chip package structure of claim 2, wherein the heat spreader is a metal heat spreader that is in contact with the second electrode of the second chip to be electrically connected;

the chip packaging structure further comprises a first electric connection part arranged on the first electrode part, and the first electric connection part is connected with the metal radiating fin and the first electrode part.

5. The chip package structure according to claim 4, wherein an end surface of the first electrical connection portion facing away from the first electrode portion is coplanar with an end surface of the second chip facing away from the carrier.

6. The chip package structure according to claim 2, further comprising: and a second electrical connection portion disposed on the first electrode portion, the second electrical connection portion connecting the second electrode of the second chip and the first electrode portion.

7. The chip package structure of claim 2, wherein the carrier is a metal plate.

8. The chip package structure according to claim 1, wherein a first electrode of the first chip is electrically connected in contact with the first electrode portion, and a second electrode of the first chip is electrically connected in contact with the second electrode portion;

the first electrode of the second chip is electrically connected with the third electrode of the first chip in a contact mode, and the third electrode of the second chip is electrically connected with the third electrode part in a contact mode.

9. The chip package structure according to claim 1, wherein a space region is provided between the first electrode portion, the second electrode portion, and the third electrode portion, and the package body is further filled in the space region.

10. The chip package structure of claim 1, wherein the semiconductor package structure comprises a plurality of semiconductor chips,

the first chip comprises a first source electrode layer, a first grid electrode layer and a first drain electrode layer, wherein the first source electrode layer and the first grid electrode layer are respectively arranged on the first drain electrode layer in a stacked mode and are mutually spaced, the first source electrode layer is configured as a first electrode of the first chip, the first grid electrode layer is configured as a second electrode of the first chip, and the first drain electrode layer is configured as a third electrode of the first chip;

and/or the number of the groups of groups,

the second chip comprises a second source electrode layer, a second gate electrode layer and a second drain electrode layer, wherein the second source electrode layer and the second drain electrode layer are respectively arranged on the second gate electrode layer in a stacked mode and are mutually spaced, the second source electrode layer is configured as a first electrode of the second chip, the second gate electrode layer is configured as a second electrode of the second chip, and the second drain electrode layer is configured as a third electrode of the second chip.

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