CN219085413U - Embedded ATE equipment of PC - Google Patents

Abstract

The embodiment of the utility model provides a PC embedded ATE device, and relates to the field of electronic equipment. Wherein the apparatus comprises: the intelligent control device comprises a back plate, a main control board, a functional board and a high-speed connector, wherein the main control board is connected with the back plate through the high-speed connector, and the main control board comprises a PC module. The PC embedded ATE equipment provided by the utility model has the advantages of small volume, installation space saving, and high signaling interaction speed in the test process, and the test efficiency of the ATE equipment is greatly improved.

Description

Embedded ATE equipment of PC

Technical Field

The utility model relates to the field of electronic equipment, in particular to a PC embedded ATE device.

Background

In all electronic component manufacturing processes, there is a need to remove the counterfeits, which is essentially a trial process. To achieve this, test equipment is required, which is so-called ATE (Automatic Test Equipment ).

However, in the existing ATE equipment, a manner that a PC is connected to the ATE equipment through a switch is generally adopted, and because the PC is external, the wiring between the equipment is long, and a communication board in the ATE equipment converts instructions issued by application software in the PC into low-speed interfaces to control the work of the ATE equipment, such as LVDS, and the like, the communication cannot be performed through high-speed signals, so that the signaling interaction time in the whole testing process is greatly increased, and the testing efficiency of the ATE equipment is reduced.

As can be seen from the above, the problem of low test efficiency of ATE equipment caused by the external PC still exists in the prior art.

Disclosure of Invention

The embodiment of the utility model provides a PC embedded ATE device, which can solve the problem of low test efficiency of the ATE device caused by the external PC in the related technology. The technical scheme is as follows:

according to one aspect of an embodiment of the utility model, a PC-embedded ATE apparatus, the apparatus comprises: the intelligent control device comprises a back plate, a main control board, a functional board and a high-speed connector, wherein the main control board is connected with the back plate through the high-speed connector, and the main control board comprises a PC module.

The technical scheme provided by the utility model has the beneficial effects that:

in the technical scheme, the utility model provides a PC embedded ATE device, which comprises a back plate, a main control board, a functional board and a high-speed connector, wherein the main control board is connected with the back plate through the high-speed connector, and the main control board comprises a PC module. Through converting the original PC into a PC module which is embedded into ATE equipment, and adopting a PCIE communication mode to carry out high-speed communication, the problem of low test efficiency of ATE equipment caused by the fact that the PC is arranged outside in the related technology is effectively solved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present utility model, the drawings that are required to be used in the description of the embodiments of the present utility model will be briefly described below.

FIG. 1 is a block diagram of a PC-embedded ATE device, according to an exemplary embodiment;

FIG. 2 is a diagram illustrating a communication scheme connection within an ATE device, according to an example embodiment;

FIG. 3 is a diagram of a signal flow pattern shown according to an exemplary embodiment;

fig. 4 is a diagram of a clock module architecture, shown in accordance with an exemplary embodiment.

Detailed Description

Embodiments of the present utility model are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the utility model.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein includes all or any element and all combination of one or more of the associated listed items.

As mentioned above, in the current electronic component detection process, because the PC is external, the wiring between the PC and the ATE equipment is long, and the communication board in the ATE equipment converts the instruction issued by the application software in the PC into some low-speed interfaces to control the ATE equipment to work, this results in that the communication cannot be performed through high-speed signals, so that the signaling interaction time in the whole test process is greatly increased, and the test efficiency of the ATE equipment is reduced.

Therefore, the embedded ATE equipment of the PC greatly improves the communication rate, reduces the time required by communication interaction and improves the test efficiency of the ATE equipment by embedding the PC into the ATE equipment and adopting a PCIE (peripheral component interconnect express, high-speed serial computer expansion bus standard) communication mode.

For the purpose of making the objects, technical solutions and advantages of the present utility model more apparent, the embodiments of the present utility model will be described in further detail with reference to the accompanying drawings.

Fig. 1 is a block diagram of a PC-embedded ATE device. The intelligent control device comprises a back plate, a main control board and a functional board, wherein the main control board comprises a PC module.

In one possible implementation, the function board includes an FPGA module and a clock module, where the FPGA (Field Programmable Gate Array, programmable logic array) module may be configured in different structures to implement various functions required to be implemented by the function board and recover data through a PCIE CLK signal of 100M.

Further, fig. 2 shows a connection diagram of the communication mode inside the ATE equipment. In one possible implementation manner, the main control board is set to be a main control and communication integrated structure, and signals output by the PC module are transmitted to the backboard through the high-speed connector.

Specifically, resources required to be controlled by the PC module can be set in ATE equipment in an interface form, such as GPIB, USB, and HDMI interfaces, and the backplane distributes the received signals to a plurality of slots on the backplane through PCIE Bridge (PCIE Bridge), and the plurality of slots are plugged with a main control board and a function board. The original PC is converted into the PC module which is embedded on the main control board, and the control instruction is issued to the FPGA module on the function board according to the PC module, so that the control instruction is executed, long wiring between the original PC and ATE equipment is omitted, a high-speed communication mode is adopted, the interaction time between the PC and the ATE equipment is shortened, and the testing efficiency of the ATE equipment is greatly improved.

In one possible embodiment, the present utility model adopts PCIE communication mode, where the main control board and the functional board are mutually data transmitting end and data receiving end, and both the data transmitting end and the data receiving end contain PCIE-TX (transmit logic) and PCIE-RX (receive logic).

In a data path of a physical link of the PCIE bus, two sets of differential signals are included, and four signal lines are included, where one differential signal is formed by two signals d+ and D-, and a signal receiving end determines whether a sending end sends a logic "1" or a logic "0" by comparing differences between the two signals. Compared with the traditional single-ended signal, the differential signal has stronger anti-interference capability, because the differential signal is required to be equal in length, equal in width, close to and in the same layer during wiring. Therefore, the external interference signals are loaded on the D+ signal and the D-signal simultaneously with the same value, the difference value is 0 in the ideal situation, and the influence on the logic value of the signals is small, so that the integrity of the signals in the whole communication process is ensured. The TX component of the data transmitting end is connected with the RX component of the data receiving end by a group of differential signals, and the link is a transmitting link of the data transmitting end and is also a receiving link of the data receiving end; the RX part of the data transmitting end and the TX part of the data receiving end are connected by another group of differential signals, and the link is the receiving link of the data transmitting end and is also the transmitting link of the data receiving end. High-speed circulation of the transmission signals in the ATE equipment is thereby achieved.

As shown in fig. 4, in one possible implementation, the clock module of the present utility model employs an asynchronous clock architecture, which is Separate Refclk Architecture, i.e., an independent reference clock. The data receiving end and the data transmitting end adopt different reference clock sources, such as Refclk1 and Refclk2 shown in the figure, no clock signal is required to be transmitted separately, and the requirements on layout and wiring are more relaxed. And can be classified into SRNC (Separate Refclk Architecture with No SSC) and SRIC (Separate Refclk Architecture with Independent SSC) according to the presence or absence of SSC (spread spectrum clock), with the difference that SRNS allows ±300ppm, and SRIS allows ±2800ppm. The clock module adopts SSC to carry out clock spread spectrum on the reference clock, reduces electromagnetic radiation of PCIE clock and data line, enhances reliability of high-speed data transmission, and further ensures reliability of data transmission in high-speed communication.

Compared with the related art, on one hand, the original external PC is converted into the PC module which is embedded in the ATE equipment, so that long wiring between the PC and the ATE equipment is omitted, the installation space is saved, and the ATE equipment is convenient to deploy; on the other hand, high-speed communication is performed inside the ATE equipment through PCIE signals, and an independent reference clock architecture is utilized, so that the stability of the high-speed communication is ensured, the time of signaling interaction is saved, and the testing efficiency of the ATE equipment is improved.

It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited in order and may be performed in other orders, unless explicitly stated herein. Moreover, at least some of the steps in the flowcharts of the figures may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order of their execution not necessarily being sequential, but may be performed in turn or alternately with other steps or at least a portion of the other steps or stages.

The foregoing is only a partial embodiment of the present utility model, and it should be noted that it will be apparent to those skilled in the art that modifications and adaptations can be made without departing from the principles of the present utility model, and such modifications and adaptations are intended to be comprehended within the scope of the present utility model.

Claims (10)

1. A PC-embedded ATE apparatus, comprising:

the intelligent control device comprises a back plate, a main control board, a functional board and a high-speed connector, wherein the main control board is connected with the back plate through the high-speed connector, and the main control board comprises a PC module.

2. The device of claim 1, wherein the function board and the backplane are connected by a PCIE bridge.

3. The apparatus of claim 1, wherein the main control board and the functional board are disposed on the back board in a slot plugging manner.

4. The device of claim 1, wherein the backplane further comprises GPIB, USB, and HDMI interfaces.

5. The device of claim 1, wherein the main control board is configured as a main control and communication integrated structure.

6. The apparatus of claim 1, wherein the PC module employs an X86 architecture.

7. The apparatus of claim 1, wherein the high-speed connector employs PCIE communications.

8. The apparatus of claim 1, wherein the function board comprises an FPGA module and a clock module for ensuring stability of communication.

9. The device of claim 8, wherein the clock module employs an asynchronous clock architecture.

10. The apparatus of claim 8 wherein a PCIE CLK communication mode is used between the FPGA module and the clock module.

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