CN219041397U - Power protection circuit - Google Patents
Power protection circuit Download PDFInfo
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- CN219041397U CN219041397U CN202223440647.5U CN202223440647U CN219041397U CN 219041397 U CN219041397 U CN 219041397U CN 202223440647 U CN202223440647 U CN 202223440647U CN 219041397 U CN219041397 U CN 219041397U
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Abstract
The utility model relates to the technical field of power protection, in particular to a power protection circuit. Wherein, this power protection circuit includes: the device comprises an input port, an output port, a charge pump circuit, a current source circuit, an overvoltage clamping protection circuit, a power supply reverse connection and negative pressure protection turn-off circuit, an inductance-capacitance filter circuit, a port capacitor array and a fast discharge circuit, wherein the inductance-capacitance filter circuit comprises a first field effect transistor and a second field effect transistor. The utility model adopting the scheme can improve the safety and the reliability of the power protection circuit and simultaneously improve the protection function types of the power protection circuit.
Description
Technical Field
The utility model relates to the technical field of power protection, in particular to a power protection circuit.
Background
In circuit design, the requirement of the integration level of the circuit is continuously increased, and the layout design and the safety of the circuit are more and more concerned. The design requirements for the power supply protection circuit are also higher and higher. In the related power protection circuit, functions supported by the circuit are limited, for example,
when the passive device design is used in the power supply filter network, the power supply filter network mainly depends on a TVS tube to meet the requirements of reverse connection and load throwing of a power supply, and does not have the functions of overvoltage active turn-off, clamp protection, surge current protection and the like;
when a P-type metal oxide semiconductor (positive channel Metal Oxide Semiconductor, PMOS) transistor is used for on-off control of the main power input path, the cost is high, corresponding software is required for control, the reliability is low, and the functions of overvoltage active turn-off, clamp protection, surge current protection and the like are not provided;
when a specific integrated chip with an N-type Metal-Oxide-Semiconductor (NMOS) transistor control function is used, the on-off control, the power supply polarity reversal protection, the overvoltage protection, the surge current protection function of the NMOS transistor need to be realized through software, the reliability is low, and the functions such as voltage clamping protection and the like are not provided.
In summary, how to improve the safety and reliability of the power protection circuit and the kind of protection function of the power protection circuit is important for those skilled in the art.
Disclosure of Invention
The utility model provides a power supply protection circuit, which mainly aims to improve the safety and reliability of the power supply protection circuit and improve the protection function types of the power supply protection circuit.
According to an aspect of the present utility model, there is provided a power supply protection circuit including: the device comprises an input port, an output port, a charge pump circuit, a current source circuit, an overvoltage clamping protection circuit, a power supply reverse connection and negative pressure protection turn-off circuit, an inductance-capacitance filter circuit, a port capacitance array and a quick discharge circuit, wherein the inductance-capacitance filter circuit comprises a first field effect transistor and a second field effect transistor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the input port is respectively connected with the input end of the charge pump circuit and the input end of the port capacitor array, the output end of the port capacitor array is connected with the drain electrode of the first field effect transistor, the source electrode of the first field effect transistor is respectively connected with the source electrode of the second field effect transistor and the first end of the power supply reverse connection and negative pressure protection turn-off circuit, the drain electrode of the second field effect transistor is respectively connected with the input end of the quick discharge circuit and the output port, the grid electrode of the first field effect transistor and the grid electrode of the second field effect transistor are respectively connected with the first end of the current source circuit, the second end of the current source circuit, the first end of the overvoltage clamping protection circuit and the second end of the power supply reverse connection and negative pressure protection turn-off circuit, and the third end of the current source circuit is connected with the output end of the charge pump circuit;
and the second end of the over-voltage clamping protection circuit and the output end of the quick discharging circuit are grounded.
Optionally, in an embodiment of the present utility model, the port capacitor array includes at least one first capacitor group connected in parallel, the first capacitor group includes at least one first capacitor connected in series, one end of the first capacitor group is grounded, and the first capacitor is a ceramic capacitor.
Optionally, in one embodiment of the present utility model, the inductance-capacitance filtering circuit further includes a first inductance, a second inductance, a first capacitance array, and a second capacitance array; wherein, the liquid crystal display device comprises a liquid crystal display device,
the first end of the first inductor is connected with the output end of the port capacitor array, the second end of the first inductor is connected with the drain electrode of the first field effect transistor, the drain electrode of the second field effect transistor is connected with the input end of the first capacitor array, the output end of the first capacitor array is connected with the first end of the second inductor, the second end of the second inductor is connected with the input end of the second capacitor array, and the output end of the second capacitor array is connected with the input end of the quick discharge circuit and the output port respectively.
Optionally, in an embodiment of the present utility model, each of the first capacitor array and the second capacitor array includes at least one set of second capacitor groups connected in parallel, one end of the second capacitor group is grounded, the second capacitor group includes at least one second capacitor connected in series, and the second capacitor is an electrolytic capacitor.
Optionally, in one embodiment of the present utility model, the charge pump circuit includes a switch, a schmitt trigger, a first resistor, a third capacitor, and a multi-stage diode array; wherein, the liquid crystal display device comprises a liquid crystal display device,
the first end of the switch is connected with the input port and the input end of the port capacitor array respectively, the second end of the switch is connected with the first end of the multi-stage diode array, and the second end of the multi-stage diode array is connected with the third end of the current source circuit;
the third end of the multistage diode array is respectively connected with the first end of the Schmitt trigger and the first end of the first resistor, the second end of the Schmitt trigger is respectively connected with the second end of the first resistor and the first end of the third capacitor, and the second end of the third capacitor is grounded.
Optionally, in one embodiment of the present utility model, the multi-stage diode array includes at least one set of diode arrays connected in series, the diode arrays including a first diode, a second diode, a fourth capacitor, and a fifth capacitor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the positive electrode of the first diode is an input end of the diode array, the negative electrode of the first diode is respectively connected with the positive electrode of the second diode and the first end of the fourth capacitor, the second end of the fourth capacitor is a third end of the multi-stage diode array, the negative electrode of the second diode and the first end of the fifth capacitor are connected to form an output end of the diode array, and the second end of the fifth capacitor is grounded.
Optionally, in one embodiment of the present utility model, the overvoltage clamping protection circuit includes a voltage regulator tube; wherein, the liquid crystal display device comprises a liquid crystal display device,
the negative electrode of the voltage stabilizing tube is respectively connected with the grid electrode of the first field effect tube, the grid electrode of the second field effect tube, the first end of the current source circuit, the second end of the current source circuit and the second end of the power supply reverse connection and negative pressure protection turn-off circuit, and the positive electrode of the voltage stabilizing tube is grounded.
Optionally, in one embodiment of the present utility model, the power supply reverse connection and negative voltage protection shutdown circuit includes a first triode; wherein, the liquid crystal display device comprises a liquid crystal display device,
the emitter of the first triode is connected with the source of the first field effect tube and the source of the second field effect tube, and the collector of the first triode is respectively connected with the grid of the first field effect tube, the grid of the second field effect tube, the first end of the current source circuit, the second end of the current source circuit and the first end of the overvoltage clamping protection circuit.
Optionally, in an embodiment of the present utility model, the first field effect transistor and the second field effect transistor are N-type metal oxide semiconductor NMOS transistors, and the first triode is an NPN triode.
Optionally, in one embodiment of the present utility model, the fast discharging circuit includes a second resistor, a third field effect transistor, and a second triode; wherein, the liquid crystal display device comprises a liquid crystal display device,
the first end of the second resistor is respectively connected with the first end of the third resistor, the drain electrode of the second field effect transistor and the output port, the second end of the second resistor is respectively connected with the drain electrode of the third field effect transistor with the second end of the third resistor, the grid electrode of the third field effect transistor is connected with the collector electrode of the second triode, and the source electrode of the third field effect transistor and the emitter electrode of the second triode are grounded.
In summary, in one or more embodiments of the present utility model, a power protection circuit includes: the device comprises an input port, an output port, a charge pump circuit, a current source circuit, an overvoltage clamping protection circuit, a power supply reverse connection and negative pressure protection turn-off circuit, an inductance-capacitance filter circuit, a port capacitor array and a fast discharge circuit, wherein the inductance-capacitance filter circuit comprises a first field effect transistor and a second field effect transistor; the input port is respectively connected with the input end of the charge pump circuit and the input end of the port capacitor array, the output end of the port capacitor array is connected with the drain electrode of the first field effect transistor, the source electrode of the first field effect transistor is respectively connected with the source electrode of the second field effect transistor and the first end of the power supply reverse connection and negative pressure protection turn-off circuit, the drain electrode of the second field effect transistor is respectively connected with the input end and the output port of the fast discharge circuit, the grid electrode of the first field effect transistor and the grid electrode of the second field effect transistor are respectively connected with the first end of the current source circuit, the second end of the current source circuit, the first end of the overvoltage clamping protection circuit and the second end of the power supply reverse connection and negative pressure protection turn-off circuit, and the third end of the current source circuit is connected with the output end of the charge pump circuit; the second end of the overvoltage clamping protection circuit and the output end of the quick discharging circuit are grounded. Therefore, the effects of inhibiting high-frequency noise of a power line, preventing reverse power connection, overvoltage protection, clamp protection, controllable slow start, negative pulse voltage impact prevention, rapid discharge of internal residual charges and the like can be realized without software control by mutually matching the charge pump circuit, the current source circuit, the overvoltage clamp protection circuit, the power reverse connection and negative pressure protection turn-off circuit, the inductance capacitance filter circuit, the port capacitance array and the rapid discharge circuit, and the like, so that the safety and the reliability of the power protection circuit can be improved, and meanwhile, the protection function variety of the power protection circuit can be improved.
Additional aspects and advantages of the utility model will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the utility model.
Drawings
The foregoing and/or additional aspects and advantages of the utility model will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
fig. 1 is a schematic structural diagram of a first power protection circuit according to an embodiment of the present utility model;
fig. 2 is a schematic structural diagram of a second power protection circuit according to an embodiment of the present utility model.
Reference numerals illustrate: a first NMOS transistor-NMOS 1; a second NMOS transistor-NMOS 2; a third NMOS transistor, NMOS3; a first NPN triode-NPN 1; a second NPN transistor-NPN 2; a first inductance-L1; a second inductance-L2; a switch-S; schmitt trigger-U1; a first resistor-R1; a second resistor-R2; a third resistor-R3; and a third capacitor-C3.
Detailed Description
Embodiments of the present utility model are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the utility model. On the contrary, the embodiments of the utility model include all alternatives, modifications and equivalents as may be included within the spirit and scope of the appended claims.
In circuit design, the requirement of the integration level of the circuit is continuously increased, and the layout design and the safety of the circuit are more and more concerned. For example, 12V batteries are commonly used on automobiles to power all electronic control units (Electronic Control Unit, ECUs), each of which requires a separate input filtering and protection circuit designed for the 12V power supply.
In the environment test conditions of the road vehicles aiming at electronic and electric equipment, the power supply protection circuit is required to meet the following basic requirements:
the device has the cutoff frequency at the frequency threshold, high-frequency noise generated by a 12V storage battery power supply end is filtered, and the power supply rejection ratio of the ECU is improved;
the noise generated by the internal power supply of the ECU to the 12V input end is restrained, and a good electromagnetic interference (Electromagnetic Interference, EMI) filtering effect is provided;
providing a large-capacity electrolytic capacitor, and realizing more stable power supply voltage input;
the device is not damaged under the condition of power supply reverse connection, and misoperation is not generated;
can withstand 24V cross over start;
can bear and overlap certain alternating voltage;
can bear the throwing load.
In the related art, the following three designs are mainly adopted for the above requirements:
the first design scheme is as follows: the power supply filter network uses passive device design, which comprises passive devices such as transient suppression diode (Transient Voltage Suppressor, TVS) tubes, ceramic capacitors, inductors, aluminum electrolytic capacitors, diodes and the like, and does not contain active devices;
the second design scheme is as follows: using a P-type metal oxide semiconductor (positive channel Metal Oxide Semiconductor, PMOS) transistor as on-off control of the main power input path strength, and controlling the PMOS transistor through corresponding software;
the third design scheme is as follows: the integrated chip with the control function of the N-type Metal-Oxide-Semiconductor (NMOS) transistor is used for realizing the on-off control, the power supply reverse polarity protection, the overvoltage protection and the surge current protection functions of the NMOS transistor.
It is easy to understand that the first design scheme is simpler in design, and mainly depends on the TVS tube to meet the requirements of reverse connection and load throwing of the power supply, and has no functions of overvoltage active turn-off, clamp protection, surge current protection and the like, and when the 12V power supply is normally powered, it is difficult to reduce the quiescent current of the whole ECU. The second design scheme adds the PMOS transistor, but the PMOS transistor has higher cost, needs corresponding software for control, has lower reliability, and does not have the functions of surge current protection and the like. In the third design scheme, although the NMOS transistor control chip with the built-in charge pump can be used, two back-to-back NMOS transistors meet the requirements of reverse power supply connection, load rejection and the like, the overvoltage shutoff is controlled by software, and the control circuit also does not have the functions of voltage clamping protection and the like.
In summary, the above three schemes do not support the functions of output voltage clamping protection during load rejection or cross-over starting, short-circuit protection of an output or post-stage circuit, quick discharge of an output electrolytic capacitor, and the like, so that the safety and reliability of the power supply protection circuit are low. Meanwhile, more integrated circuit (Integrated Circuit, IC) chips are used, resulting in higher cost of the power protection circuit.
The present utility model will be described in detail with reference to specific examples.
Fig. 1 is a schematic structural diagram of a first power protection circuit according to an embodiment of the present utility model.
As shown in fig. 1, the power supply protection circuit includes: the device comprises an input port, an output port, a charge pump circuit, a current source circuit, an overvoltage clamping protection circuit, a power supply reverse connection and negative pressure protection turn-off circuit, an inductance-capacitance filter circuit, a port capacitor array and a fast discharge circuit, wherein the inductance-capacitance filter circuit comprises a first field effect transistor and a second field effect transistor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the input port is respectively connected with the input end of the charge pump circuit and the input end of the port capacitor array, the output end of the port capacitor array is connected with the drain electrode of the first field effect transistor, the source electrode of the first field effect transistor is respectively connected with the source electrode of the second field effect transistor and the first end of the power supply inverse connection and negative pressure protection turn-off circuit, the drain electrode of the second field effect transistor is respectively connected with the input end and the output port of the quick discharge circuit, the grid electrode of the first field effect transistor and the grid electrode of the second field effect transistor are respectively connected with the first end of the current source circuit, the second end of the current source circuit, the first end of the overvoltage clamping protection circuit and the second end of the power supply inverse connection and negative pressure protection turn-off circuit, and the third end of the current source circuit is connected with the output end of the charge pump circuit;
the second end of the overvoltage clamping protection circuit and the output end of the quick discharging circuit are grounded.
According to some embodiments, the input port is for connecting to a battery and receiving power input from the battery. The output port is used for connecting a load and providing a battery-input power supply for the load.
In some embodiments, the battery is not specifically a fixed battery. For example, the battery may be a 12V battery.
According to some embodiments, the port capacitor array may be used to filter out high frequency noise on the power line and may implement the function of electrostatic discharge (ESD) protection.
In some embodiments, an lc filter circuit may be used to filter out noise from the power line. For example, power line noise above 100HZ may be filtered out.
According to some embodiments, the charge pump circuit may be configured to convert a power supply voltage output by the battery into a driving power supply voltage, and drive the first fet and the second fet to normally conduct according to the driving power supply voltage, and ensure that the first fet and the second fet are in a fully saturated conducting state.
In some embodiments, the driving power voltage is not specific to a certain fixed voltage. For example, the driving power supply voltage may be changed when the transistor types of the first field effect transistor and the second field effect transistor are changed.
According to some embodiments, the current source circuit may be configured to output a constant current, so that the first field effect transistor and the second field effect transistor are turned on slowly, so that surge current at the instant of turning on the first field effect transistor and the second field effect transistor may be limited, and surge current surge may be effectively reduced.
In some embodiments, the charge pump circuit is configured with an over-voltage clamp protection circuit, and after the power supply voltage exceeds the voltage threshold, the voltage Vgs of the gate to the source in the first triode is limited by the voltage defined by the over-voltage clamp protection circuit. If the supply voltage continues to increase, vgs will remain unchanged and Vgs will not fully satisfy the fully on state of the first transistor and an additional voltage drop will be applied to the first transistor.
According to some embodiments, the power protection circuit may also be connected with the ECU. At this time, the ECU may limit the power of the load after detecting the occurrence of the overvoltage, thereby avoiding overheating of the first fet.
In some embodiments, the output voltage actively clamps the voltage limit, which may allow the ECU to remain fully functional at higher supply voltages, e.g., voltages above 20V may be clamped to 20V.
According to some embodiments, the power supply reverse connection and negative voltage protection turn-off circuit may be used to turn off the second triode when a negative voltage pulse occurs on the power supply line, thereby preventing the output voltage from generating a negative voltage and protecting the subsequent stage circuit.
In some embodiments, a fast discharging circuit for the large electrolytic capacitor at the output end can be connected with the ECU, and the fast discharging circuit does not work when the power protection circuit is in a normal working state, but can rapidly discharge charges remained on the large electrolytic capacitor when the fast discharging circuit receives a sleep mode entering instruction sent by the ECU, so that the power protection circuit can enter a deep sleep or off state more rapidly. Therefore, the quick discharging circuit is beneficial to improving the reliability of the ECU under the similar electric test working conditions such as poor intermittent contact of a power supply.
Optionally, in an embodiment of the present utility model, fig. 2 is a schematic structural diagram of a second power protection circuit according to an embodiment of the present utility model. As shown in fig. 2, the first field effect transistor and the second field effect transistor are NMOS transistors, and at this time, the first field effect transistor is a first NMOS transistor NMOS1, and the second field effect transistor is a second NMOS transistor NMOS2. And the two NMOS transistors NMOS1 and NMOS2 are connected back-to-back.
It is easy to understand that the combined protection of the two NMOS transistors NMOS1 and NMOS2 can omit TVS at the port of the related power protection circuit, which can save the cost of the power protection circuit and reduce the occupied space of the power protection circuit.
Alternatively, in one embodiment of the present utility model, as shown in fig. 2, the port capacitor array includes at least one set of first capacitors connected in parallel, one end of the first capacitor set is grounded, and the first capacitor set includes at least one first capacitor connected in series.
According to some embodiments, the first capacitance is not specifically a fixed capacitance. For example, the first capacitance may be a ceramic capacitance.
In some embodiments, as shown in fig. 2, in the first capacitor group connected in parallel, the parallel position in the port capacitor array is at the other ends of the first and penultimate first capacitor groups, which are the input and output ends of the port capacitor array, respectively. Specifically, the other end of the first capacitor group connected with the input port is the input end of the port capacitor array, and the other end of the first capacitor group connected with the drain electrode of the first field effect transistor is the output end of the port capacitor array.
Optionally, in one embodiment of the present utility model, as shown in fig. 2, the lc filter circuit further includes a first inductor L1, a second inductor L2, a first capacitor array, and a second capacitor array; wherein, the liquid crystal display device comprises a liquid crystal display device,
the first end of the first inductor L1 is connected with the output end of the port capacitor array, the second end of the first inductor L1 is connected with the drain electrode of the first field effect transistor, the drain electrode of the second field effect transistor is connected with the input end of the first capacitor array, the output end of the first capacitor array is connected with the first end of the second inductor L2, the second end of the second inductor L2 is connected with the output end of the second capacitor array, and the output end of the second capacitor array is respectively connected with the input end and the output port of the quick discharge circuit.
According to some embodiments, the first inductance L1 and the second inductance L2 do not refer to a certain fixed inductance. For example, the inductance value of the first inductor L1 and the inductance value of the second inductor L2 may be 1uH.
In some embodiments, the first inductor L1, the second inductor L2, the first capacitor array and the second capacitor array may form a two-stage low-pass LC filter circuit, so as to improve the noise filtering effect of the power line.
According to some embodiments, the LC filter circuit may include at least one cascaded low-pass LC filter circuit. For example, when the LC filter circuit includes only the first inductor L1 and the first capacitor array, the LC filter circuit is a first-stage low-pass LC filter circuit. When the LC filter circuit includes a first inductor L1, a second inductor L2, a third inductor L3, a first capacitor array, a second capacitor array, and a third capacitor array, the LC filter circuit is a two-stage low-pass LC filter circuit.
According to some embodiments, as shown in fig. 2, the first capacitor array and the second capacitor array each comprise at least one set of parallel connected second capacitor groups, one end of the second capacitor groups is grounded, and the second capacitor groups comprise at least one series connected second capacitor.
According to some embodiments, the second capacitor bank is similar to the first capacitor bank, and the parallel locations in the capacitor arrays (first capacitor array and second capacitor array) are at the other ends of the first and penultimate second capacitor banks, respectively, the input and output ends of the capacitor arrays. For example, the other end of the second capacitor group connected with the drain electrode of the second field effect transistor is an input end of the first capacitor array, and the other end of the second capacitor group connected with the first end of the second inductor L2 is an output end of the first capacitor array; the other end of the second capacitor group connected with the second end of the second inductor L2 is an input end of the second capacitor array, and the other end of the second capacitor group connected with the input end and the output port of the fast discharging circuit is an output end of the second capacitor array.
In some embodiments, the second capacitance is not specific to a fixed capacitance. For example, the second capacitor may be an electrolytic capacitor. The capacitance of the second capacitor may be selected according to the filtered frequency range.
Alternatively, in one embodiment of the present utility model, as shown in fig. 2, the charge pump circuit includes a switch S, a schmitt trigger U1, a first resistor R1, a third capacitor C3, and a multi-stage diode array; wherein, the liquid crystal display device comprises a liquid crystal display device,
the first end of the switch S is connected with the input port and the input end of the port capacitor array respectively, the second end of the switch S is connected with the first end of the multi-stage diode array, and the second end of the multi-stage diode array is connected with the third end of the current source circuit;
the third end of the multistage diode array is respectively connected with the first end of the Schmitt trigger U1 and the first end of the first resistor R1, the second end of the Schmitt trigger U1 is respectively connected with the second end of the first resistor R1 and the first end of the third capacitor C3, and the second end of the third capacitor C3 is grounded.
According to some embodiments, as shown in fig. 2, the multi-stage diode array comprises at least one set of diode arrays connected in series, the diode arrays comprising a first diode, a second diode, a fourth capacitor, and a fifth capacitor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the anode of the first diode is an input end of the diode array, the cathode of the first diode is respectively connected with the anode of the second diode and the first end of the fourth capacitor, the second end of the fourth capacitor is a third end of the multi-stage diode array, the cathode of the second diode and the first end of the fifth capacitor are connected to form an output end of the diode array, and the second end of the fifth capacitor is grounded.
In some embodiments, the number of diode arrays connected in series in the multi-stage diode array is not specific to a certain fixed number. For example, when two sets of diode arrays connected in series are included in the multi-stage diode array, the charge pump circuit is a two-stage charge pump circuit that can generate a driving power supply voltage 8V higher than the port power supply voltage on the basis of the power supply voltage output from the 12V battery, as shown in fig. 2. When three diode arrays connected in series are included in the multi-stage diode array, the charge pump circuit is a three-stage charge pump circuit that can generate a driving power supply voltage higher than the port power supply voltage by 12V on the basis of the power supply voltage output from the 12V battery.
Optionally, in an embodiment of the present utility model, as shown in fig. 2, the over-voltage clamp protection circuit includes a regulator tube; wherein, the liquid crystal display device comprises a liquid crystal display device,
the negative electrode of the voltage stabilizing tube is respectively connected with the grid electrode of the first field effect tube, the grid electrode of the second field effect tube, the first end of the current source circuit, the second end of the current source circuit and the second end of the power supply reverse connection and negative pressure protection turn-off circuit, and the positive electrode of the voltage stabilizing tube is grounded.
It is easy to understand that, the charge pump circuit cooperates with the voltage regulator of the NMOS transistor gate, and after the power supply voltage exceeds the voltage threshold, the Vgs voltage of the first NMOS transistor NMOS1 is limited by the voltage defined by the voltage regulator. If the supply voltage continues to increase, vgs remains unchanged and Vgs does not fully satisfy the fully on state of the first NMOS transistor NMOS1 and an additional voltage drop is applied across the first NMOS transistor NMOS 1. Therefore, overvoltage protection and clamp protection functions for the output voltage can be realized, and the overvoltage protection device has an advantage over overvoltage shutdown.
Optionally, in an embodiment of the present utility model, as shown in fig. 2, the power supply reverse connection and negative voltage protection shutdown circuit includes a first triode; wherein, the liquid crystal display device comprises a liquid crystal display device,
the emitter of the first triode is connected with the source of the first field effect tube and the source of the second field effect tube, and the collector of the first triode is respectively connected with the grid of the first field effect tube, the grid of the second field effect tube, the first end of the current source circuit, the second end of the current source circuit and the first end of the overvoltage clamping protection circuit.
According to some embodiments, the first transistor is not specifically a fixed transistor. For example, the first transistor may be an NPN transistor. As shown in fig. 2, at this time, the first transistor is a first NPN transistor NPN1.
It is easy to understand that the power supply reverse connection and negative pressure protection turn-off circuit can utilize the on condition (difference of saturated on and off) of the NPN triode to turn off the second NMOS transistor NMOS2 in time when negative voltage pulse appears on the 12V power supply line, thereby preventing the condition that the output voltage has negative voltage, and protecting the subsequent circuit.
Optionally, in one embodiment of the present utility model, as shown in fig. 2, the fast discharging circuit includes a second resistor R2, a third resistor R3, a third field effect transistor, and a second triode; wherein, the liquid crystal display device comprises a liquid crystal display device,
the first end of the second resistor is respectively connected with the first end of the third resistor, the drain electrode of the second field effect transistor and the output port, the second end of the second resistor and the second end of the third resistor are respectively connected with the drain electrode of the third field effect transistor, the grid electrode of the third field effect transistor is connected with the collector electrode of the second triode, and the source electrode of the third field effect transistor and the emitter electrode of the second triode are grounded.
According to some embodiments, the third fet is not specifically a fixed fet. For example, the third field effect transistor may be an NMOS transistor. As shown in fig. 2, at this time, the third field effect transistor is a third NMOS transistor NMOS3.
In some embodiments, the second transistor is not specific to a fixed transistor. For example, the second transistor may be an NPN transistor. As shown in fig. 2, the second transistor is a second NPN transistor NPN2.
Optionally, in an embodiment of the present utility model, as shown in fig. 2, the current source circuit may use two PNP transistors to form the current source, and simultaneously, the synchronous internal resistor may adjust the magnitude of the constant current, so that the output voltage of the charge pump circuit passes through the current source circuit built by the discrete device, and controllable time charging of the gate voltages of the first NMOS transistor NMOS1 and the second NMOS transistor NMOS2 may be implemented, so that slow start of conduction of the first NMOS transistor NMOS1 and the second NMOS transistor NMOS2 may be implemented, thereby limiting the surge impact current at the opening moment, and effectively reducing the impact of the surge current.
In summary, the power protection circuit provided by the embodiment of the utility model includes: the device comprises an input port, an output port, a charge pump circuit, a current source circuit, an overvoltage clamping protection circuit, a power supply reverse connection and negative pressure protection turn-off circuit, an inductance-capacitance filter circuit, a port capacitor array and a fast discharge circuit, wherein the inductance-capacitance filter circuit comprises a first field effect transistor and a second field effect transistor; the input port is respectively connected with the input end of the charge pump circuit and the input end of the port capacitor array, the output end of the port capacitor array is connected with the drain electrode of the first field effect transistor, the source electrode of the first field effect transistor is respectively connected with the source electrode of the second field effect transistor and the first end of the power supply reverse connection and negative pressure protection turn-off circuit, the drain electrode of the second field effect transistor is respectively connected with the input end and the output port of the fast discharge circuit, the grid electrode of the first field effect transistor and the grid electrode of the second field effect transistor are respectively connected with the first end of the current source circuit, the second end of the current source circuit, the first end of the overvoltage clamping protection circuit and the second end of the power supply reverse connection and negative pressure protection turn-off circuit, and the third end of the current source circuit is connected with the output end of the charge pump circuit; the second end of the overvoltage clamping protection circuit and the output end of the quick discharging circuit are grounded. Therefore, the effects of inhibiting high-frequency noise of a power line, preventing reverse power connection, overvoltage protection, clamp protection, controllable slow start, negative pulse voltage impact prevention, rapid discharge of internal residual charges and the like can be realized without software control by mutually matching the charge pump circuit, the current source circuit, the overvoltage clamp protection circuit, the power reverse connection and negative pressure protection turn-off circuit, the inductance capacitance filter circuit, the port capacitance array and the rapid discharge circuit, and the like, so that the safety and the reliability of the power protection circuit can be improved, and meanwhile, the protection function variety of the power protection circuit can be improved. Meanwhile, all sub-circuits except the charge pump circuit use a Schmitt trigger and are composed of discrete components, and the used IC chip is smaller, so that the cost of the power supply protection circuit can be reduced, and the design flexibility of the power supply protection circuit is improved.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present utility model. In this specification, schematic representations of the above terms may be directed to different embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present utility model, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
While embodiments of the present utility model have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the utility model, the scope of which is defined by the claims and their equivalents.
Claims (10)
1. A power supply protection circuit, comprising: the device comprises an input port, an output port, a charge pump circuit, a current source circuit, an overvoltage clamping protection circuit, a power supply reverse connection and negative pressure protection turn-off circuit, an inductance-capacitance filter circuit, a port capacitance array and a quick discharge circuit, wherein the inductance-capacitance filter circuit comprises a first field effect transistor and a second field effect transistor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the input port is respectively connected with the input end of the charge pump circuit and the input end of the port capacitor array, the output end of the port capacitor array is connected with the drain electrode of the first field effect transistor, the source electrode of the first field effect transistor is respectively connected with the source electrode of the second field effect transistor and the first end of the power supply reverse connection and negative pressure protection turn-off circuit, the drain electrode of the second field effect transistor is respectively connected with the input end of the quick discharge circuit and the output port, the grid electrode of the first field effect transistor and the grid electrode of the second field effect transistor are respectively connected with the first end of the current source circuit, the second end of the current source circuit, the first end of the overvoltage clamping protection circuit and the second end of the power supply reverse connection and negative pressure protection turn-off circuit, and the third end of the current source circuit is connected with the output end of the charge pump circuit;
and the second end of the over-voltage clamping protection circuit and the output end of the quick discharging circuit are grounded.
2. The power protection circuit of claim 1, wherein the port capacitor array comprises at least one first capacitor group connected in parallel, the first capacitor group comprising at least one first capacitor connected in series, one end of the first capacitor group being grounded, the first capacitor being a ceramic capacitor.
3. The power protection circuit of claim 1, wherein the lc filter circuit further comprises a first inductor, a second inductor, a first capacitor array, and a second capacitor array; wherein, the liquid crystal display device comprises a liquid crystal display device,
the first end of the first inductor is connected with the output end of the port capacitor array, the second end of the first inductor is connected with the drain electrode of the first field effect transistor, the drain electrode of the second field effect transistor is connected with the input end of the first capacitor array, the output end of the first capacitor array is connected with the first end of the second inductor, the second end of the second inductor is connected with the input end of the second capacitor array, and the output end of the second capacitor array is respectively connected with the input end of the quick discharge circuit and the output port.
4. A power protection circuit according to claim 3, wherein the first capacitor array and the second capacitor array each comprise at least one set of parallel connected second capacitor groups, the second capacitor groups comprising at least one series connected second capacitor, one end of the second capacitor groups being grounded, the second capacitors being electrolytic capacitors.
5. The power protection circuit of claim 1, wherein the charge pump circuit comprises a switch, a schmitt trigger, a first resistor, a third capacitor, and a multi-stage diode array; wherein, the liquid crystal display device comprises a liquid crystal display device,
the first end of the switch is connected with the input port and the input end of the port capacitor array respectively, the second end of the switch is connected with the first end of the multi-stage diode array, and the second end of the multi-stage diode array is connected with the third end of the current source circuit;
the third end of the multistage diode array is respectively connected with the first end of the Schmitt trigger and the first end of the first resistor, the second end of the Schmitt trigger is respectively connected with the second end of the first resistor and the first end of the third capacitor, and the second end of the third capacitor is grounded.
6. The power protection circuit of claim 5, wherein the multi-stage diode array comprises at least one set of diode arrays connected in series, the diode arrays comprising a first diode, a second diode, a fourth capacitor, and a fifth capacitor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the positive electrode of the first diode is an input end of the diode array, the negative electrode of the first diode is respectively connected with the positive electrode of the second diode and the first end of the fourth capacitor, the second end of the fourth capacitor is a third end of the multi-stage diode array, the negative electrode of the second diode and the first end of the fifth capacitor are connected to form an output end of the diode array, and the second end of the fifth capacitor is grounded.
7. The power supply protection circuit of claim 1, wherein the over-voltage clamp protection circuit comprises a regulator tube; wherein, the liquid crystal display device comprises a liquid crystal display device,
the negative electrode of the voltage stabilizing tube is respectively connected with the grid electrode of the first field effect tube, the grid electrode of the second field effect tube, the first end of the current source circuit, the second end of the current source circuit and the second end of the power supply reverse connection and negative pressure protection turn-off circuit, and the positive electrode of the voltage stabilizing tube is grounded.
8. The power supply protection circuit of claim 1, wherein the reverse power supply and negative voltage protection turn-off circuit comprises a first transistor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the emitter of the first triode is connected with the source of the first field effect tube and the source of the second field effect tube, and the collector of the first triode is respectively connected with the grid of the first field effect tube, the grid of the second field effect tube, the first end of the current source circuit, the second end of the current source circuit and the first end of the overvoltage clamping protection circuit.
9. The power protection circuit of claim 8, wherein the first field effect transistor and the second field effect transistor are N-type metal oxide semiconductor NMOS transistors and the first transistor is an NPN transistor.
10. The power protection circuit of claim 1, wherein the fast discharge circuit comprises a second resistor, a third field effect transistor, and a second triode; wherein, the liquid crystal display device comprises a liquid crystal display device,
the first end of the second resistor is respectively connected with the first end of the third resistor, the drain electrode of the second field effect transistor and the output port, the second end of the second resistor is respectively connected with the drain electrode of the third field effect transistor with the second end of the third resistor, the grid electrode of the third field effect transistor is connected with the collector electrode of the second triode, and the source electrode of the third field effect transistor and the emitter electrode of the second triode are grounded.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223440647.5U CN219041397U (en) | 2022-12-20 | 2022-12-20 | Power protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223440647.5U CN219041397U (en) | 2022-12-20 | 2022-12-20 | Power protection circuit |
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| CN219041397U true CN219041397U (en) | 2023-05-16 |
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| CN202223440647.5U Active CN219041397U (en) | 2022-12-20 | 2022-12-20 | Power protection circuit |
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| CN (1) | CN219041397U (en) |
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