CN217824259U

CN217824259U - Peak detection level shift surge suppression circuit

Info

Publication number: CN217824259U
Application number: CN202221636644.6U
Authority: CN
Inventors: 陈晟
Original assignee: Wuxi Tianhe Electronic Co ltd
Current assignee: Wuxi Tianhe Electronic Co ltd
Priority date: 2022-06-29
Filing date: 2022-06-29
Publication date: 2022-11-15
Anticipated expiration: 2032-06-29

Abstract

The utility model provides a peak detection level shift surge suppression circuit, it realizes the surge function through adopting peak detection and level shift circuit, and it is small, and can be suitable for high power circuit. The input voltage is filtered and then connected into the surge suppression circuit by the filter circuit, the input voltage surge is suppressed by the surge suppression circuit, the output voltage between a voltage output end Vout + and Vout-is ensured not to exceed 36.5V under the condition that surge voltage occurs at input end voltage input ends IN + and IN-by switching control of an MOS tube Q1 and matching with a microprocessor U3, wherein IN order to ensure that the voltage of the MOS tube Q1 at the voltage input end is larger than 39V and the normal operation is still realized, the peak detection of a diode D4 and the level shift of the diode D1 are mainly realized.

Description

Peak detection level shift surge suppression circuit

Technical Field

The utility model relates to a surge suppression circuit technical field specifically is a peak detection level shift surge suppression circuit.

Background

At present, a common surge suppression circuit is formed by connecting a voltage clamping device such as a transient voltage suppression diode, a piezoresistor, a discharge tube and the like in parallel at a power input end, and under a normal condition, the fluctuation range of power voltage is lower than the action voltage of the clamping device, so that the clamping device has no response, namely, an open circuit, and no influence on the circuit; when the power supply is in surge, the surge voltage is higher than the action voltage of the clamping device, the clamping device is quickly conducted, the energy of the surge voltage is absorbed, and the power supply voltage is limited in a safety range, so that the effect of protecting the electric equipment is achieved. The other is to connect a voltage clamping device in series on the power input line, such as an NMOS field effect transistor or an IGBT, etc., when the input voltage is in a normal range, the voltage clamping device is completely turned on under the driving of the control chip, which is equivalent to a low impedance path, when the power supply is in surge, the control chip acts immediately to reduce the driving voltage or driving current, so that the NMOS field effect transistor or the IGBT is in a linear working region to bear the surge voltage, thereby ensuring the electric equipment to work under the safe voltage.

The existing clamping device absorbs the energy of surge voltage in a series or parallel mode to bear the surge voltage, and the power supply surge energy of certain specific electric equipment is very large, so that the current flowing through the clamping device when the clamping device is conducted usually reaches more than dozens of even hundreds of amperes, and the power consumption born instantly is from thousands of watts to tens of thousands of watts. Therefore, the clamping device with smaller power is easy to damage and cannot play a normal protection role. The high power clamping device is more expensive and larger, and thus the use of the clamping device is more limited.

SUMMERY OF THE UTILITY MODEL

Adopt cluster, parallel access equipment to restrain the surge to current clamp suppression circuit, consequently the clamping device that the power of use is on the small side then easily burns out, and the great clamping device of power of use has the problem of great restriction when using, the utility model provides a peak detection level shift surge suppression circuit, it realizes the surge function through adopting peak detection and level shift circuit, and its is small, and can be suitable for high power circuit.

The technical scheme is as follows: a peak detect level shift surge suppression circuit, characterized by: the surge suppression circuit comprises a filter circuit and a surge suppression circuit, wherein the filter circuit filters an input voltage and then accesses the input voltage into the surge suppression circuit, suppressing an input voltage surge by the surge suppression circuit, the surge suppression module comprising a microprocessor U3, a pin 1 of the microprocessor U3 is connected with a 5V voltage source, a pin 2 of the microprocessor U3 is connected with one end of a resistor R0, the other end of the resistor R0 is connected with the base electrode of the triode Q2, the emitting electrode of the triode Q2 is grounded, the collector of the triode Q2 is connected with one end of a resistor R6, the other end of the resistor R6 is connected with one end of a capacitor C5, one end of the resistor R5, the cathode of a diode D1, the cathode of a diode D2 and the cathode of a diode D3, the other end of the resistor R5 is connected with the grid electrode of the MOS tube Q1, the drain electrode of the MOS tube Q1 is connected with the voltage end OUT + and one end of the resistor R3, the other end of the capacitor C5 is connected with the anode of the diode D2 and then is connected with one end of a resistor R4 and one end of a capacitor C7 and is connected with a voltage end OUT < - >, a voltage output end Vout < - >, the other end of the resistor R4 is connected with the other end of the resistor R3 and the 7 pins of the microprocessor U3, the source electrode of the MOS tube Q1 is connected with the anode of the diode D1, the anode of the diode D4, the other end of the capacitor C7, the 3-pin of the microprocessor U3 and connected with a voltage output end Vout +, the anode of the diode D3 is connected with the cathode of the diode D4 and one end of a capacitor C6, the other end of the capacitor C6 is connected with one end of a resistor R8 and the collector of the triode Q3, the other end of the resistor R8 is connected with a 12V voltage source, the base electrode of the triode Q3 is connected with the 5 pin of the microprocessor U3 through a resistor R7, the emitting electrode of the triode Q3 is grounded, and the 8 pin of the microprocessor U3 is grounded.

It is further characterized in that: the filter circuit comprises a differential mode inductor Ld and a common mode inductor Lc, wherein 1 pin of the differential mode inductor Ld is connected with one end and a voltage input end IN + of a capacitor Cx1, 2 pins of the differential mode inductor Ld are connected with the other end of the capacitor Cx1 and the voltage input end IN-, 3 pins of the differential mode inductor Ld are connected with one end of the capacitor Cx2 and 1 pin of the common mode inductor Lc, 4 pins of the differential mode inductor Ld are connected with the other end of the capacitor Cx2 and 2 pins of the common mode inductor Lc, 3 pins of the differential mode inductor Lc are connected with one end of the capacitor Cx3, one end of a capacitor Cy1 and the voltage end OUT +, 4 pins of the differential mode inductor Lc are connected with the other end of the capacitor Cx3, one end of the capacitor Cy2 and the voltage end OUT-, and the other end of the capacitor Cy1 and the capacitor Cy2 are connected and then connected with a shell ground;

the three-terminal voltage stabilizer further comprises a peripheral circuit, the peripheral circuit comprises three-terminal voltage stabilizers U1 and U2, vin pins of the three-terminal voltage stabilizers U1 and U2 are respectively connected with one ends of a resistor R1 and a resistor R2, vout pins of the three-terminal voltage stabilizers U1 and U2 are respectively connected with one ends of a capacitor C3 and one end of a capacitor C4, the other end of the resistor R1 is connected with one end of the resistor R3, one end of the capacitor C1, one end of the capacitor C2, a drain electrode of an MOS (metal oxide semiconductor) tube Q1 and a voltage end OUT +, and GND pins of the three-terminal voltage stabilizers U1 and U2 are respectively connected with the other ends of the capacitors C1 and C4 and the voltage end OUT-and are grounded.

After the structure is adopted, the output voltage between the voltage output ends Vout + and Vout-can be ensured not to exceed 36.5V under the condition that surge voltage occurs at the voltage input ends IN + and IN-of the input end by the switch control of the MOS tube Q1 and the cooperation of the microprocessor U3, wherein IN order to ensure that the voltage of the MOS tube Q1 at the voltage input end is more than 39V and the normal operation can still be realized, the peak detection of the diode D4 and the level shift of the diode D1 are mainly used for realizing, the whole circuit of the suppression circuit uses few components, so the suppression circuit occupies small volume and can meet the surge suppression of a high-power supply.

Drawings

Fig. 1 is a schematic diagram of a surge suppression circuit of the present invention;

fig. 2 is a schematic diagram of the filter circuit of the present invention;

fig. 3 is a schematic diagram of the surge suppression circuit and the peripheral circuit of the present invention.

Detailed Description

As shown in FIG. 1, a peak detection level shift surge suppression circuit comprises a filter circuit and a surge suppression circuit, wherein the filter circuit filters an input voltage and then accesses the input voltage into the surge suppression circuit, and the input voltage surge is suppressed through the surge suppression circuit, specifically, the surge suppression module comprises a microprocessor U3, a pin 1 of the microprocessor U3 is connected with a 5V voltage source, a pin 2 of the microprocessor U3 is connected with one end of a resistor R0, the other end of the resistor R0 is connected with a base electrode of a triode Q2, an emitting electrode of the triode Q2 is grounded, a collecting electrode of the triode Q2 is connected with one end of a resistor R6, the other end of the resistor R6 is connected with one end of a capacitor C5, one end of a resistor R5, a negative electrode of a diode D1, a negative electrode of a diode D2 and a negative electrode of a diode D3, the other end of the resistor R5 is connected with a grid electrode of an MOS tube Q1, a drain electrode of the MOS tube Q1 is connected with a voltage end OUT + and one end of a resistor R3, the other end of the capacitor C5 is connected with the anode of the diode D2 and then connected with one end of a resistor R4, one end of a capacitor C7 is connected with a voltage end OUT-, the voltage output end Vout-, the other end of the resistor R4 is connected with the other end of a resistor R3, the 7 pins of the microprocessor U3, the source electrode of the MOS tube Q1 is connected with the anode of the diode D1, the anode of the diode D4, the other end of the capacitor C7, the 3 pins of the microprocessor U3 are connected with the voltage output end Vout +, the anode of the diode D3 is connected with the cathode of the diode D4, one end of the capacitor C6, the other end of the capacitor C6 is connected with one end of a resistor R8, the collector electrode of the triode Q3, the other end of the resistor R8 is connected with a 12V voltage source, the base electrode of the triode Q3 is connected with the 5 pins of the microprocessor U3 through the resistor R7, the emitter electrode of the triode Q3 is grounded, and the 8 pins of the microprocessor U3 are grounded.

As shown IN fig. 2, the filter circuit includes a differential mode inductor Ld and a common mode inductor Lc, wherein 1 pin of the differential mode inductor Ld is connected to one end of a capacitor Cx1 and a voltage input terminal IN +, 2 pins of the differential mode inductor Ld are connected to the other end of the capacitor Cx1 and a voltage input terminal IN-, 3 pins of the differential mode inductor Ld are connected to one end of the capacitor Cx2 and 1 pin of the common mode inductor Lc, 4 pins of the differential mode inductor Ld are connected to the other end of the capacitor Cx2 and 2 pins of the common mode inductor Lc, 3 pins of the differential mode inductor Lc are connected to one end of the capacitor Cx3, one end of the capacitor Cy1 and a voltage terminal OUT +, and 4 pins of the differential mode inductor Lc are connected to the other end of the capacitor Cx3, one end of the capacitor Cy2 and a voltage terminal OUT-, and the other end of the capacitor Cy1 and the other end of the capacitor Cy2 are connected to a housing ground.

As shown in fig. 3, the three-terminal regulator further comprises a peripheral circuit, the peripheral circuit comprises a three-terminal regulator U1 and a three-terminal regulator U2, vin pins of the three-terminal regulator U1 and the three-terminal regulator U2 are respectively connected with a resistor R1 and one end of a resistor R2, vout pins of the three-terminal regulator U1 and the three-terminal regulator U2 are respectively connected with one end of a capacitor C3 and one end of a capacitor C4, the other end of the resistor R1 is connected with the other end of the resistor R2 and then connected with one end of a resistor R3, one end of a capacitor C1, one end of a capacitor C2, a drain electrode of the MOS transistor Q1 and a voltage end OUT +, and GND pins of the three-terminal regulator U1 and the three-terminal regulator U2 are respectively connected with the other ends of the capacitors C1 to C4 and the voltage end OUT-and grounded.

The utility model discloses a theory of operation as follows:

in order to meet the power supply characteristics of GJB151A-97 and GJB181-86 airplanes and the requirements on electric equipment, a surge suppression circuit needs to be added at the input end of the secondary power supply. The circuit realizes that the output voltage of the voltage output ends Vout + and Vout-does not exceed 36.5V under the condition that the surge voltage of 80V/50ms occurs to the voltage input ends IN + and IN-through the on-off control of the MOS tube Q1 (LE 15N 004J), thereby ensuring that the following modules can work IN the normal working voltage range (18-36V).

Taking the input power supply voltage of 28V as an example, since the circuit controls the MOS transistor Q1 (LE 15N 004J), IN order to ensure that the MOS transistor Q1 can normally operate, it is known that the control voltage of more than 11V is required at the Vgs end of the MOS transistor during normal operation, and taking the voltage input end IN +, IN-input voltage of 28V as an example, the gate voltage of the MOS transistor is more than 39V, and thus the circuit needs to be implemented IN cooperation with the peak detection and level shift functions of other elements.

Specifically, the principle of implementing the peak detection and level shift function is as follows:

when the input voltage is 28V, the Vin pin of the three-terminal regulator U2 is powered through the resistor R2, the output end of the three-terminal regulator U2 is 5V voltage-stabilizing value, and meanwhile the Vin pin of the three-terminal regulator U1 is powered through the resistor R1. The output end of the three-terminal regulator U1 is a 5V regulated voltage value, the voltage is used as Vgs control voltage of the MOS tube Q1 through a resistor R8, peak detection is carried out through a resistor R8, a capacitor C6, a diode D3 and a diode D4 according to the charge pump principle, level shift is carried out on the D1, the voltage at a node where the capacitor C6 and the diode D4 are connected can be changed into 28V through the level shift, the capacitor C5 is charged through the diode D3, the maximum charging voltage is limited through the diode D2, and the maximum charging voltage does not exceed the maximum voltage (51V) of the diode D2 because the capacitor C5 is not provided with a discharge loop after being charged, so the maximum charging voltage can be kept through the capacitor C5. The voltage of the capacitor C5 controls the base electrode of the MOS transistor Q1 through the resistor R5, as long as the base electrode voltage is higher than the starting voltage of the MOS transistor Q1, the MOS transistor Q1 starts to be conducted, 12V minus the voltage drop of the diode 0.7V, the base electrode voltage added to the MOS transistor Q1 is 11.3V, meanwhile, the Vgs voltage difference is larger than 11.3V, as the voltage is far higher than the starting voltage (5V) of the MOS transistor Q1, the MOS transistor Q1 works in a saturation region, the MOS transistor Q1 works normally, and the output voltage of the voltage output end Vout + Vout-is equal to 28V minus the voltage drop of the MOS transistor Vds.

The utility model discloses a surge inhibiting function's concrete principle does: the voltage obtained by dividing the resistors R3 and R4 is fed back to a pin 7 of the microprocessor U3, and the output voltage is calculated after AD conversion. If the calculated feedback voltage is lower than 37V, the microprocessor U3 controls the pin output of the transistor 2 to be 0V, and the transistor Q2 is in a turn-off state. When surge voltage appears in input voltage, the divided voltage values of the resistors R3 and R4 are fed back to a pin 7 of the microprocessor U3, when the calculated feedback voltage is higher than 37V, the output voltage of a pin 2 of the microprocessor U is a certain value, the transistor Q2 is driven to be conducted, so that the transistor Q2 is in an amplification area, meanwhile, the MOS transistor Q1 works in a linear area, the output voltage is obtained by subtracting Uds voltage at two ends of the MOS transistor Q1 from the surge voltage, and therefore the output voltage is guaranteed to be stabilized below 36.5V by the suppression circuit under the condition of surge voltage.

The above description is only for the preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A peak detect level shift surge suppression circuit, characterized by: the surge suppression circuit comprises a filter circuit and a surge suppression circuit, wherein the filter circuit filters an input voltage and then accesses the input voltage into the surge suppression circuit, suppressing an input voltage surge by the surge suppression circuit, the surge suppression module comprising a microprocessor U3, a pin 1 of the microprocessor U3 is connected with a 5V voltage source, a pin 2 of the microprocessor U3 is connected with one end of a resistor R0, the other end of the resistor R0 is connected with the base electrode of the triode Q2, the emitting electrode of the triode Q2 is grounded, the collector of the triode Q2 is connected with one end of a resistor R6, the other end of the resistor R6 is connected with one end of a capacitor C5, one end of the resistor R5, the cathode of a diode D1, the cathode of a diode D2 and the cathode of a diode D3, the other end of the resistor R5 is connected with the grid electrode of the MOS tube Q1, the drain electrode of the MOS tube Q1 is connected with the voltage end OUT + and one end of the resistor R3, the other end of the capacitor C5 is connected with the anode of the diode D2 and then connected with one end of a resistor R4 and one end of a capacitor C7 and connected with a voltage end OUT-and a voltage output end Vout-, the other end of the resistor R4 is connected with the other end of the resistor R3 and the 7 pins of the microprocessor U3, the source electrode of the MOS tube Q1 is connected with the anode of the diode D1, the anode of the diode D4, the other end of the capacitor C7, the 3-pin of the microprocessor U3 and connected with a voltage output end Vout +, the anode of the diode D3 is connected with the cathode of the diode D4 and one end of a capacitor C6, the other end of the capacitor C6 is connected with one end of a resistor R8 and the collector of the triode Q3, the other end of the resistor R8 is connected with a 12V voltage source, the base of the triode Q3 is connected with the 5 pins of the microprocessor U3 through a resistor R7, the emitting electrode of the triode Q3 is grounded, and the 8 pins of the microprocessor U3 are grounded.

2. A peak detection level shifting surge suppression circuit according to claim 1, wherein: the filter circuit comprises a differential mode inductor Ld and a common mode inductor Lc, wherein 1 pin of the differential mode inductor Ld is connected with one end and a voltage input end IN + of a capacitor Cx1, 2 pins of the differential mode inductor Ld are connected with the other end of the capacitor Cx1 and the voltage input end IN-, 3 pins of the differential mode inductor Ld are connected with one end of the capacitor Cx2 and 1 pin of the common mode inductor Lc, 4 pins of the differential mode inductor Ld are connected with the other end of the capacitor Cx2 and 2 pins of the common mode inductor Lc, 3 pins of the differential mode inductor Lc are connected with one end of the capacitor Cx3, one end of a capacitor Cy1 and the voltage end OUT +, 4 pins of the differential mode inductor Lc are connected with the other end of the capacitor Cx3, one end of the capacitor Cy2 and the voltage end OUT-, and the other end of the capacitor Cy1 and the other end of the capacitor Cy2 are connected and then connected with a shell ground.

3. A peak detection level shifting surge suppression circuit according to claim 1, wherein: the three-terminal voltage stabilizer further comprises a peripheral circuit, the peripheral circuit comprises three-terminal voltage stabilizers U1 and U2, vin pins of the three-terminal voltage stabilizers U1 and U2 are respectively connected with one ends of a resistor R1 and a resistor R2, vout pins of the three-terminal voltage stabilizers U1 and U2 are respectively connected with one ends of a capacitor C3 and one end of a capacitor C4, the other end of the resistor R1 is connected with one end of the resistor R3, one end of the capacitor C1, one end of the capacitor C2, a drain electrode of an MOS (metal oxide semiconductor) tube Q1 and a voltage end OUT +, and GND pins of the three-terminal voltage stabilizers U1 and U2 are respectively connected with the other ends of the capacitors C1 and C4 and the voltage end OUT-and are grounded.