CN219875480U - Time-delay high-voltage protection circuit - Google Patents
Time-delay high-voltage protection circuit Download PDFInfo
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- CN219875480U CN219875480U CN202321086405.2U CN202321086405U CN219875480U CN 219875480 U CN219875480 U CN 219875480U CN 202321086405 U CN202321086405 U CN 202321086405U CN 219875480 U CN219875480 U CN 219875480U
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- 230000005669 field effect Effects 0.000 claims abstract description 153
- 239000003990 capacitor Substances 0.000 claims abstract description 45
- 238000005070 sampling Methods 0.000 claims abstract description 40
- 230000000087 stabilizing effect Effects 0.000 description 19
- 230000007423 decrease Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000001105 regulatory effect Effects 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Abstract
The utility model relates to a delay high-voltage protection circuit which comprises an adjusting circuit, a comparison amplifying circuit, a reference voltage circuit, a sampling circuit and a delay circuit, wherein the adjusting circuit is connected with the comparison amplifying circuit; the adjusting circuit comprises a first field effect transistor, the drain electrode of the first field effect transistor is connected with the input voltage, and the source electrode of the first field effect transistor is connected with the output voltage; the comparison amplifying circuit comprises a third resistor and a second field effect transistor, wherein two ends of the third resistor are respectively connected with an input voltage and a drain electrode of the second field effect transistor, and the drain electrode of the second field effect transistor is connected with a grid electrode of the first field effect transistor; the sampling circuit is connected with the grid electrode of the second field effect transistor, and the reference voltage circuit is connected with the source electrode of the second field effect transistor; the delay circuit comprises a third diode and a second capacitor, wherein the cathode of the third diode is connected with the input voltage, the anode of the third diode is simultaneously connected with the drain electrode of the second field effect transistor and the upper polar plate of the second capacitor, and the lower polar plate of the second capacitor is connected with the source electrode of the second field effect transistor. The scheme protects the electric components of the circuit through time delay.
Description
Technical Field
The utility model relates to the technical field of integrated circuits, in particular to a delay high-voltage protection circuit.
Background
The power supply circuit is divided into a linear voltage stabilizing circuit and a switching voltage stabilizing circuit, and most of electronic equipment currently uses the linear voltage stabilizing circuit, and the power device adjusting tubes in the circuit work in a linear region and are stably output by adjusting voltage drop among the tubes; a small part of devices adopt a switch type voltage stabilizing circuit, so that a voltage regulating tube of the device works in a switch state, and stable voltage output is carried out through conversion of an energy storage circuit.
When the applicant applies the voltage stabilizing circuit to equipment, tests show that the voltage stabilizing circuit can inhibit high-voltage overshoot from a high-voltage power supply, but high voltage still exists at the moment of power-on, which can cause higher peak current to cause damage to electric components of the voltage stabilizing circuit, in particular to damage to a regulating tube.
Disclosure of Invention
In view of the above, the present utility model provides a delay high voltage protection circuit for solving the problem that the electrical components of the high voltage power supply power-on induced voltage stabilizing circuit are easy to be damaged in the related art.
In order to achieve one or a part or all of the above objects or other objects, the present utility model provides a delay high voltage protection circuit, which comprises an adjusting circuit, a comparison amplifying circuit, a reference voltage circuit, a sampling circuit and a delay circuit;
the adjusting circuit comprises a first field effect tube Q1, wherein the drain electrode of the first field effect tube Q1 is connected with an input voltage, and the source electrode of the first field effect tube Q1 is connected with an output voltage;
the comparison amplifying circuit comprises a third resistor R3 and a second field effect transistor Q2, wherein two ends of the third resistor R3 are respectively connected with an input voltage and the drain electrode of the second field effect transistor Q2, and the drain electrode of the second field effect transistor Q2 is connected with the grid electrode of the first field effect transistor Q1;
the sampling circuit is connected with the grid electrode of the second field effect transistor Q2 and is used for providing sampling voltage for the comparison amplifying circuit; the reference voltage circuit is connected with the source electrode of the second field effect transistor Q2 and is used for providing reference voltage for the comparison amplifying circuit; the second field effect transistor Q2 amplifies an error value of the sampling voltage compared with the reference voltage and then controls the first field effect transistor Q1 to work;
the delay circuit comprises a third diode D3 and a second capacitor C2, wherein the negative electrode of the third diode D3 is connected with the input voltage, the positive electrode of the third diode D3 is simultaneously connected with the drain electrode of the second field effect transistor Q2 and the upper polar plate of the second capacitor C2, and the lower polar plate of the second capacitor C2 is connected with the source electrode of the second field effect transistor Q2.
In an alternative embodiment, the reference voltage circuit includes a second resistor R2 and a first zener diode D5, where an anode of the first zener diode D5 is connected to a lower plate of the second capacitor C2, a cathode of the first zener diode D5 is simultaneously connected to the source of the second field effect transistor Q2 and one end of the second resistor R2, and the other end of the second resistor R2 is connected to the source of the first field effect transistor Q1.
In an alternative embodiment, the sampling circuit includes at least two sampling resistors connected in series, and two ends of the whole series sampling resistor are respectively connected to the source electrode of the first field effect transistor Q1 and the positive electrode of the first zener diode D5.
In an alternative embodiment, the sampling resistor includes a first resistor R1, a fourth resistor R4, and a fifth resistor R5 connected in series, one end of the first resistor R1 is connected to the source of the first field effect transistor Q1, the other end of the first resistor R1 is simultaneously connected to the gate of the second field effect transistor Q2 and one end of the fourth resistor R4, two ends of the fifth resistor R5 are respectively connected to the other end of the fourth resistor R4 and the positive electrode of the first zener diode D5, and the gate of the second field effect transistor Q2 is connected to the middle of any two adjacent sampling resistors in the sampling circuit.
In an alternative embodiment, the adjusting circuit further includes a first diode D1, where an anode of the first diode D1 is connected to a source of the first field effect transistor Q1, and a cathode of the first diode D1 is connected to a drain of the first field effect transistor Q1.
In an alternative embodiment, the adjusting circuit further includes a second diode D2, an anode of the second diode D2 is connected to the source of the first field effect transistor Q1, and a cathode of the second diode D2 is connected to the gate of the first field effect transistor Q1.
In an alternative embodiment, the comparison amplifying circuit further includes a fourth diode D4, where an anode of the fourth diode D4 is connected to the source of the second field effect transistor Q2, and a cathode of the fourth diode D4 is connected to the gate of the second field effect transistor Q2.
In an optional embodiment, the delay high-voltage protection circuit further includes a first capacitor C1, an upper plate of the first capacitor C1 is connected to the output voltage, and a lower plate of the first capacitor C1 is connected to a lower plate of the second capacitor C2.
In an alternative embodiment, the adjusting circuit further includes a second zener diode D6, a third zener diode D7, and a fourth zener diode D8;
the anode of the second zener diode D6 is connected with the source electrode of the first field effect transistor Q1, and the cathode of the second zener diode D6 is connected with the drain electrode of the first field effect transistor Q1;
the negative electrode of the third zener diode D7 is connected to the gate of the first field effect transistor Q1, the positive electrode of the third zener diode D7 is connected to the positive electrode of the fourth zener diode D8, and the negative electrode of the fourth zener diode D8 is connected to the source of the first field effect transistor Q1.
In an alternative embodiment, the comparison amplifying circuit further includes a fifth zener diode D9, a sixth zener diode D10, and a seventh zener diode D11;
the positive electrode of the fifth zener diode D9 is connected with the source electrode of the second field effect transistor Q2, and the negative electrode of the fifth zener diode D9 is connected with the drain electrode of the second field effect transistor Q2;
the cathode of the sixth zener diode D10 is connected to the gate of the second field effect transistor Q2, the anode of the sixth zener diode D10 is connected to the anode of the seventh zener diode D11, and the cathode of the seventh zener diode D11 is connected to the source of the second field effect transistor Q2.
The implementation of the embodiment of the utility model has the following beneficial effects:
the utility model realizes the time delay function by arranging the time delay circuit on the linear voltage stabilizing circuit, the utility model adopts the structure of the series linear voltage stabilizing circuit, the second field effect transistor Q2 controls the grid electrode of the first field effect transistor Q1 after amplifying the error value of the comparison of the sampling voltage and the reference voltage, changes the conducting state of the first field effect transistor Q1, realizes the voltage stabilizing function, and on the basis, realizes the time delay by arranging the second capacitor C2, and when the circuit is just electrified, the high voltage firstly charges the second capacitor C2 after passing through the third resistor R3, the current entering the second field effect transistor Q2 and the first field effect transistor Q1 is very small and negligible, which is equivalent to being bypassed, the second field effect transistor Q2 can be regarded as not working, and as the second capacitor C2 is charged, the current flowing into the second field effect transistor Q2 and the first field effect transistor Q1 is gradually increased, so the output voltage is gradually increased, and the service life of the circuit is prolonged by the time delay function. In addition, when the input voltage is turned off, the third diode D3 can rapidly discharge the charge in the second capacitor C2, so as to avoid the problem that the second turn-on cannot be delayed due to the fact that the charge in the second capacitor C2 is discharged when the input voltage is turned on for the second time in the two continuous times of switching the input voltage in a short time, and the third diode D3 can ensure that the electric quantity in the second capacitor C2 is zero when the input voltage is turned on each time, so that a reset delay protection function is achieved.
The utility model solves the problem that the electric components of the high-voltage power supply power-on induced voltage stabilizing circuit are easy to damage in the related art.
Drawings
In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described, and it is apparent that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
Wherein:
fig. 1 is a schematic diagram of a circuit configuration of a delay high voltage protection circuit according to an alternative embodiment of the present utility model.
The reference numerals are explained as follows: c1, a first capacitor; c2, a second capacitor; d1, a first diode; d2, a second diode; d3, a third diode; d4, a fourth diode; d5, a first zener diode; d6, a second zener diode; d7, a third zener diode; d8, a fourth zener diode; d9, a fifth zener diode; d10, a sixth zener diode; d11, a seventh zener diode; r1, a first resistor; r2, a second resistor; r3, a third resistor; r4, a fourth resistor; r5, a fifth resistor; q1, a first field effect transistor; q2, a second field effect transistor.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
As shown in FIG. 1, one embodiment of the present utility model provides a delay high voltage protection circuit, which comprises an adjusting circuit, a comparison amplifying circuit, a reference voltage circuit, a sampling circuit and a delay circuit;
the adjusting circuit comprises a first field effect tube Q1, wherein the drain electrode of the first field effect tube Q1 is connected with an input voltage, and the source electrode of the first field effect tube Q1 is connected with an output voltage; the first field effect transistor Q1 is an adjusting tube, the first field effect transistor Q1 is used for adjusting an input voltage to form an output voltage, and the conducting state of the first field effect transistor Q1 is determined by the gate voltage.
The comparison amplifying circuit comprises a third resistor R3 and a second field effect transistor Q2, wherein two ends of the third resistor R3 are respectively connected with an input voltage and the drain electrode of the second field effect transistor Q2, and the drain electrode of the second field effect transistor Q2 is connected with the grid electrode of the first field effect transistor Q1; the second fet Q2 is turned on to control the voltage of the gate of the first fet Q1.
The sampling circuit is connected with the grid electrode of the second field effect transistor Q2 and is used for providing sampling voltage for the comparison amplifying circuit; the reference voltage circuit is connected with the source electrode of the second field effect transistor Q2 and is used for providing reference voltage for the comparison amplifying circuit; the second field effect transistor Q2 amplifies the error value of the comparison between the sampling voltage and the reference voltage and then controls the first field effect transistor Q1 to work; the sampling circuit is used for controlling the voltage of the grid electrode of the second field effect transistor Q2.
The delay circuit comprises a third diode D3 and a second capacitor C2, wherein the negative electrode of the third diode D3 is connected with the input voltage, the positive electrode of the third diode D3 is simultaneously connected with the drain electrode of the second field effect transistor Q2 and the upper polar plate of the second capacitor C2, and the lower polar plate of the second capacitor C2 is connected with the source electrode of the second field effect transistor Q2. The source of the second fet Q2 may be grounded. The second capacitor C2 is used for charging and discharging.
The sampling circuit, the reference voltage circuit and the adjusting circuit are in parallel connection, and the second capacitor C2 and the second field effect transistor Q2 are in parallel connection.
The delay function is realized by arranging a delay circuit on the linear voltage stabilizing circuit, and the embodiment adopts the structure of the series linear voltage stabilizing circuit. The combined linear voltage stabilizing circuit consists of an adjusting circuit, a comparison amplifying circuit, a reference voltage circuit and a sampling circuit.
The sampling circuit takes out a portion of the output voltage variation for comparison with a reference voltage. The second field effect transistor Q2 is used for controlling the grid electrode of the first field effect transistor Q1 after amplifying the error value of the comparison between the sampling voltage and the reference voltage, so that the conducting state of the first field effect transistor Q1 is changed, and the voltage stabilizing effect is realized.
On the basis, the delay is realized by arranging the second capacitor C2.
The time delay process comprises the following steps: when the power-on is performed, the high voltage charges the second capacitor C2 through the third resistor R3, the current entering the second field effect tube Q2 and the first field effect tube Q1 is very small and negligible and is equivalent to being bypassed, the second field effect tube Q2 can be regarded as not working, along with the charging of the second capacitor C2, the current at the position of the second capacitor C2 is gradually reduced, the current flowing into the second field effect tube Q2 and the first field effect tube Q1 is gradually increased, so that the output voltage is gradually increased, the soft start process is realized, the circuit elements such as the field effect tube and the like are protected through the delay effect, and the service life is prolonged.
In addition, when the input voltage is turned off, the third diode D3 can rapidly discharge the charge in the second capacitor C2, so as to avoid the problem that the second turn-on cannot be delayed due to the fact that the charge in the second capacitor C2 is discharged when the input voltage is turned on for the second time in the two continuous times of switching the input voltage in a short time, and the third diode D3 can ensure that the electric quantity in the second capacitor C2 is zero when the input voltage is turned on each time, so that a reset delay protection function is achieved.
Optionally, in order to provide the reference voltage for the second field effect transistor Q2, the reference voltage circuit includes a second resistor R2 and a first zener diode D5, the positive electrode of the first zener diode D5 is connected to the lower electrode plate of the second capacitor C2, the negative electrode of the first zener diode D5 is simultaneously connected to the source electrode of the second field effect transistor Q2 and one end of the second resistor R2, and the other end of the second resistor R2 is connected to the source electrode of the first field effect transistor Q1. The first zener diode D5 is configured to provide a stable voltage to the source of the first field effect transistor Q1.
Optionally, the sampling circuit at least comprises more than two sampling resistors connected in series, two ends of the whole series sampling resistor are respectively connected with the source electrode of the first field effect transistor Q1 and the positive electrode of the first zener diode D5, and the grid electrode of the second field effect transistor Q2 is connected to the middle of any two adjacent sampling resistors in the sampling circuit.
As an alternative example, the sampling resistor includes a first resistor R1, a fourth resistor R4, and a fifth resistor R5 connected in series, one end of the first resistor R1 is connected to the source of the first field effect transistor Q1, the other end of the first resistor R1 is simultaneously connected to the gate of the second field effect transistor Q2 and one end of the fourth resistor R4, and two ends of the fifth resistor R5 are respectively connected to the other end of the fourth resistor R4 and the anode of the first zener diode D5.
Optionally, the adjusting circuit further includes a first diode D1, where an anode of the first diode D1 is connected to a source of the first field effect transistor Q1, and a cathode of the first diode D1 is connected to a drain of the first field effect transistor Q1. As such, when the input voltage is turned off, the high voltage of the voltage output can be turned off instantaneously with its turn off.
Optionally, the adjusting circuit further includes a second diode D2, an anode of the second diode D2 is connected to the source of the first field effect transistor Q1, and a cathode of the second diode D2 is connected to the gate of the first field effect transistor Q1. The second diode D2 is configured to protect the voltage difference between the gate and the source of the first field effect transistor Q1 from exceeding a standard, so that the first field effect transistor Q1 is not in a deep saturation region, and further plays a role in protecting the first field effect transistor Q1.
Optionally, the comparison amplifying circuit further includes a fourth diode D4, an anode of the fourth diode D4 is connected to the source of the second field effect transistor Q2, and a cathode of the fourth diode D4 is connected to the gate of the second field effect transistor Q2. Similarly, the fourth diode D4 is configured to protect the voltage difference between the gate and the source of the second field effect transistor Q2 from exceeding the standard, so that the second field effect transistor Q2 is not in the deep saturation region, and further plays a role in protecting the second field effect transistor Q2.
Optionally, the delay high-voltage protection circuit further includes a first capacitor C1, an upper plate of the first capacitor C1 is connected to the output voltage, and a lower plate of the first capacitor C1 is connected to a lower plate of the second capacitor C2. The first capacitor C1 has a filtering function, and reduces ripple voltage in the output voltage.
Alternatively, the first fet Q1 or the second fet Q2 may be an integrated fet with better performance, for example, an integrated fet with a model STL2N80K5, as shown in fig. 1, and the structure may be considered as follows:
the adjusting circuit further includes a second zener diode D6, a third zener diode D7, and a fourth zener diode D8. The positive pole of the second zener diode D6 is connected with the source electrode of the first field effect transistor Q1, and the negative pole of the second zener diode D6 is connected with the drain electrode of the first field effect transistor Q1. The negative electrode of the third zener diode D7 is connected with the grid electrode of the first field effect transistor Q1, the positive electrode of the third zener diode D7 is connected with the positive electrode of the fourth zener diode D8, and the negative electrode of the fourth zener diode D8 is connected with the source electrode of the first field effect transistor Q1.
The comparison amplifying circuit further includes a fifth zener diode D9, a sixth zener diode D10, and a seventh zener diode D11. The positive pole of the fifth zener diode D9 is connected with the source electrode of the second field effect transistor Q2, and the negative pole of the fifth zener diode D9 is connected with the drain electrode of the second field effect transistor Q2. The negative electrode of the sixth zener diode D10 is connected with the grid electrode of the second field effect transistor Q2, the positive electrode of the sixth zener diode D10 is connected with the positive electrode of the seventh zener diode D11, and the negative electrode of the seventh zener diode D11 is connected with the source electrode of the second field effect transistor Q2.
The specific pressure stabilizing process comprises the following steps: when the input voltage rises, the voltage at two ends of a resistor in the sampling circuit rises, the sampling circuit takes out a part of variation of the output voltage to the grid electrode of the second field effect transistor Q2, the grid voltage of the second field effect transistor Q2 rises, and the voltage of the source electrode of the second field effect transistor Q2 is stabilized by the first voltage stabilizing diode D5 and kept basically unchanged, so that the voltage between the source electrode and the grid electrode of the second field effect transistor Q2 rises, the grid current of the second field effect transistor Q2 increases, the source current of the second field effect transistor Q2 increases, the voltage between the drain electrode and the source electrode of the second field effect transistor Q2 decreases, and accordingly, the grid voltage of the first field effect transistor Q1 decreases, the current of the drain electrode and the source electrode of the first field effect transistor Q1 decreases, and the voltage between the drain electrode and the source electrode of the first field effect transistor Q1 increases, namely the voltage drop of the first field effect transistor Q1 increases in the regulating circuit, so that the final output voltage decreases, and the voltage stabilizing effect is realized.
The present utility model is not limited to the above-mentioned embodiments, but is not limited to the above-mentioned embodiments, and any person skilled in the art can make some changes or modifications to the above-mentioned embodiments without departing from the scope of the present utility model.
Claims (10)
1. The delay high-voltage protection circuit is characterized by comprising an adjusting circuit, a comparison amplifying circuit, a reference voltage circuit, a sampling circuit and a delay circuit;
the adjusting circuit comprises a first field effect tube Q1, wherein the drain electrode of the first field effect tube Q1 is connected with an input voltage, and the source electrode of the first field effect tube Q1 is connected with an output voltage;
the comparison amplifying circuit comprises a third resistor R3 and a second field effect transistor Q2, wherein two ends of the third resistor R3 are respectively connected with an input voltage and the drain electrode of the second field effect transistor Q2, and the drain electrode of the second field effect transistor Q2 is connected with the grid electrode of the first field effect transistor Q1;
the sampling circuit is connected with the grid electrode of the second field effect transistor Q2 and is used for providing sampling voltage for the comparison amplifying circuit; the reference voltage circuit is connected with the source electrode of the second field effect transistor Q2 and is used for providing reference voltage for the comparison amplifying circuit; the second field effect transistor Q2 amplifies an error value of the sampling voltage compared with the reference voltage and then controls the first field effect transistor Q1 to work;
the delay circuit comprises a third diode D3 and a second capacitor C2, wherein the negative electrode of the third diode D3 is connected with the input voltage, the positive electrode of the third diode D3 is simultaneously connected with the drain electrode of the second field effect transistor Q2 and the upper polar plate of the second capacitor C2, and the lower polar plate of the second capacitor C2 is connected with the source electrode of the second field effect transistor Q2.
2. The delay high voltage protection circuit of claim 1, wherein: the reference voltage circuit comprises a second resistor R2 and a first zener diode D5, wherein the positive electrode of the first zener diode D5 is connected with the lower polar plate of the second capacitor C2, the negative electrode of the first zener diode D5 is simultaneously connected with the source electrode of the second field effect transistor Q2 and one end of the second resistor R2, and the other end of the second resistor R2 is connected with the source electrode of the first field effect transistor Q1.
3. The delay high voltage protection circuit of claim 2, wherein: the sampling circuit at least comprises more than two sampling resistors connected in series, two ends of the whole sampling resistor connected in series are respectively connected with the source electrode of the first field effect transistor Q1 and the positive electrode of the first zener diode D5, and the grid electrode of the second field effect transistor Q2 is connected to the middle of any two adjacent sampling resistors in the sampling circuit.
4. A time delay high voltage protection circuit as claimed in claim 3, characterized in that: the sampling resistor comprises a first resistor R1, a fourth resistor R4 and a fifth resistor R5 which are connected in series, one end of the first resistor R1 is connected with the source electrode of the first field effect transistor Q1, the other end of the first resistor R1 is simultaneously connected with the grid electrode of the second field effect transistor Q2 and one end of the fourth resistor R4, and two ends of the fifth resistor R5 are respectively connected with the other end of the fourth resistor R4 and the anode of the first zener diode D5.
5. A time-delay high-voltage protection circuit as claimed in any one of claims 1 to 4, characterized in that: the adjusting circuit further comprises a first diode D1, wherein the positive electrode of the first diode D1 is connected with the source electrode of the first field effect transistor Q1, and the negative electrode of the first diode D1 is connected with the drain electrode of the first field effect transistor Q1.
6. A time-delay high-voltage protection circuit as claimed in any one of claims 1 to 4, characterized in that: the adjusting circuit further comprises a second diode D2, wherein the positive electrode of the second diode D2 is connected with the source electrode of the first field effect transistor Q1, and the negative electrode of the second diode D2 is connected with the grid electrode of the first field effect transistor Q1.
7. A time-delay high-voltage protection circuit as claimed in any one of claims 1 to 4, characterized in that: the comparison amplifying circuit further comprises a fourth diode D4, wherein the positive electrode of the fourth diode D4 is connected with the source electrode of the second field effect transistor Q2, and the negative electrode of the fourth diode D4 is connected with the grid electrode of the second field effect transistor Q2.
8. A time-delay high-voltage protection circuit as claimed in any one of claims 1 to 4, characterized in that: the delay high-voltage protection circuit further comprises a first capacitor C1, wherein an upper polar plate of the first capacitor C1 is connected with output voltage, and a lower polar plate of the first capacitor C1 is connected with a lower polar plate of the second capacitor C2.
9. A time-delay high-voltage protection circuit as claimed in any one of claims 1 to 4, characterized in that: the adjusting circuit further comprises a second zener diode D6, a third zener diode D7 and a fourth zener diode D8;
the anode of the second zener diode D6 is connected with the source electrode of the first field effect transistor Q1, and the cathode of the second zener diode D6 is connected with the drain electrode of the first field effect transistor Q1;
the negative electrode of the third zener diode D7 is connected to the gate of the first field effect transistor Q1, the positive electrode of the third zener diode D7 is connected to the positive electrode of the fourth zener diode D8, and the negative electrode of the fourth zener diode D8 is connected to the source of the first field effect transistor Q1.
10. A time-delay high-voltage protection circuit as claimed in any one of claims 1 to 4, characterized in that: the comparison amplifying circuit further comprises a fifth zener diode D9, a sixth zener diode D10 and a seventh zener diode D11;
the positive electrode of the fifth zener diode D9 is connected with the source electrode of the second field effect transistor Q2, and the negative electrode of the fifth zener diode D9 is connected with the drain electrode of the second field effect transistor Q2;
the cathode of the sixth zener diode D10 is connected to the gate of the second field effect transistor Q2, the anode of the sixth zener diode D10 is connected to the anode of the seventh zener diode D11, and the cathode of the seventh zener diode D11 is connected to the source of the second field effect transistor Q2.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321086405.2U CN219875480U (en) | 2023-05-08 | 2023-05-08 | Time-delay high-voltage protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321086405.2U CN219875480U (en) | 2023-05-08 | 2023-05-08 | Time-delay high-voltage protection circuit |
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| CN219875480U true CN219875480U (en) | 2023-10-20 |
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| CN202321086405.2U Active CN219875480U (en) | 2023-05-08 | 2023-05-08 | Time-delay high-voltage protection circuit |
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