CN219760863U - Time delay switch circuit of BOOST PFC circuit - Google Patents
Time delay switch circuit of BOOST PFC circuit Download PDFInfo
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- CN219760863U CN219760863U CN202321260165.3U CN202321260165U CN219760863U CN 219760863 U CN219760863 U CN 219760863U CN 202321260165 U CN202321260165 U CN 202321260165U CN 219760863 U CN219760863 U CN 219760863U
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Abstract
The utility model specifically relates to a delay switch circuit of a BOOST PFC circuit, which comprises: an input filter capacitor C1, one end of which is connected with a voltage input end VIN, and the other end of which is grounded; one end of the output filter capacitor C4 is connected with the voltage output end VOUT, and the other end of the output filter capacitor C is grounded; the delay circuit is connected in parallel with two ends of the input filter capacitor C1; a first zener diode D1 connected to the delay circuit; the voltage reference chip U1 is connected with the delay circuit and the ground; an enhanced NMOSFET Q1, wherein the G pole of the enhanced NMOSFET Q1 is connected with a voltage reference chip U1; and the switching unit is respectively connected with the voltage reference chip U1, the enhanced NMOSFET Q1 and the voltage input end VOUT of the power supply. The utility model has the advantages that the input undervoltage and output voltage stabilizing functions are added, and the generation of large surge current can be avoided while the delay starting of the BOOST PFC circuit is realized.
Description
Technical Field
The utility model relates to the technical field of circuit design, in particular to a delay switch circuit of a BOOST PFC circuit.
Background
In the current power supply products with high-power single-phase input, the output capacitance of the BOOST PFC circuit is large, so that the bus capacitor of the BOOST PFC circuit needs to be charged through a pre-charging circuit, the voltage of the bus capacitor is close to the rectified voltage value of the input alternating current, then a relay is attracted, soft start of the BOOST PFC circuit is realized, if the relay is attracted without delay, a very large surge current is generated at the input end, and the relay contacts are in arc-pulling, are in contact connection, and are tripped and pollute a power grid.
For example, application number 201410088978.8 and patent name are "a delay soft start circuit for BOOST-PFC", which discloses a technical scheme for charging a bus capacitor through a soft start resistor R7, but the above scheme has a single function, cannot provide stable voltage while realizing long delay, and has no under-voltage protection function.
Disclosure of Invention
The present utility model aims to solve one of the technical problems existing in the prior art or related technologies.
The technical scheme adopted by the utility model is as follows:
provided is a delay switch circuit of a BOOST PFC circuit, comprising:
an input filter capacitor C1, one end of which is connected with a voltage input end VIN of a power supply, and the other end of which is grounded;
one end of the output filter capacitor C4 is connected with the voltage output end VOUT of the power supply, and the other end of the output filter capacitor C is grounded;
the delay circuit is connected in parallel with two ends of the input filter capacitor C1;
a first zener diode D1 connected to the delay circuit for stabilizing an input voltage;
the voltage reference chip U1 is connected with the delay circuit and the ground;
an enhanced N MOSFET Q1, wherein the G pole of the enhanced N MOSFET Q1 is connected with the voltage reference chip U1;
and the switch unit is respectively connected with the voltage reference chip U1, the enhanced N MOSFET Q1 and the voltage input end VOUT of the power supply.
Preferably, the switching unit includes an NPN transistor Q2, a base electrode of which is connected to a D pole of the enhancement N MOSFET Q1, a collector electrode of which is connected to the voltage reference chip U1, and an emitter electrode of which is connected to a voltage input terminal VOUT of the power supply.
Preferably, the switch unit includes an enhancement N MOSFET Q2, a G pole of which is connected with a D pole of the enhancement N MOSFET Q1, an S pole of which is connected with the voltage input terminal VOUT, and a D pole of which is connected with the voltage reference chip U1.
Preferably, the delay circuit includes: a first resistor R1, a second resistor R2, and a first capacitor C2;
the 1 st end of the first resistor R1 is connected with the voltage input end VIN, the 2 nd end is connected with the 1 st end of the second resistor R2, the 2 nd end of the second resistor R2 is connected with one end of the first capacitor C2, and the other end of the first capacitor C2 is grounded;
the anode of the first zener diode D1 is grounded, and the cathode is connected with the 2 nd end of the first resistor R1 and the 1 st end of the second resistor R2; the voltage reference chip U1 is connected to the 2 nd end of the second resistor R2 and the first capacitor C2, respectively.
Preferably, the delay switch circuit further comprises: a third resistor R3, a fourth resistor R4, and a first diode D2;
the cathode of the first diode D2 is connected to the power input terminal VIN, and the cathode is respectively connected to the 1 st end of the third resistor R3, the voltage reference chip U1, and the 2 nd end of the second resistor R2;
and the 2 nd end of the third resistor R3 is grounded.
Preferably, the delay switch circuit further comprises: a fifth resistor R5 and a second diode D4;
the 1 st end of the fifth resistor R5 is connected with the voltage input end VIN, and the 2 nd end is connected with the D pole of the enhanced N MOSFET Q1;
the cathode of the second diode D4 is connected to the voltage input terminal VIN, and the anode is connected to the voltage output terminal VOUT.
Preferably, the delay switch circuit further comprises: the second capacitor C3, the second zener diode D3 and the third zener diode D5;
one end of the second capacitor C3 is connected to the voltage output terminal VOUT, the other end is connected to the cathode of the third zener diode D5, and the anode of the third zener diode D5 is grounded;
the anode of the second zener diode D3 is grounded, and the cathode is connected to the voltage reference chip U1 and the G pole of the enhancement N MOSFET Q1, respectively.
Preferably, the delay switch circuit further comprises: and the anode of the fourth zener diode D6 is connected with the voltage output end VOUT, and the cathode of the fourth zener diode D5 is connected with the cathode of the third zener diode D5.
Preferably, the voltage reference chip U1 has a reference voltage of 1.25V or 2.5V.
Preferably, a parasitic diode is connected between the S pole and the D pole of the enhanced N MOSFET Q1.
The utility model has the following beneficial technical effects:
the circuit has a simple structure, can reduce the number of elements and the size of the circuit, has the functions of under-voltage input and voltage stabilization output, and can avoid generating large surge current while realizing the delayed start of the BOOST PFC circuit.
Drawings
Fig. 1 is a circuit diagram of a delay switch circuit (a switch unit is an NPN type triode Q2) of a BOOST PFC circuit according to the present utility model;
fig. 2 is a circuit diagram of a delay switch circuit (the switch unit is an enhanced N MOSFET Q2) of the BOOST PFC circuit according to the present utility model.
Detailed Description
The objects, technical solutions and advantages of the present utility model will become more apparent by the following detailed description of the present utility model with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments of the present utility model and features in the embodiments may be combined with each other.
A delay switch circuit of a BOOST PFC circuit according to some embodiments of the present utility model is described below with reference to the accompanying drawings.
Example 1:
referring to fig. 1, the present utility model provides a delay switch circuit of a BOOST PFC circuit, which includes:
an input filter capacitor C1, one end of which is connected with a voltage input end VIN of a power supply, and the other end of which is grounded;
one end of the output filter capacitor C4 is connected with the voltage output end VOUT of the power supply, and the other end of the output filter capacitor C is grounded; the voltage output end VOUT of the power supply is connected with the BOOST PFC circuit;
a delay circuit 100 connected in parallel to both ends of the input filter capacitor C1;
a first zener diode D1 connected to the delay circuit 100 for stabilizing the input voltages such that the delay times are consistent at different input voltages;
a voltage reference chip U1 connected to the delay circuit 100 and to ground; preferably, in this embodiment, the voltage reference chip U1 is a 431 voltage reference chip, and the reference voltage thereof is 1.25V or 2.5V;
an enhanced N MOSFET Q1, wherein a parasitic diode is connected between an S pole and a D pole of the enhanced N MOSFET Q1, and a G pole of the enhanced N MOSFET Q1 is connected with the voltage reference chip U1;
the switch unit is respectively connected with the voltage reference chip U1, the enhanced N MOSFET Q1 and the voltage input end VOUT of the power supply;
when the voltage input by the voltage input end VIN of the power supply is greater than or equal to the reference voltage of the voltage reference chip U1, the voltage reference chip U1 pulls down the G pole voltage of the enhanced N MOSFET Q1, so that the enhanced N MOSFET Q1 is turned off, and meanwhile, the switch unit is turned on, so that the voltage output by the voltage input end VOUT rises.
In this embodiment, the switching unit includes an NPN transistor Q2, a base of which is connected to a D pole of the enhancement N MOSFET Q1, a collector of which is connected to the voltage reference chip U1, and an emitter of which is connected to a voltage input terminal VOUT of a power supply;
when the voltage input by the voltage input end VIN of the power supply is greater than or equal to the reference voltage of the voltage reference chip U1, the voltage reference chip U1 pulls down the G pole voltage of the enhanced N MOSFET Q1, so that the enhanced N MOSFET Q1 is turned off, and the NPN triode Q2 is turned on accordingly, so that the voltage output by the voltage input end VOUT slowly rises.
Therefore, the delay switch circuit in the embodiment has simple structural design, can slowly and stably output voltage, can realize delay starting of the BOOST PFC circuit, has long delay time and avoids generating large surge current.
Example 2:
the present embodiment is different from embodiment 1 only in that, as shown in fig. 2, the switching unit includes an enhancement N MOSFET Q2, the G pole of which is connected to the D pole of the enhancement N MOSFET Q1, the S pole of which is connected to the voltage input terminal VOUT, and the D pole of which is connected to the voltage reference chip U1, and it is also possible to achieve a slow rise of the output voltage through the enhancement N MOSFET Q2.
Example 3:
this embodiment differs from embodiment 1 or 2 only in that, as shown in fig. 1, the delay circuit 100 includes: a first resistor R1, a second resistor R2, and a first capacitor C2;
the 1 st end of the first resistor R1 is connected with the voltage input end VIN, the 2 nd end is connected with the 1 st end of the second resistor R2, the 2 nd end of the second resistor R2 is connected with one end of the first capacitor C2, and the other end of the first capacitor C2 is grounded;
the anode of the first zener diode D1 is grounded, and the cathode is connected with the 2 nd end of the first resistor R1 and the 1 st end of the second resistor R2; meanwhile, the voltage reference chip U1 is connected to the 2 nd end of the second resistor R2 and the first capacitor C2, respectively.
Therefore, in the embodiment, the delay circuit is formed by the first resistor R1, the second resistor R2 and the first capacitor C2, so that the circuit structure design is greatly simplified.
Example 4:
this embodiment differs from any of embodiments 1 to 3 only in that, as shown in fig. 1, the delay switching circuit further includes: a third resistor R3, a fourth resistor R4, and a first diode D2;
the cathode of the first diode D2 is connected to the power input terminal VIN, and the cathode is respectively connected to the 1 st end of the third resistor R3, the voltage reference chip U1, and the 2 nd end of the second resistor R2;
and the 2 nd end of the third resistor R3 is grounded.
Therefore, the input undervoltage protection can be realized through the third resistor R3, the fourth resistor R4 and the first diode D2, and specifically, the input undervoltage point of the circuit can be determined through the voltage division formula of the second resistor R2 and the third resistor R3.
When the input voltage of the power input terminal VIN is smaller than the reference voltage of the voltage reference chip U1, the G-pole voltage of the enhanced N MOSFET Q1 rises, so that the enhanced N MOSFET Q1 is turned on, and further, the driving voltage of the switching unit is pulled down to the ground, so that the switching unit is turned off, the output voltage drops to 0V gradually, and meanwhile, the energy stored in the first capacitor C2 can be rapidly released through the first diode D2.
Example 5:
this embodiment differs from any of embodiments 1 to 4 only in that, as shown in fig. 1, the delay switching circuit further includes: the fifth resistor R5, the second diode D4, the second capacitor C3, the second zener diode D3, the third zener diode D5 and the fourth zener diode D6;
the 1 st end of the fifth resistor R5 is connected with the voltage input end VIN, and the 2 nd end is connected with the D pole of the enhanced N MOSFET Q1;
the cathode of the second diode D4 is connected with the voltage input end VIN, and the anode of the second diode D4 is connected with the voltage output end VOUT;
one end of the second capacitor C3 is connected with the voltage output end VOUT, the other end of the second capacitor C is connected with the cathode of the third zener diode D5, and the anode of the third zener diode D5 is grounded;
the anode of the fourth zener diode D6 is connected to the voltage output terminal VOUT, and the cathode is connected to the cathode of the third zener diode D5;
the anode of the second zener diode D3 is grounded, and the cathode is connected to the voltage reference chip U1 and the G pole of the enhancement N MOSFET Q1, respectively.
When the input voltage drops to be smaller than the output voltage, the second diode D4 can be used for discharging rapidly, meanwhile, the second capacitor C3 and the fourth voltage stabilizing diode D6 can be used for protecting the switch unit from damage at the moment when the enhanced N MOSFET Q1 is turned on or turned off, and meanwhile, the voltage output by the fourth voltage stabilizing diode D6 can be released rapidly, so that larger surge current is avoided.
Meanwhile, when the switch unit is an NPN triode Q2, the third zener diode D5 may make the output voltage consistent with the voltage stabilizing value of the third zener diode D5 and the difference between the emitter voltages of the NPN triode Q2; when the switch unit is the enhancement N MOSFET Q2, the third zener diode D5 can make the output voltage consistent with the difference between the regulated value of the third zener diode D5 and the threshold voltage value of the enhancement N MOSFET Q2, thereby realizing stable output voltage.
Further, since the reference voltage of the voltage reference chip U1 is generally 1.25V or 2.5V, the first capacitor C2 may be a low withstand voltage, a large capacity, or a small size capacitor, and the number of capacitors may be increased appropriately according to the required delay time. Meanwhile, the fourth resistor R4 and the third resistor R3 are used for clamping the voltage reference chip U1 and the voltage of the connection point of the enhanced N MOSFET Q1, so that the circuit can be applied to high input voltage occasions.
In summary, the delay switch circuit has a simple structure, for example, the delay circuit structure is greatly simplified, so that the number of elements is reduced, the circuit size is reduced, and meanwhile, the functions of input undervoltage and output voltage stabilization are added, so that the delay start of the BOOST PFC circuit can be realized, and meanwhile, large surge current is avoided.
Although embodiments of the present utility model have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the spirit and scope of the utility model as defined by the appended claims and their equivalents.
Claims (10)
1. A delay switch circuit of a BOOST PFC circuit, comprising:
an input filter capacitor C1, one end of which is connected with a voltage input end VIN, and the other end of which is grounded;
one end of the output filter capacitor C4 is connected with the voltage output end VOUT connected with the BOOSTPFC circuit, and the other end of the output filter capacitor C4 is grounded;
the delay circuit is connected in parallel with two ends of the input filter capacitor C1;
a first zener diode D1 connected to the delay circuit for stabilizing an input voltage;
the voltage reference chip U1 is connected with the delay circuit and the ground;
an enhanced NMOSFET Q1, wherein the G electrode of the enhanced NMOSFET Q1 is connected with the voltage reference chip U1;
and the switching unit is respectively connected with the voltage reference chip U1, the enhanced NMOSFET Q1 and the voltage input end VOUT of the power supply.
2. The delay switch circuit of claim 1, wherein said switch unit comprises an NPN transistor Q2 having a base connected to a D pole of said enhanced nmosfet Q1, a collector connected to said voltage reference die U1, and an emitter connected to a voltage input VOUT of a power supply.
3. The delay switching circuit of claim 1 wherein the switching cell comprises an enhanced nmosfet q2 having its G-pole connected to the D-pole of the enhanced nmosfet q1, its S-pole connected to the voltage input VOUT, and its D-pole connected to the voltage reference chip U1.
4. The delay switch circuit of claim 1, wherein the delay circuit comprises: a first resistor R1, a second resistor R2, and a first capacitor C2;
the 1 st end of the first resistor R1 is connected with the voltage input end VIN, the 2 nd end is connected with the 1 st end of the second resistor R2, the 2 nd end of the second resistor R2 is connected with one end of the first capacitor C2, and the other end of the first capacitor C2 is grounded;
the anode of the first zener diode D1 is grounded, and the cathode is connected with the 2 nd end of the first resistor R1 and the 1 st end of the second resistor R2; the voltage reference chip U1 is connected to the 2 nd end of the second resistor R2 and the first capacitor C2, respectively.
5. The delay switch circuit of claim 1, wherein the delay switch circuit further comprises: a third resistor R3, a fourth resistor R4, and a first diode D2;
the cathode of the first diode D2 is connected to the power input terminal VIN, and the cathode is respectively connected to the 1 st end of the third resistor R3, the voltage reference chip U1, and the 2 nd end of the second resistor R2;
and the 2 nd end of the third resistor R3 is grounded.
6. The delay switch circuit of claim 1, wherein the delay switch circuit further comprises: a fifth resistor R5 and a second diode D4;
the 1 st end of the fifth resistor R5 is connected with the voltage input end VIN, and the 2 nd end of the fifth resistor R5 is connected with the D pole of the enhanced NMOSFET Q1;
the cathode of the second diode D4 is connected to the voltage input terminal VIN, and the anode is connected to the voltage output terminal VOUT.
7. The delay switch circuit of claim 6, wherein the delay switch circuit further comprises: the second capacitor C3, the second zener diode D3 and the third zener diode D5;
one end of the second capacitor C3 is connected to the voltage output terminal VOUT, the other end is connected to the cathode of the third zener diode D5, and the anode of the third zener diode D5 is grounded;
the anode of the second zener diode D3 is grounded, and the cathode is connected to the voltage reference chip U1 and the G pole of the enhanced nmosfet q1, respectively.
8. The delay switch circuit of claim 7, wherein the delay switch circuit further comprises: and the anode of the fourth zener diode D6 is connected with the voltage output end VOUT, and the cathode of the fourth zener diode D5 is connected with the cathode of the third zener diode D5.
9. The delay switch circuit of claim 1, wherein the voltage reference chip U1 reference voltage is 1.25V or 2.5V.
10. The delay switch circuit of claim 1, wherein a parasitic diode is connected between the S-pole and the D-pole of the enhanced NMOSFET Q1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321260165.3U CN219760863U (en) | 2023-05-23 | 2023-05-23 | Time delay switch circuit of BOOST PFC circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321260165.3U CN219760863U (en) | 2023-05-23 | 2023-05-23 | Time delay switch circuit of BOOST PFC circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219760863U true CN219760863U (en) | 2023-09-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321260165.3U Active CN219760863U (en) | 2023-05-23 | 2023-05-23 | Time delay switch circuit of BOOST PFC circuit |
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| Country | Link |
|---|---|
| CN (1) | CN219760863U (en) |
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2023
- 2023-05-23 CN CN202321260165.3U patent/CN219760863U/en active Active
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