CN213521662U - Simple impact current suppression circuit - Google Patents

Abstract

The utility model provides a simple and easy impulse current suppression circuit, including constant current source, N channel MOS pipe, first electric capacity and first stabilivolt, the circuit is equipped with positive input end, positive output end, negative input end and negative output end, positive input end with positive output end lug connection, the constant current source is followed positive input end is got the electricity, the grid of N channel MOS pipe is connected the first end of first electric capacity the negative pole of first stabilivolt with the current output end of constant current source, the source connection of N channel MOS pipe the second end of first electric capacity the positive pole of first stabilivolt with the negative input end, the drain electrode of N channel MOS pipe is connected the negative output end. The utility model discloses simple easy-to-use and effect are good, can restrain impulse current at reasonable within range, satisfy DC power supply system's application demand and relevant standard regulation.

Description

Simple impact current suppression circuit

Technical Field

The utility model belongs to the technical field of the new forms of energy technique and specifically relates to a simple and easy impulse current suppression circuit.

Background

The direct current power supply system has energy storage capacitors and filter capacitors with different capacities at an input end according to different power levels, and when the direct current power supply system is powered on and started, the capacitors are charged to generate larger impact current, and the impact current has larger interference on a power supply source, a load and other electric equipment, and can cause abnormal work or even damage of the direct current power supply system in serious cases. There is also a relevant provision in the GJB181B-2012 "aircraft supply characteristics" that the inrush current peak should be no more than 5 times the rated current and should return to the rated current within 0.1 s.

The existing direct current power supply system has a complex circuit structure for suppressing the impact current, has poor effect on suppressing the impact current, and cannot meet the application requirements and relevant standard regulations of the direct current power supply system.

SUMMERY OF THE UTILITY MODEL

In order to solve the problem, the utility model provides a simple and easy impulse current suppression circuit, this circuit is simple easy-to-use and excellent in effect, can restrain impulse current at reasonable within range, satisfies DC power supply system's application demand and relevant standard regulation.

The utility model discloses a following technical scheme realizes:

the utility model provides a simple and easy impulse current suppression circuit, including constant current source, N channel MOS pipe, first electric capacity and first stabilivolt, the circuit is equipped with positive input end, positive output end, negative input end and negative output end, positive input end with positive output end lug connection, the constant current source is followed positive input end is got the electricity, the grid of N channel MOS pipe is connected the first end of first electric capacity the negative pole of first stabilivolt with the current output end of constant current source, the source connection of N channel MOS pipe the second end of first electric capacity the positive pole of first stabilivolt with the negative input end, the drain electrode of N channel MOS pipe is connected the negative output end.

The constant current source further comprises a triode, a first resistor, a second resistor, a third resistor, a second voltage regulator tube and a diode, wherein the first end of the first resistor is connected with the cathode of the second voltage regulator tube and the positive input end, the second end of the first resistor is connected with the emitting electrode of the triode, the anode of the second voltage regulator tube is connected with the anode of the diode, the cathode of the diode is connected with the base electrode of the triode and the first end of the third resistor, the collector electrode of the triode is connected with the first end of the second resistor, the second end of the second resistor is connected with the grid electrode of the N-channel MOS tube, and the second end of the third resistor is connected with the negative input end.

Further, the utility model provides a simple and easy impulse current suppression circuit still includes fourth resistance and second electric capacity, the first end of fourth resistance is connected the first end of second electric capacity with the projecting pole of triode, the second end of fourth resistance is connected the second end of second electric capacity with the burden output.

Further, the utility model provides a simple and easy impulse current suppression circuit still is equipped with the delay adjustment end, the delay adjustment end connect in the second end of first resistance, the delay adjustment end with external adjustable resistance between the positive input.

Further, the utility model provides a simple and easy impulse current suppression circuit still includes the TVS pipe, the negative pole of TVS pipe is connected positive input end, the positive pole of TVS pipe is connected the negative input end.

The utility model has the advantages that:

the utility model discloses an increase N channel MOS pipe Q1 on the power negative line, the design delays regulating circuit and makes N channel MOS pipe Q1 open slowly, finally makes back level output voltage rise slowly, charges for the capacitive device of back level wave filter or DC/DC converter and provides the buffering, makes fast power-on process become the power-on process slowly to effectively reduce the impulse current that the electric capacity charges and arouse; the charging current of the constant current source can be adjusted through an external adjustable resistor, so that the rise time of the output voltage is adjusted; in addition, the utility model discloses increase TVS pipe D4 at the front end and can effectively restrain transient spike voltage 600V/10 mus/50 omega (requiring to GJB 181) or 400V/5 mus (requiring to GJB 151), the protection circuit can not overvoltage damage.

Drawings

Fig. 1 is a schematic diagram of a circuit structure according to an embodiment of the present invention.

Detailed Description

For a more clear and complete description of the technical solution of the present invention, the following description is made with reference to the accompanying drawings.

Referring to fig. 1, the utility model provides a simple and easy impulse current suppression circuit embodiment, including the constant current source, N channel MOS transistor Q1, first electric capacity C1 and first stabilivolt D1, the circuit is equipped with positive input end VIN +, positive output Vo, negative input VIN-and negative output GNDo, positive input end VIN + and positive output Vo lug connection, the constant current source is got from positive input end VIN +, the first end of first electric capacity C1 is connected to the grid of N channel MOS transistor Q1, the negative pole of first stabilivolt D1 and the current output end of constant current source, the second end of first electric capacity C1 is connected to the source of N channel MOS transistor Q1, the positive pole and the negative input VIN-of first stabilivolt D1, negative output GNDo is connected to the drain electrode of N channel MOS transistor Q1.

Specifically, the utility model discloses an increase N channel MOS pipe Q1 on the power negative line, the design delays regulating circuit and makes N channel MOS pipe Q1 open slowly, finally makes the later stage output voltage rise slowly, charges for the capacitive device of later stage wave filter or DC/DC converter and provides the buffering, makes the electricity process of going up soon become the electricity process of going up slowly to effectively reduce the impact current that electric capacity charges and arouse. The utility model discloses a constant current source charges for first electric capacity C1, makes the voltage on the C1 can linear rising, and this voltage also adds between N channel MOS pipe Q1's grid and source electrode to control N channel MOS pipe Q1 and open slowly. The first voltage regulator tube D1 provides voltage regulation protection for the grid electrode of the N-channel MOS tube Q1, the grid electrode-source electrode overvoltage breakdown after the N-channel MOS tube Q1 is completely conducted is prevented, and the first capacitor C1 can eliminate the misconduction of the N-channel MOS tube Q1 caused by parasitic parameters at the moment of electrifying.

Further, referring to fig. 1, in the embodiment of the present invention, the constant current source includes a triode Q2, a first resistor R1, a second resistor R2, a third resistor R3, a second regulator D2 and a diode D3, a first end of the first resistor R1 is connected to a cathode and a positive input terminal VIN + of the second regulator D2, a second end of the first resistor R1 is connected to an emitter of the triode Q2, an anode of the second regulator D2 is connected to an anode of the diode D3, a cathode of the diode D3 is connected to a base of the triode Q2 and a first end of the third resistor R3, a collector of the triode Q2 is connected to a first end of the second resistor R2, a second end of the second resistor R2 is connected to a gate of the N-channel MOS transistor Q1, and a second end of the third resistor R3 is connected to a negative input terminal VIN-.

The diode D32 in the constant current source can counteract the temperature drift caused by the PN junction of the transistor Q2, so that the current flowing through the first resistor R1 is equal to the regulated voltage value of the second regulator D2 divided by the resistance value of R1. In addition, a control circuit is formed by the triode Q2, the second resistor R2, the first voltage regulator tube D1, the first capacitor C1 and the third resistor R3, so that the N-channel MOS tube Q1 works in a saturation region, and the gate voltage and the output voltage of the N-channel MOS tube Q1 rise in proportion in the charging process. The transistor Q2 is a PNP transistor.

It should be noted that, on the premise that the requirement of withstand voltage and overcurrent is met, the N-channel MOS transistor Q1 should ensure that the temperature cannot exceed the junction temperature during steady-state operation, and in the circuit, the N-channel MOS transistor Q1 operates in two operating regions, namely a saturation region and a deep linear region. In the power-on process, the N-channel MOS tube Q1 works in a saturation region, and at the moment, the N-channel MOS tube Q1 is slowly conducted to play a role in inhibiting impact current; after the process of suppressing the impulse current is finished, the N-channel MOS tube Q1 works in a linear region, at the moment, the N-channel MOS tube Q1 is completely switched on, the power consumption is mainly conduction loss, and the drain-source on-resistance RDS (on) is required to be as small as possible when the N-channel MOS tube Q1 is selected. If the minimum working voltage required by the circuit is lower (such as 8V), at least, the N-channel MOS tube Q1 can be completely switched on when the grid voltage is 5V, and an MOS tube with low logic switching-on is selected. Due to the particularity of the working principle of the circuit design, the on-resistance of the N-channel MOS transistor Q1 is large at low input voltage, and excessive current can cause overheating damage, and special attention needs to be paid to the test conditions and methods. The load requires proper under-voltage protection, the passing current of the N-channel MOS tube Q1 at low input voltage can be limited, and the power consumption is controlled; if the load has no undervoltage protection or the undervoltage protection voltage is low, the circuit needs to be electrified first and then the load is carried, otherwise, the circuit fails.

Further, referring to fig. 1, in the embodiment of the present invention, the present invention further includes a fourth resistor R4 and a second capacitor C2, a first end of the fourth resistor R4 is connected to a first end of the second capacitor C2 and an emitter of the transistor Q2, and a second end of the fourth resistor R4 is connected to a second end of the second capacitor C2 and the negative output terminal GNDo. The capacitor C2 is charged through the constant current source circuit, so that the emitter voltage of the triode Q2 slowly rises, the turn-on time of the triode Q2 is delayed, the charging time of the capacitor C1 is further controlled, and the turn-on time and the voltage rising slope of the MOS transistor Q1 are set. The resistor R4 is used to provide a charge bleed-off path for the capacitor C2 when power is off, so that the circuit can be reset quickly.

Further, referring to fig. 1, in the embodiment of the present invention, the circuit is further provided with a delay adjustment end RISE, the delay adjustment end RISE is connected to the second end of the first resistor R1, and an external adjustable resistor is connected between the delay adjustment end RISE and the positive input end VIN +. The charging current of the constant current source can be adjusted through the external adjustable resistor, so that the rise time of the output voltage is adjusted.

Further, referring to fig. 1, in the embodiment of the present invention, a TVS (Transient Voltage super, Transient diode) D4 is further included, the cathode of the TVS D4 is connected to the positive input terminal VIN +, and the anode of the TVS D4 is connected to the negative input terminal VIN-. Because the utility model discloses generally arrange power supply system's foremost in during practical application, increase TVS pipe D4 and can effectively restrain transient spike voltage 600V 10 mus 50 omega (to GJB181 requirement) or 400V 5 mus (to GJB151 requirement), protection circuit can not overvoltage damage.

Of course, the present invention can also have other various embodiments, and based on the embodiments, those skilled in the art can obtain other embodiments without any creative work, and all of them belong to the protection scope of the present invention.

Claims (5)

1. A simple surge current suppression circuit is characterized by comprising a constant current source, an N-channel MOS tube (Q1), a first capacitor (C1) and a first voltage regulator tube (D1), wherein the circuit is provided with a positive input end (VIN +), a positive output end (Vo), a negative input end (VIN-) and a negative output end (GNDo), the positive input end (VIN +) is directly connected with the positive output end (Vo), the constant current source gets power from the positive input end (VIN +), the grid electrode of the N-channel MOS tube (Q1) is connected with the first end of the first capacitor (C1), the cathode of the first voltage regulator tube (D1) and the current output end of the constant current source, the source electrode of the N-channel MOS tube (Q1) is connected with the second end of the first capacitor (C1), the anode of the first voltage regulator tube (D1) and the negative input end (VIN-), the drain electrode of the N-channel MOS tube (Q1) is connected with the negative output end (GNDo).

2. The simple inrush current suppression circuit as claimed in claim 1, wherein the constant current source comprises a transistor (Q2), a first resistor (R1), a second resistor (R2), a third resistor (R3), a second regulator (D2) and a diode (D3), a first end of the first resistor (R1) is connected to a cathode and the positive input terminal (VIN +) of the second regulator (D2), a second end of the first resistor (R1) is connected to an emitter of the transistor (Q2), an anode of the second regulator (D2) is connected to an anode of the diode (D3), a cathode of the diode (D3) is connected to a base of the transistor (Q2) and a first end of the third resistor (R3), a collector of the transistor (Q2) is connected to a first end of the second resistor (R2), a second end of the second resistor (R2) is connected to a gate of the MOS channel (Q1), a second terminal of the third resistor (R3) is connected to the negative input terminal (VIN-).

3. The simplified inrush current suppression circuit as claimed in claim 2, further comprising a fourth resistor (R4) and a second capacitor (C2), wherein a first terminal of the fourth resistor (R4) is connected to a first terminal of the second capacitor (C2) and an emitter of the transistor (Q2), and a second terminal of the fourth resistor (R4) is connected to a second terminal of the second capacitor (C2) and the negative output terminal (GNDo).

4. The simplified inrush current suppression circuit as claimed in claim 3, further comprising a delay adjustment terminal (RISE), wherein the delay adjustment terminal (RISE) is connected to the second terminal of the first resistor (R1), and an adjustable resistor is externally connected between the delay adjustment terminal (RISE) and the positive input terminal (VIN +).

5. The simplified surge current suppression circuit as claimed in claim 4, further comprising a TVS transistor (D4), wherein a cathode of said TVS transistor (D4) is connected to said positive input terminal (VIN +), and an anode of said TVS transistor (D4) is connected to said negative input terminal (VIN-).

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