CN218829901U - Analog-digital conversion module with switchable multichannel frequency - Google Patents

Abstract

The utility model discloses a changeable analog-to-digital conversion module of multichannel frequency, divide ware, phase-locked loop PLL, amplifier A, amplifier B, merit to divide network A, merit to divide network B, radio frequency switch A, radio frequency switch B, radio frequency switch C and clock distributor including crystal oscillator, digital phase-locked loop, crystal oscillator constitute inside reference and input reference coherent circuit, the signal input part that the ware was divided to the merit connects outside input reference signal, the utility model provides a low spurious low phase noise's of broadband L wave band frequency synthesizer of small, with low costs, the debugging degree of difficulty is little, control accuracy and reliability are high. The synthesized signal can output various dot frequency signals after passing through the frequency divider, and the signals are switched after passing through the switch filtering group, and the signals are converted by the next-stage low-frequency clock distributor and then output LVPECL level.

Description

Analog-digital conversion module with switchable multichannel frequency

Technical Field

The utility model relates to the technical field of integrated circuit, specifically a changeable analog-to-digital conversion module of multichannel frequency.

Background

The frequency synthesizer is used as an important component module of a communication system, various indexes of the frequency synthesizer are very critical, particularly phase noise and spurious signals, and the phase noise influences various performances of the communication system, for example, in a receiver, the phase noise determines the signal-to-noise ratio of the receiver, adjacent channel suppression and the like; the spurious indicators affect the sensitivity of the system receiver.

Frequency synthesizers are generally implemented in three ways: direct frequency synthesis, direct digital frequency synthesis, and indirect frequency synthesis (i.e., phase Locked Loop (PLL)). The direct frequency synthesizer has the advantages of high frequency conversion speed, wide bandwidth, good phase noise index and the disadvantages of complex circuit structure, large power consumption, large volume and high cost. The direct digital frequency synthesizer has the advantages of high frequency conversion speed, high frequency resolution, good phase noise performance, lower realization frequency and poorer spurious suppression. Indirect frequency synthesizers have the advantage that a wider frequency range and higher frequencies can be achieved, as well as excellent spur rejection, and the disadvantage that the frequency conversion time and frequency resolution are poor. How to select a proper frequency synthesis scheme to optimize the overall performance becomes a difficult problem of engineering design.

For example, a multi-channel analog-to-digital conversion apparatus disclosed in patent No. CN2938573Y discloses a technique capable of performing analog-to-digital conversion by automatically switching a plurality of analog input signals, and performs signal amplification by using an amplifier, but since a clutter interference signal is also amplified simultaneously with signal amplification, it is not very accurate, and improvement is required.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a changeable analog-to-digital conversion module of multichannel frequency to solve the current multichannel analog-to-digital conversion device that proposes in the above-mentioned background art and when enlargiing the signal, also enlargied clutter interference signal equally, consequently its problem of improving precision that can not be fine.

In order to achieve the above object, the utility model provides a following technical scheme:

a multi-channel frequency switchable analog-to-digital conversion module comprises a crystal oscillator, a digital phase-locked loop, a 2-power divider, a phase-locked loop PLL, an amplifier A, an amplifier B, a power dividing network A, a power dividing network B, a radio frequency switch A, a radio frequency switch B, a radio frequency switch C and a clock distributor, wherein the digital phase-locked loop and the crystal oscillator form an internal reference and input reference coherent circuit, the input end of the internal reference and input reference coherent circuit is connected with a 10MHz reference signal, the output end of the internal reference and input reference coherent circuit is connected with the 2-power divider, the 2-power divider outputs two paths, one path sequentially passes through the amplifier A, the power dividing network A, the radio frequency switch A and the radio frequency switch C to the clock distributor, and the other path sequentially passes through the phase-locked loop, the amplifier B, the power dividing network B, the radio frequency switch B and the radio frequency switch C to the clock distributor.

As a further technical solution of the present invention: the model of the phase-locked loop PLL is HMC830LP6G.

As a further technical solution of the present invention: the amplifier A and the amplifier B are of the type TQP3M9008.

As a further technical scheme of the utility model: the model of the digital phase-locked loop is ADF4002.

As a further technical solution of the present invention: the radio frequency switch A, the radio frequency switch B and the radio frequency switch C are HMC8038LP4CE in model number.

As a further technical solution of the present invention: the model of the clock distributor is ADCLK905.

As a further technical solution of the present invention: the crystal oscillator is a 120Hz crystal oscillator.

Compared with the prior art, the beneficial effects of the utility model are that: the utility model provides a L wave band frequency synthesizer of low spurious low phase noise of broadband that small, with low costs, the debugging degree of difficulty is little, control accuracy and reliability are high. The synthesized signal can output various dot frequency signals after passing through the frequency divider, and the signals are switched after passing through the switch filtering group, and the signals are converted by the next-stage low-frequency clock distributor and then output LVPECL level.

Drawings

Fig. 1 is an overall schematic block diagram of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

As shown in fig. 1, a multi-channel frequency switchable analog-to-digital conversion module includes internal reference and input reference coherent circuits (internal 10MHz crystal oscillator and digital phase-locked loop), a phase-locked loop PLL of an integrated VCO, a low-pass filter, an amplifier, the internal reference and input reference coherent circuits: the external reference 10MHz is locked at 120MHz through the digital phase-locked loop ADF4002, internal 100MHz and external reference in-phase coherent are completed, the 120MHz reference is sent to the phase-locked loop PLL1 of the integrated VCO, and the fixed point frequency of the output target frequency f is locked. The signals of 120MHz and f are amplified by an amplifier, clutter signals outside a low-pass filter f pass through a power division network and then are divided to output 20 paths of signals, the 20 paths of power division signals enter a switch (HMC 8038LP4 CE) group and then are switched, and output signals are converted by a low-frequency clock distributor (ADCLK 905) of a final stage and then output LVPECL levels.

In this design, the model of the PLL is HMC830LP6G. The amplifier a and the amplifier B are of type TQP3M9008. The digital phase-locked loop is in the ADF4002 model. The radio frequency switch A, the radio frequency switch B and the radio frequency switch C are in the model of HMC8038LP4CE. The clock distributor is model ADCLK905. The crystal oscillator is a 120Hz crystal oscillator.

After the technical scheme is adopted, the phase noise index is achieved by adjusting the loop of the frequency synthesizer, and the output of the low-frequency clock distributor is matched so that the low-frequency clock distributor can output a standard square wave signal. The utility model discloses simple structure, the integrated level is high, and debugging work load is little, and the reliability is high, and is with low costs, has popularization and application and worth.

In the product configuration, the highest output frequency is in the secondary L wave band, and the HMC830LP6GE is selected.

Meanwhile, according to the scheme, as shown in table 1, the PLL chip of the similar wideband integrated VCO is replaced, and different frequencies can be output. Table 1 is a family of wideband integrated VCO PLL chips.

Table 1: wideband integrated VCO PLL chip model and frequency range data table

Integrated VCO PLL model	Frequency range
		HMC833	25MHz～6000MHz
LMX2572	28MHz～6400MHz

It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims (7)

1. A multi-channel frequency switchable analog-to-digital conversion module comprises a crystal oscillator, a digital phase-locked loop, a 2 power divider, a phase-locked loop PLL, an amplifier A, an amplifier B, a power dividing network A, a power dividing network B, a radio frequency switch A, a radio frequency switch B, a radio frequency switch C and a clock distributor.

2. The multi-channel frequency switchable analog-to-digital conversion module of claim 1, wherein the model of the phase locked loop PLL is HMC830LP6G.

3. A multi-channel frequency switchable analog-to-digital conversion module as claimed in claim 1, characterized in that the type of the amplifiers a and B is TQP3M9008.

4. The multi-channel frequency-switchable analog-to-digital conversion module of claim 1, wherein the digital phase-locked loop is of the ADF4002 type.

5. The multi-channel frequency switchable analog-to-digital conversion module of claim 1, wherein the radio frequency switch a, the radio frequency switch B and the radio frequency switch C are of the type HMC8038LP4CE.

6. The multi-channel frequency switchable analog-to-digital conversion module of claim 1, wherein the clock divider is of the type ADCLK905.

7. The multi-channel frequency switchable analog-to-digital conversion module of claim 1, wherein the crystal oscillator is a 120Hz crystal oscillator.

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