CN218829599U - NMOS output control circuit of isolated high-level end - Google Patents
NMOS output control circuit of isolated high-level end Download PDFInfo
- Publication number
- CN218829599U CN218829599U CN202223399047.9U CN202223399047U CN218829599U CN 218829599 U CN218829599 U CN 218829599U CN 202223399047 U CN202223399047 U CN 202223399047U CN 218829599 U CN218829599 U CN 218829599U
- Authority
- CN
- China
- Prior art keywords
- output
- capacitor
- resistor
- nmos
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Dc-Dc Converters (AREA)
Abstract
The application relates to an isolated NMOS output control circuit with a high-level end, which belongs to the technical field of integrated circuits and comprises a driving unit, a first voltage signal and a second voltage signal, wherein the driving unit comprises two input ends and an output end; the input end of the isolation unit receives an output signal of the MCU as a driving control signal, the first output end of the isolation unit is connected with the output end of the driving unit, and the second output end of the isolation unit outputs a second voltage signal; and the grid electrode of the NMOS tube receives the second voltage signal, the source electrode of the NMOS tube receives the first voltage signal, and the drain electrode of the NMOS tube is used for being connected with the anode of the adjustable power supply. This application has following effect, under the same condition, compares PMOS pipe control mode, and this application has reduced the size of device, has reduced manufacturing cost, and has good electrical insulation ability and interference killing feature.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to an NMOS output control circuit of an isolated high-level end.
Background
In the aspect of controlling the power output, especially in the high-level switch control, a PMOS switch control mode is generally adopted, and since PMOS charge carriers are minority carriers and NMOS charge carriers are majority carriers, the on-resistance of PMOS is much larger than NMOS under the same DIE-SIZE, PMOS needs larger SIZE and higher price under the condition of passing the same current, which is not beneficial to the product cost control.
Disclosure of Invention
In order to solve the problem that the size of the existing PMOS switch control mode is large and the cost is high, the application provides an isolated NMOS output control circuit with a high-level end.
In a first aspect, the present application provides an isolated NMOS output control circuit with a high-level end, which adopts the following technical solution:
an isolated high-level-end NMOS output control circuit, comprising:
a drive unit including two input terminals and an output terminal, an input of the drive unit
The end receives alternating current, the other input end of the driving unit is used for receiving a SW output signal of the MCU, and the output end of the driving unit outputs a first voltage signal;
an isolation unit, the input end of which receives the output signal of the MCU as the drive control
A first output end of the isolation unit is connected with an output end of the driving unit, and a second output end of the isolation unit outputs a second voltage signal;
a gate of the NMOS transistor receives the second voltage signal, and the NMOS transistor
The source electrode receives the first voltage signal, the drain electrode of the NMOS tube is used for being connected with the anode of the adjustable power supply, the source electrode of the NMOS tube is used as the output anode of the control circuit, and the cathode of the power supply is used as the output cathode of the control circuit.
By adopting the technical scheme, the driving unit provides a driving voltage to the source electrode of the NMOS tube for the NMOS tube, the driving control signal is input to the grid electrode of the NMOS tube after being converted by the isolation unit, the first voltage signal of the driving unit is a signal after voltage reduction, vg is larger than Vs, vgs is larger than Vth, the NMOS tube can be switched on by taking the first voltage signal as the driving voltage of the NMOS tube, switching on and off of the power supply can be controlled through switching on and off of the NMOS tube switch, the NMOS tube is placed at a high level position, and under the same condition, compared with a PMOS tube control mode, the size of a device is reduced, the production cost is reduced, the NMOS tube switch has good electrical insulation capacity and anti-interference capacity, and the NMOS tube switch has practical value.
Preferably, the driving unit includes a first capacitor and a voltage reduction unit, the voltage reduction unit includes a bidirectional diode, a second capacitor, a third capacitor and a fourth capacitor, one end of the first capacitor is used for connecting a SW pin of the MCU, the other end of the first capacitor is connected to the third pin of the bidirectional diode, the first pin of the bidirectional diode receives an alternating current signal, the second pin of the bidirectional diode outputs a first voltage signal, and the second capacitor, the third capacitor and the fourth capacitor are connected in parallel between the first pin and the second pin of the bidirectional diode.
By adopting the technical scheme, a signal output by the SW pin of the MCU is filtered by the first capacitor and then is input into the third pin of the bidirectional diode, an alternating current signal is input into the first pin of the bidirectional diode, and is bootstrapped by the voltage of the bidirectional diode to output a voltage signal to the source electrode of the NMOS tube, and the voltage signal is a voltage signal obtained by reducing the DC voltage so as to meet the conduction condition of the NMOS tube.
Preferably, the isolation unit comprises an optical coupler, a first resistor and a second resistor, wherein the positive electrode of the input end of the optical coupler is connected with one end of the first resistor, the other end of the first resistor receives a driving control signal, the negative electrode of the input end of the optical coupler is grounded, the output collector of the optical coupler is connected with the output end of the driving unit, the output emitter of the optical coupler is connected with one end of the second resistor, and the other end of the second resistor is connected with the grid electrode of the NMOS tube.
By adopting the technical scheme, the drive control signal is input into the input anode of the optical coupler through the first resistor, the voltage signal is transmitted to the grid electrode of the NMOS tube through the electro-optic-electric conversion, and the input and the output of the optical coupler are isolated from each other, so that the circuit has good electrical insulation capacity and anti-interference capacity, and the running stability of the circuit is improved.
Preferably, the source of the NMOS transistor and the output end of the isolation unit are connected to a first voltage regulator diode, the negative electrode of the first voltage regulator diode is connected to the output end of the isolation unit, the positive electrode of the first voltage regulator diode is connected to the source of the NMOS transistor, and a third resistor is further connected between the gate and the source of the NMOS transistor.
By adopting the technical scheme, the first voltage stabilizing diode is reversely connected in the circuit and has a clamping function after being reversely broken down, the voltage can be clamped to a proper value to meet the voltage requirement of the circuit, the third resistor is connected between the grid electrode and the source electrode of the NMOS tube, the bias voltage can be provided for the NMOS tube, the effect of the bleeder resistor can be played, and the grid electrode and the source electrode of the NMOS tube are protected.
Preferably, a fifth capacitor and a sixth capacitor are connected between the NMOS transistor and the power supply, one end of the fifth capacitor is connected to the positive electrode of the power supply, the other end of the fifth capacitor is connected to the negative electrode of the power supply, one end of the sixth capacitor is connected to the positive electrode of the power supply, and the other end of the sixth capacitor is connected to the negative electrode of the power supply.
Through adopting above-mentioned technical scheme, fifth capacitor C5 and sixth capacitor C6 can influence switch's drive speed and the shock effect of circuit, if the capacitor discreteness of chooseing for use is great, also can grow to multitube parallel operation's synchronous drive influence.
Preferably, the power supply further comprises an energy storage unit, an input end of the energy storage unit is connected to the source electrode of the NMOS transistor, and an output end of the energy storage unit is used as an output end of the control circuit to output a voltage signal.
By adopting the technical scheme, the energy storage unit stores the output of the NMOS tube and the power supply and converts the electric energy.
Preferably, the energy storage unit includes a seventh capacitor, an eighth capacitor, a second zener diode, a fourth resistor, and a fifth resistor, the seventh capacitor and the eighth capacitor are connected in parallel and are connected between the source of the NMOS transistor and the negative electrode of the power supply, the negative electrode of the second zener diode is connected to the source of the NMOS transistor, the positive electrode of the second zener diode is connected to the negative electrode of the power supply, one end of the fourth resistor is connected to the source of the NMOS transistor, the fourth resistor and the fifth resistor are connected in series, one end of the fifth resistor, which is away from the fourth resistor, is connected to the negative electrode of the power supply and is grounded, and a connection node of the fourth resistor and the fifth resistor is used for outputting the sampling voltage.
By adopting the technical scheme, the seventh capacitor and the eighth capacitor are used for energy storage filtering, the second voltage stabilizing diode can clamp the voltage to a proper value, and the connecting node of the fourth resistor and the fifth resistor is used for monitoring the output voltage to ensure the normal operation of the circuit.
In summary, the present application includes at least one of the following beneficial technical effects:
1. through the source electrode of the input NMOS pipe after stepping down drive voltage, drive control voltage passes through the grid that the opto-coupler input NMOS pipe to make Vg be greater than Vs, and Vgs is greater than Vth, the NMOS pipe can switch on, has realized switching on and off of coming control power through switching on and off of control NMOS pipe switch, thereby can replace the control mode of PMOS pipe, has reduced the size of device, has reduced manufacturing cost.
2. The optocoupler has the characteristics of mutual isolation of input and output, unidirectional transmission of electric signals and the like, so that the circuit has good electric insulation capacity and anti-interference capacity, and the stability of the circuit during operation is improved.
Drawings
Fig. 1 is a circuit connection structure diagram of an isolated high-level NMOS output control circuit according to an embodiment of the present application.
Description of reference numerals: 1. a drive unit; 2. a voltage reduction unit; 3. an isolation unit; 4. and an energy storage unit.
Detailed Description
The present application is described in further detail below with reference to fig. 1.
The embodiment of the application discloses an NMOS output control circuit at an isolated high-level end. Referring to fig. 1, includes:
a drive unit 1 having two input terminals and an output terminal, one input terminal of the drive unit 1 being connected to
Receiving alternating current, wherein the other input end of the driving unit 1 is used for being connected with a SW pin of the MCU and receiving a DC voltage reduction signal from the MCU, and the output end of the driving unit 1 outputs a first voltage signal;
an isolation unit 3, the input end of the isolation unit 3 receives the output signal of the MCU as a driving control signal,
a first output end of the isolation unit 3 is connected with an output end of the driving unit 1, and a second output end of the isolation unit 3 outputs a second voltage signal;
a gate of the NMOS transistor Q1 receives a second voltage signal, and a source of the NMOS transistor Q1
And receiving a first voltage signal, wherein the drain electrode of the NMOS tube Q1 is used for connecting the anode of the adjustable power supply P1.
The input end of the energy storage unit 4 is connected with the source electrode of the NMOS tube Q1, the first output end of the energy storage unit 4 is used as the output anode of the control circuit, and the second output end of the energy storage unit 4 is connected with the cathode of the power supply and used as the output cathode of the control circuit.
NMOS pipe Q1 connects the positive terminal at the power, be in the high level position, this application provides drive unit 1 and provides a drive voltage to NMOS pipe Q1's source electrode for NMOS pipe Q1, drive control signal passes through the grid of isolation unit 3 input NMOS pipe Q1, and drive unit 1's first voltage signal is for the signal after the step-down, vg is greater than Vs so, it is greater than Vth (the opening voltage of NMOS pipe) to establish Vgs, it accords with the condition of switching on of NMOS pipe Q1 to use first voltage signal as drive voltage, thereby make NMOS pipe Q1 can switch on, NMOS pipe Q1 is as the switch, adjust the different voltage of power input, switch on and shut off of realization power through switching on and shut off of NMOS pipe Q1, thereby realized NMOS pipe Q1 to power P1's on-off control, compare PMOS pipe's control mode, the size of device has been reduced under the same condition, and the cost is also reduced, and has practical value extremely.
The driving unit 1 comprises a first capacitor C1 and a voltage reduction unit 2, the voltage reduction unit 2 comprises a bidirectional diode D1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4, one end of the first capacitor C1 is used for being connected with a SW pin of an MCU (microprogrammed control Unit), a DC voltage reduction signal from the MCU is received, the other end of the first capacitor C1 is connected with a third pin of the bidirectional diode D1, a first pin of the bidirectional diode D1 receives a 32V alternating current signal, a second pin of the bidirectional diode D1 outputs a first voltage signal, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are connected in parallel and are connected between the first pin and the second pin of the bidirectional diode D1.
Voltage signals output by the SW pin of the MCU enter the third pin of the bidirectional diode D1 after being filtered by the first capacitor C1, DC32V alternating current is input into the first pin of the bidirectional diode D1, voltage bootstrap is realized by the bidirectional diode D1, and the second pin of the bidirectional diode D1 outputs the voltage signals after voltage reduction to the source electrode of the NMOS tube Q1 so as to meet the conduction condition of the NMOS tube Q1.
Isolation unit 3 includes opto-coupler U1, first resistor R1 and second resistor R2, the anodal one end of connecting first resistor R1 of input of opto-coupler U1, first resistor R1's the other end is used for receiving MCU's output voltage signal as drive control signal, opto-coupler U1's input negative pole ground connection, bidirectional diode D1 and fourth capacitor C4's connected node is connected to opto-coupler U1's output collector, second resistor R2's one end is connected to opto-coupler U1's output emitter, NMOS pipe Q1's grid is connected to second resistor R2's the other end.
MCU's output signal passes through the input positive terminal of first resistor R1 input opto-coupler U1 as drive control signal, through electricity-photoelectricity-electric signal conversion again, with voltage signal input to NMOS pipe Q1's grid to realize the effect of input and output isolation, because opto-coupler U1's input/output is isolated each other, and the transmission of signal of telecommunication has characteristics such as unidirectionality, therefore has good electric insulating ability and interference killing feature, has promoted the stability of circuit.
A first voltage stabilizing diode D2 is further connected between the source electrode of the NMOS tube Q1 and the other end of the second resistor R2, the negative electrode of the first voltage stabilizing diode D2 is connected with the other end of the second resistor R2, the positive electrode of the first voltage stabilizing diode D2 is connected with the source electrode of the NMOS tube Q1, a third resistor R3 is further connected between the grid electrode of the NMOS tube Q1 and the source electrode, one end of the third resistor R3 is connected with the connection node of the grid electrode of the NMOS tube Q1 and the negative electrode of the first voltage stabilizing diode D2, the other end of the third resistor R3 is connected with the connection node of the source electrode of the NMOS tube Q1 and the positive electrode of the first voltage stabilizing diode D2, and the drain electrode of the NMOS tube Q1 is connected with the positive electrode of the power supply P1.
The first voltage stabilizing diode D1 is reversely connected in the circuit, the voltage is clamped to a proper value by utilizing the clamping function after the reverse breakdown of the diode caused by the reverse breakdown voltage, and the third resistor R3 is connected between the grid electrode and the source electrode of the NMOS tube Q1, so that the bias voltage can be provided for the field effect tube, and the effect of a bleeder resistor can be realized to protect the grid electrode and the drain electrode of the NMOS tube Q1.
A fifth capacitor C5 and a sixth capacitor C6 are further connected between the NMOS transistor Q1 and the power supply P1, the fifth capacitor C5 and the sixth capacitor C6 are connected in parallel, one end of the fifth capacitor C5 and one end of the sixth capacitor C6 are connected to the positive electrode of the power supply P1, and the other end of the fifth capacitor C5 and the other end of the sixth capacitor C6 are connected to the negative electrode of the power supply P1.
The fifth capacitor C5 and the sixth capacitor C6 can affect the driving speed of the power switch and the oscillation effect of the circuit, and if the discreteness of the selected capacitors is large, the influence on the synchronous driving of the parallel operation of multiple tubes can also be large.
The energy storage unit 4 comprises a seventh capacitor C7, an eighth capacitor C8, a second voltage stabilizing diode D3, a fourth resistor D4 and a fifth resistor D5, one end of the seventh capacitor C7 is connected with the connection node of the source of the NMOS transistor Q1 and the third resistor R3, the other end of the seventh capacitor C7 is connected with the negative electrode of the power supply P1, the eighth capacitor C8 and the seventh capacitor C7 are connected in parallel, the negative electrode of the second voltage stabilizing diode D3 is connected with the source of the NMOS transistor Q1, the positive electrode of the second voltage stabilizing diode D3 is connected with the negative electrode of the power supply P1, one end of the fourth resistor R4 is connected with the source of the NMOS transistor Q1, the fifth resistor R5 is connected with the fourth resistor R4 in series, and one end of the fifth resistor R5 far away from the fourth resistor R4 is connected with the negative electrode of the power supply P1 and grounded. The connection node of the fourth resistor R4 and the source electrode of the NMOS tube Q1 is used as the output anode P2 of the control circuit, the connection node of the fifth resistor R5 and the cathode of the power supply P1 is used as the output cathode P3 of the control circuit, and the connection node of the fourth resistor R4 and the fifth resistor R5 is used for outputting the sampling voltage.
After the output voltage passes through the energy storage unit 4, the energy is stored and converted, and finally, the energy is released to an output positive electrode and an output negative electrode of the control circuit for use, and a sampling voltage is output at a connection node of the fourth resistor R4 and the fifth resistor R5 and used for monitoring the output voltage, so that the normal operation of the circuit is ensured.
The implementation principle of the NMOS output control circuit of the isolated high-level end in the embodiment of the present application is as follows: alternating current signal and MCU's DC step-down signal pass through two-way diode D1 effect and realize that the output voltage signal after the voltage bootstrapping to NMOS pipe Q1's source after the step-down, MCU's output voltage is as drive control signal, input NMOS pipe Q1's grid after the isolation through opto-coupler U1 conversion, satisfy NMOS pipe Q1's the condition of switching on, vg is greater than Vs, and Vgs is greater than Vth, thereby realize switching on and shutting off of realizing power P1 through switching on and shutting off of NMOS pipe Q1, and this application NMOS pipe Q1 connects at power P1's positive terminal, also realized under the high level, NMOS pipe Q1's output control with isolation function, thereby device size and cost have been reduced.
The above are preferred embodiments of the present application, and the scope of protection of the present application is not limited thereto, so: all equivalent changes made according to the structure, shape and principle of the present application shall be covered by the protection scope of the present application.
Claims (7)
1. An isolated high-level-side NMOS output control circuit, comprising:
a drive unit (1) comprising two input terminals and an output terminal, one of said drive unit (1)
The input end of the driving unit (1) receives alternating current, the other input end of the driving unit (1) is used for receiving an SW output signal of an MCU, and the output end of the driving unit (1) outputs a first voltage signal;
the input end of the isolation unit (3) receives the output signal of the MCU as a drive
A first output end of the isolation unit (3) is connected with an output end of the driving unit (1), and a second output end of the isolation unit (3) outputs a second voltage signal;
the grid electrode of the NMOS tube receives the second voltage signal, and the grid electrode of the NMOS tube is connected with the first voltage signal
The source electrode receives the first voltage signal, the drain electrode of the NMOS tube is used for being connected with the anode of the adjustable power supply, the source electrode of the NMOS tube is used as the output anode of the control circuit, and the cathode of the power supply is used as the output cathode of the control circuit.
2. The isolated high-level-end NMOS output control circuit according to claim 1, wherein said driving unit (1) comprises a first capacitor and a voltage-dropping unit (2), said voltage-dropping unit (2) comprises a bidirectional diode, a second capacitor, a third capacitor and a fourth capacitor, one end of said first capacitor is used for connecting the SW pin of the MCU, the other end of said first capacitor is connected to the third pin of said bidirectional diode, the first pin of said bidirectional diode receives an ac signal, the second pin of said bidirectional diode outputs a first voltage signal, and said second, third and fourth capacitors are connected in parallel between the first pin and the second pin of said bidirectional diode.
3. The isolated high-level-end NMOS output control circuit according to claim 1, wherein the isolation unit (3) comprises an optocoupler, a first resistor and a second resistor, wherein an input end of the optocoupler is connected with an anode of a positive electrode of the first resistor, the other end of the first resistor receives a driving control signal, an input end of the optocoupler is grounded, an output collector of the optocoupler is connected with an output end of the driving unit (1), an output emitter of the optocoupler is connected with one end of the second resistor, and the other end of the second resistor is connected with a grid electrode of the NMOS transistor.
4. The isolated high-level-end NMOS output control circuit according to claim 1, wherein a first zener diode is connected between the source of the NMOS transistor and the output end of the isolation unit (3), the negative pole of the first zener diode is connected to the output end of the isolation unit (3), the positive pole of the first zener diode is connected to the source of the NMOS transistor, and a third resistor is further connected between the gate and the source of the NMOS transistor.
5. The isolated high-level-end NMOS output control circuit according to claim 1, wherein a fifth capacitor and a sixth capacitor are connected between the NMOS transistor and the power supply, one end of the fifth capacitor is connected to an anode of the power supply, the other end of the fifth capacitor is connected to a cathode of the power supply, one end of the sixth capacitor is connected to the anode of the power supply, and the other end of the sixth capacitor is connected to the cathode of the power supply.
6. The isolated high-level-end NMOS output control circuit according to claim 1, further comprising an energy storage unit (4), wherein an input end of the energy storage unit (4) is connected to a source of the NMOS transistor, and an output end of the energy storage unit (4) is used as an output end of the control circuit to output a voltage signal.
7. The isolated high-level-end NMOS output control circuit according to claim 6, wherein the energy storage unit (4) comprises a seventh capacitor, an eighth capacitor, a second zener diode, a fourth resistor and a fifth resistor, the seventh capacitor and the eighth capacitor are connected in parallel and connected between the source of the NMOS transistor and the negative electrode of the power supply, the negative electrode of the second zener diode is connected to the source of the NMOS transistor, the positive electrode of the second zener diode is connected to the negative electrode of the power supply, one end of the fourth resistor is connected to the source of the NMOS transistor, the fourth resistor and the fifth resistor are connected in series, one end of the fifth resistor, which is far away from the fourth resistor, is connected to the negative electrode of the power supply and grounded, and the connection node of the fourth resistor and the fifth resistor is used for outputting the sampling voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223399047.9U CN218829599U (en) | 2022-12-16 | 2022-12-16 | NMOS output control circuit of isolated high-level end |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223399047.9U CN218829599U (en) | 2022-12-16 | 2022-12-16 | NMOS output control circuit of isolated high-level end |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218829599U true CN218829599U (en) | 2023-04-07 |
Family
ID=87258106
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223399047.9U Active CN218829599U (en) | 2022-12-16 | 2022-12-16 | NMOS output control circuit of isolated high-level end |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218829599U (en) |
-
2022
- 2022-12-16 CN CN202223399047.9U patent/CN218829599U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111654193B (en) | Drive control method and circuit thereof | |
| CN101237189B (en) | Positive activation converter | |
| CN104269997B (en) | A kind of adjustable transformer isolation complementary drive circuit in dead band | |
| CN108418458A (en) | A kind of half-bridge inverter based on quasi- Y source impedance networks | |
| CN109638797A (en) | A kind of Multi- Switch synchronization isolated drive circuit with overcurrent protection | |
| CN105896987A (en) | Flyback converter bootstrap type synchronous rectification drive circuit | |
| CN218829599U (en) | NMOS output control circuit of isolated high-level end | |
| CN109194126A (en) | A kind of power supply switch circuit | |
| CN111884492A (en) | Switch control circuit and power supply device | |
| CN101009486A (en) | Narrow pulse driver of insulation bar power tube | |
| US4598349A (en) | Electronic transformer composed of flyback converters | |
| CN205490127U (en) | High -voltage startup circuit | |
| CN106602883A (en) | Power MOS pipe switch power supply integration power supply circuit without auxiliary winding | |
| CN110912409A (en) | Forward and reverse excitation type switching power supply circuit | |
| CN115065247A (en) | Boost converter circuit and boost converter | |
| CN212323983U (en) | Switch control circuit and power supply device | |
| CN104092383A (en) | High-voltage input auxiliary power supply circuit and working method thereof | |
| CN210724554U (en) | Clamping type boosting power conversion circuit structure | |
| CN108566112B (en) | A kind of three-level current transformer driving circuit with negative pressure bootstrapping | |
| CN113364304A (en) | Synchronous rectification sampling control circuit, method and chip | |
| CN208353210U (en) | A kind of MOSFET isolated drive circuit | |
| CN112051884A (en) | Maximum power point tracking device for energy collection system | |
| CN104052253B (en) | Power on-off control circuit | |
| CN205596022U (en) | Synchronous Rectifier type switching power supply circuit | |
| CN204859049U (en) | Dc motor rotational speed control circuit and have electronic equipment of this circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |