CN218826845U - Intelligent high-voltage direct-current solid-state relay - Google Patents

Abstract

The utility model discloses an intelligent high-voltage direct-current solid-state relay, which comprises a shell encapsulation, an isolation control circuit, an isolation power circuit, a bus interface acquisition circuit and a power switch circuit, wherein the shell encapsulation consists of a shell and pouring sealant encapsulated in the shell; the isolation control circuit comprises a constant current source circuit, an optical coupling isolation circuit and a grid driver; the isolation power supply circuit comprises a first isolation power supply circuit and a second isolation power supply circuit; the bus interface acquisition circuit comprises a signal isolation circuit, an overload short circuit conditioning circuit, an overload short circuit acquisition circuit, a voltage and current acquisition circuit, an isolation operational amplifier circuit and a voltage conditioning circuit; the utility model discloses an intelligence high voltage direct current solid state relay's adoption overload short circuit acquisition circuit and overload short circuit conditioning circuit, when making relay operating current be greater than rated current, overflow the tripping operation curve according to the inverse time limit that sets up and carry out overcurrent protection, protection relay power consumption safety.

Description

Intelligent high-voltage direct-current solid-state relay

Technical Field

The utility model belongs to the technical field of electronic equipment, concretely relates to intelligence high voltage direct current solid state relay.

Background

The existing direct current solid-state relay is a novel non-contact switch device consisting of a microelectronic circuit, a discrete electronic device and a power electronic power device, and a control end and a load end are isolated through photoelectric coupling or magnetic isolation. The switch characteristics of power field effect transistor (MOSFET), IGB and silicon controlled rectifier are used to achieve the purpose of non-contact and non-spark connection and disconnection of circuit. Compared with the traditional electromagnetic coil relay with contacts, the solid-state relay has the advantages of long service life, high reliability, small control power, high switching speed, small electromagnetic interference, no noise, no spark and the like. The intelligent solid-state relay has the advantages of current and voltage real-time acquisition, overload protection, short-circuit protection, intelligent bus interface and the like. Although the existing intelligent direct-current solid-state relay has short-circuit protection and bus interface reporting functions, the working voltage range of the voltage and current acquisition chip is usually small and generally lower than 100V, so that the use of the relay in a high-voltage direct-current 270V system is limited. The existing intelligent direct-current solid-state relay with the high-voltage output function usually adopts an IGBT as a power switch device, the switch conduction voltage drop of the relay is large, the power consumption of the relay is large, and the relay does not have the functions of collecting current and voltage in real time and reporting the current and voltage through a bus interface.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a have 28VDC ~ 270VDC wide voltage range's switching power ability, the low internal resistance that switches on, real-time current and voltage gathers, overload and short-circuit protection, an intelligent high-voltage direct current solid state relay that bus interface and computer control equipment are connected.

The utility model provides a following technical scheme: an intelligent high-voltage direct-current solid-state relay comprises a shell package, an isolation control circuit, an isolation power circuit, a bus interface acquisition circuit and a power switch circuit, wherein the shell package comprises a shell and pouring sealant encapsulated in the shell; the isolation control circuit comprises a constant current source circuit, an optical coupling isolation circuit and a grid driver; the isolation power supply circuit comprises a first isolation power supply circuit and a second isolation power supply circuit; the bus interface acquisition circuit comprises a signal isolation circuit, an overload short circuit conditioning circuit, an overload short circuit acquisition circuit, a voltage and current acquisition circuit, an isolation operational amplifier circuit and a voltage conditioning circuit; the power switch circuit comprises a first grid resistor, a second grid resistor, a first high-voltage power field effect transistor, a second high-voltage power field effect transistor and a current sampling resistor;

the input end of the constant current source circuit is connected with the control end CTL + and the control end CTL-, and the output end of the constant current source circuit is connected with the input end of the optical coupling isolation circuit; the input end of the optical coupling isolation circuit is connected with the output end of the constant current source circuit, the isolation power supply input end of the signal isolation circuit is connected with the 5V output end of the first isolation power supply circuit and the power supply end C of the voltage and current acquisition circuit, the data signal end of the signal isolation circuit is connected with the data signal end D of the voltage and current acquisition circuit, and the output end of the optical coupling isolation circuit is connected with the input end A of the grid driver and the output end of the overload short-circuit conditioning circuit at the same time; the input end A of the grid driver is connected with the output end of the optical coupling isolation circuit and the output end of the overload short circuit conditioning circuit, the input end B of the grid driver is connected with the 12V output end of the first isolation power supply circuit, and the output end of the grid driver is connected with one end of the first grid resistor and one end of the second grid resistor; the second output end of the first isolation power supply circuit is 5V and is connected with a power supply end C of the voltage current acquisition circuit; the input end of the second isolation power supply circuit is connected with a power supply end VDD and a power supply ground end GND, and the output end 5VP of the second isolation power supply circuit is connected with the power supply input end of the isolation operational amplifier circuit; one end of a first input end current sampling resistor of the overload short-circuit acquisition circuit and an input end G of the voltage current acquisition circuit; the power supply input end of the isolation operational amplifier circuit is connected with the output end 5VP of the second isolation power supply circuit; and the second input end of the voltage conditioning circuit is connected with a high-voltage direct-current power ground end PG.

Preferably, one end of the first gate resistor is connected to the output end of the gate driver and one end of the second gate resistor; the grid electrode of the second high-voltage power field effect transistor is connected with the second end of the second grid resistor; the other end of the current sampling resistor is connected with the second input end of the overload short-circuit acquisition circuit, the input end H of the voltage current acquisition circuit, the source electrode of the second high-voltage power field-effect tube and the first input end of the voltage conditioning circuit.

Preferably, the input end of the first isolated power supply circuit is connected with a power supply VDD end and a power ground end GND, and the first output end of the first isolated power supply circuit is 12V and is connected with the input end B of the gate driver; the signal input end of the isolation operational amplifier circuit is connected with the signal output end of the voltage conditioning circuit, and the output end of the isolation operational amplifier circuit is connected with the signal input end F of the voltage acquisition circuit; the signal output end of the voltage conditioning circuit is connected with the signal input end of the isolation operational amplifier, and the first input end of the voltage conditioning circuit is connected with the second end of the current sampling resistor and the source electrode of the second high-voltage power field effect transistor.

Preferably, a first end of the signal isolation circuit is connected to a bus signal end SDA, a second end of the signal isolation circuit is connected to a bus signal end SCL, and a clock output end of the signal isolation circuit is connected to a clock input end E of the voltage and current acquisition circuit; the input end of the overload short-circuit conditioning circuit is connected with the output end of the overload short-circuit acquisition circuit, and the output end of the overload short-circuit conditioning circuit is connected with the output end of the optical coupling isolation circuit and the input end A of the grid driver; the second input end of the overload short-circuit acquisition circuit is connected with the other end of the current sampling resistor, the input end H of the voltage current acquisition circuit and the source electrode of the second high-voltage power field effect transistor, and the output end of the overload short-circuit acquisition circuit is connected with the input end of the overload short-circuit conditioning circuit; the power supply end C of the voltage and current acquisition circuit is connected with the output end 5V of the first isolation power supply circuit, the data signal end D of the voltage and current acquisition circuit is connected with the data signal end of the signal isolation circuit, the clock input end E is connected with the clock output end of the signal isolation circuit, the signal input end F of the voltage and current acquisition circuit is connected with the output end of the isolation operational amplifier circuit, the input end G of the voltage and current acquisition circuit is connected with one end of the current sampling resistor and the first input end of the overload short-circuit acquisition circuit, and the input end H of the voltage and current acquisition circuit is connected with the other end of the current sampling resistor, the second input end of the overload short-circuit acquisition circuit and the source electrode of the second high-voltage power field effect tube.

Preferably, the drain of the second high-voltage power field-effect transistor is a switch terminal S2, the source of the second high-voltage power field-effect transistor is connected to the second terminal of the current sampling resistor, the second input terminal of the overload short-circuit acquisition circuit and the input terminal H of the voltage current acquisition circuit, one terminal of the current sampling resistor is connected to the source of the first high-voltage power field-effect transistor, the first input terminal of the overload short-circuit acquisition circuit and the input terminal G of the voltage current acquisition circuit, and the other terminal of the first gate resistor is connected to the gate of the first high-voltage power field-effect transistor; one end of the second grid resistor is connected with the output end of the grid driver and one end of the first grid resistor, and the other end of the second grid resistor is connected with the grid of the second high-voltage power field effect transistor; the grid of the first high-voltage power field effect transistor is connected with the second end of the first grid resistor, the drain electrode of the first high-voltage power field effect transistor is a switch end S1, and the source electrode of the first high-voltage power field effect transistor is connected with one end of the current sampling resistor, the first input end of the overload short-circuit acquisition circuit and the input end G of the voltage current acquisition circuit.

Compared with the prior art, the beneficial effects of the utility model are as follows:

the utility model discloses an intelligent high-voltage direct-current solid-state relay adopts two-stage high-voltage high-power field effect transistor circuit, has 270V high pressure resistant, conduction current non-directivity, and the conduction internal resistance is little, has advantages such as preventing reverse function under the off-state;

the utility model discloses an intelligent high-voltage direct-current solid-state relay adopts overload short circuit acquisition circuit and overload short circuit conditioning circuit, when making relay operating current be greater than rated current, carries out overcurrent protection according to the inverse time limit overcurrent tripping curve that sets up, protects relay power consumption safety;

the utility model discloses an intelligent high-voltage direct-current solid-state relay, which enables the relay to have overload short-circuit protection latch function through an overload short-circuit conditioning circuit;

the utility model discloses an intelligent high-voltage direct-current solid-state relay adopts the isolation power supply and the isolation operational amplifier, so that the relay can normally work under the high-voltage direct-current 270V, and the high-voltage direct-current voltage information of a power end is collected;

the utility model discloses an intelligence high voltage direct current solid state relay need not software programming, gathers power terminal voltage current information in real time through hardware circuit and is connected with computer control equipment through keeping apart bus interface output, has advantages such as sampling precision height, collection scope width.

Drawings

Fig. 1 is a circuit block diagram of an intelligent high-voltage dc solid-state relay of the present invention;

fig. 2 is the circuit schematic diagram of the utility model discloses an intelligence high voltage direct current solid state relay.

In the figure: the device comprises a shell package 1, an isolation control circuit 2, an isolation power supply circuit 3, a bus interface acquisition circuit 4, a power switch circuit 5, a constant current source circuit 21, an optical coupling isolation circuit 22, a grid driver 23, a first isolation power supply circuit 31, a second isolation power supply circuit 32, a signal isolation circuit 41, an overload short-circuit conditioning circuit 42, an overload short-circuit acquisition circuit 43, a voltage and current acquisition circuit 44, an isolation operational amplifier circuit 45, a voltage conditioning circuit 46, a first grid resistor 51, a second grid resistor 52, a first high-voltage power field effect transistor 53, a second high-voltage power field effect transistor 54 and a current sampling resistor 55.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts all belong to the protection scope of the present invention.

Referring to fig. 1-2, the present invention provides a technical solution: an intelligent high voltage direct current solid state relay comprising: the shell package 1, install the isolation control circuit 2 in the shell package, keep apart power supply circuit 3, bus interface acquisition circuit 4, power switch circuit 5, control input CTL +, CTL-, power supply input VDD, GND, bus interface end SDA, SCL and solid state relay' S switch both ends S1, S2 and high-voltage direct current power electricity ground terminal PG. The shell encapsulation consists of a shell and pouring sealant filled in the shell; the isolation control circuit 2 comprises a constant current source circuit 21, an optical coupling isolation circuit 22 and a grid driver 23; the isolated power supply circuit 3 includes a first isolated power supply circuit 31, a second isolated power supply circuit 32; the bus interface acquisition circuit 4 comprises a signal isolation circuit 41, an overload short-circuit conditioning circuit 42, an overload short-circuit acquisition circuit 43, a voltage and current acquisition circuit 44, an isolation operational amplifier circuit 45 and a voltage conditioning circuit 46; the power switch circuit 5 comprises a first grid resistor 51, a second grid resistor 52, a first high-voltage power field-effect tube 53, a second high-voltage power field-effect tube 54 and a current sampling resistor 55;

the input end of the constant current source circuit 21 is connected with the control end CTL + and the control end CTL-, and the output end is connected with the input end of the optical coupling isolation circuit 22; the input end of the optical coupling isolation circuit 22 is connected with the output end of the constant current source circuit 21, and the output end is connected with the input end A of the grid driver 23 and the output end of the overload short-circuit conditioning circuit 42; the input end a of the gate driver 23 is connected to the output end of the optical coupling isolation circuit 22 and the output end of the overload short-circuit conditioning circuit 42, the input end B is connected to the 12V output end of the first isolation power circuit 31, and the output end is connected to one end of the first gate resistor 51 and one end of the second gate resistor 52; the input end of the first isolation power supply circuit 31 is connected with a power supply VDD end and a power supply ground GND end, the first output end 12V is connected with the input end B of the gate driver, and the second output end 5V is connected with the power supply end C of the voltage current acquisition circuit 44; the input end of the second isolation power supply circuit 32 is connected with a power supply VDD end and a power supply ground GND end, and the output end 5VP is connected with the power supply input end of the isolation operational amplifier circuit; the first end of the signal isolation circuit 41 is connected to the bus signal end SDA, the second end is connected to the bus signal end SCL, the isolated power supply input end is connected to the 5V output end of the first isolated power supply circuit 31 and the power supply end C of the voltage and current acquisition circuit 44, the data signal end is connected to the data signal end D of the voltage and current acquisition circuit 44, and the clock output end is connected to the clock input end E of the voltage and current acquisition circuit 44; the input end of the overload short-circuit conditioning circuit 42 is connected with the output end of the overload short-circuit acquisition circuit 43, and the output end is connected with the output end of the optical coupling isolation circuit 22 and the input end A of the grid driver 23; one end of a first input end current sampling resistor 55 of the overload short-circuit acquisition circuit 43 and an input end G of the voltage current acquisition circuit 44, a second input end is connected with the other end of the current sampling resistor 55, an input end H of the voltage current acquisition circuit 44 and a source electrode of the second high-voltage power field-effect tube 54, and an output end is connected with an input end of the overload short-circuit conditioning circuit 42; a power supply end C of the voltage and current acquisition circuit 44 is connected with the output end 5V of the first isolation power supply circuit 31, a data signal end D is connected with a data signal end of the signal isolation circuit 41, a clock input end E is connected with a clock output end of the signal isolation circuit 41, a signal input end F is connected with an output end of the isolation operational amplifier circuit 45, an input end G is connected with one end of the current sampling resistor 55 and a first input end of the overload short-circuit acquisition circuit 43, and an input end H is connected with the other end of the current sampling resistor 55, a second input end of the overload short-circuit acquisition circuit 43 and a source electrode of the second high-voltage power field-effect tube 54; the power supply input end of the isolation operational amplifier circuit 45 is connected with the output end 5VP of the second isolation power supply circuit, the signal input end is connected with the signal output end of the voltage conditioning circuit 46, and the output end is connected with the signal input end F of the voltage acquisition circuit 44; the signal output end of the voltage conditioning circuit 46 is connected with the signal input end of the isolation operational amplifier 45, the first input end is connected with the second end of the current sampling resistor and the source electrode of the second high-voltage power field-effect tube 54, and the second input end is connected with the high-voltage direct-current power electric ground end PG; one end of the first gate resistor 51 is connected to the output end of the gate driver 23 and one end of the second gate resistor 52, and the other end is connected to the gate of the first high-voltage power fet 53; one end of the second gate resistor 52 is connected to the output end of the gate driver 23 and one end of the first gate resistor 51, and the other end is connected to the gate of the second high voltage power fet 54; the gate of the first high-voltage power fet 53 is connected to the second end of the first gate resistor, the drain is the switch end S1, the source is connected to one end of the current sampling resistor 55, the first input end of the overload short-circuit acquisition circuit 43, and the input end G of the voltage-current acquisition circuit 44; the gate of the second high-voltage power fet 54 is connected to the second end of the second gate resistor, the drain is the switch end S2, and the source is connected to the second end of the current sampling resistor 55, the second input end of the overload short-circuit acquisition circuit 43, and the input end H of the voltage-current acquisition circuit 44; one end of the current sampling resistor 55 is connected to the source of the first high voltage power fet 53, the first input terminal of the overload short-circuit acquisition circuit 43, and the input terminal G of the voltage-current acquisition circuit 44, and the other end is connected to the second input terminal of the overload short-circuit acquisition circuit 43, the input terminal H of the voltage-current acquisition circuit 44, the source of the second high voltage power fet 54, and the first input terminal of the voltage conditioning circuit.

The constant current source circuit 21 is composed of an RC filter circuit composed of a resistor and a capacitor and a constant current diode, and is used for limiting the working current of the solid-state relay, ensuring the control signal to be continuously effective within a wide input control voltage range of 3V to 32V, and reducing the power consumption of the control signal.

The optical coupling isolation circuit 22 is composed of an optical coupling device, a resistor and a capacitor, and is configured to detect a control voltage input signal, output a logic amount of a high level and a low level to the gate driver 23 according to whether the control voltage input signal exists or not, and if the control voltage input signal exists, the optical coupling isolation circuit 22 outputs the high level, otherwise, the optical coupling isolation circuit outputs the low level.

The gate driver 23 drives the two high-voltage power field effect transistors in the power switch circuit 5 to be turned on and off according to the level condition of the control signal of the optical coupling isolation circuit 22, and is turned on at a high level and turned off at a low level.

The isolation power supply circuit 3 provides a +12V isolation control power supply for the isolation control circuit 2 and provides a +5V isolation power supply for the bus interface acquisition circuit 4, and the isolation power supply ground is the end where one end of the current sampling resistor 55 is connected with the source electrode of the first high-voltage power field effect transistor; the isolation power supply circuit 3 provides a +5VP isolation power supply for the bus interface acquisition circuit 4, and the isolation power supply ground is a high-voltage direct-current power ground end PG.

The voltage conditioning circuit 46 is composed of a resistor, a capacitor and an inductor, converts the high-voltage 270V power voltage into an input voltage range of the isolation operational amplifier circuit 45, and simultaneously performs filtering and rectifying processing to obtain a stable voltage signal, and the stable voltage signal is output to the voltage acquisition end F of the voltage and current acquisition circuit 44 after being followed by the isolation operational amplifier circuit 45.

The voltage and current acquisition circuit 44 acquires differential voltage signals at two ends of the current sampling resistor, automatically converts the differential voltage signals into current signals flowing through the current sampling resistor according to the resistance value of the current sampling resistor, simultaneously acquires voltage signals output by the isolation operational amplifier circuit 45, converts the voltage signals into digital quantity and outputs the digital quantity through a bus interface, and particularly, the conversion and transmission process is automatically completed by hardware, and external computer control equipment reads related voltage and current signals according to a set communication protocol.

The signal isolation circuit 41 is composed of a digital signal isolation interface chip and a resistance capacitor, and is used for realizing the isolation of power electricity and control electricity of the solid-state relay, and connecting an internal signal to an external computer control device after the electrical isolation.

The overload short circuit acquisition circuit 43 acquires overload and short circuit overcurrent signals on the current sampling resistor 55, processes the current state flowing through the current sampling resistor and outputs the processed current state to the overload short circuit conditioning circuit 42, when overload current is generated, the overload short circuit conditioning circuit 42 accumulates overload energy, the larger the overload current is, the faster the energy accumulation is, the faster output turn-off signal is generated, the smaller the overload current is, the longer the energy accumulation process time is, and the time for outputting the turn-off signal is correspondingly lengthened. When the circuit is short-circuited and the current flowing through the current sampling resistor is set to be 8-10 times of the rated current, the overload short-circuit conditioning circuit 42 immediately generates a short-circuit turn-off signal, controls the gate driver 23 to immediately turn off the power switch circuit 5, and automatically latches the turn-off signal until the power is cut off and restarted. Particularly, the overload short circuit conditioning circuit comprises an operational amplifier, a resistor, a capacitor, a voltage regulator tube, a triode and the like, and can adjust the inverse time limit turning curve according to the parameters of an application adjusting device.

The first grid resistor 51 and the second grid resistor 52 are respectively connected in series between the grids of the first high-voltage power field effect transistor 53 and the second high-voltage power field effect transistor 54 and the output end of the grid driver 23, and are used for controlling the rising and falling time of the power transistor switch and improving the electromagnetic compatibility and stability of the solid-state relay.

Adopt high-voltage power field effect transistor as an intelligent high-voltage direct current solid state relay's switch, the drain electrode of two power tubes is as the both ends point of solid state relay's switch respectively, and the source electrode links to each other through a current sampling resistance, makes the utility model discloses an intelligent high-voltage direct current solid state relay has bidirectional conductivity, and switch on resistance is less than 40m omega under the rated 5A condition, has reduced switching power loss, reduces the heat consumption of relay during operation.

This embodiment adopts two high-voltage power field effect transistors as the switch tube, makes the utility model discloses an intelligence solid state relay has the function of preventing reversing, can adopt the parallelly connected mode of a plurality of power tubes to improve an intelligence high voltage direct current solid state relay's conduction current. Particularly, the method can also be applied to a unidirectional power input scene in a mode of adopting a single power field effect transistor, and the size and the cost of the solid-state relay can be effectively reduced.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (5)

1. An intelligent high-voltage direct-current solid-state relay is characterized by comprising a shell package (1), an isolation control circuit (2), an isolation power circuit (3), a bus interface acquisition circuit (4) and a power switch circuit (5), wherein the shell package (1) consists of a shell and pouring sealant encapsulated in the shell; the isolation control circuit (2) comprises a constant current source circuit (21), an optical coupling isolation circuit (22) and a grid driver (23); the isolation power supply circuit (3) comprises a first isolation power supply circuit (31) and a second isolation power supply circuit (32); the bus interface acquisition circuit (4) comprises a signal isolation circuit (41), an overload short circuit conditioning circuit (42), an overload short circuit acquisition circuit (43), a voltage and current acquisition circuit (44), an isolation operational amplifier circuit (45) and a voltage conditioning circuit (46); the power switch circuit (5) comprises a first grid resistor (51), a second grid resistor (52), a first high-voltage power field effect transistor (53), a second high-voltage power field effect transistor (54) and a current sampling resistor (55);

the input end of the constant current source circuit (21) is connected with the control end CTL + and the control end CTL-, and the output end of the constant current source circuit (21) is connected with the input end of the optical coupling isolation circuit (22); the input end of the optical coupling isolation circuit (22) is connected with the output end of the constant current source circuit (21), the isolation power supply input end of the signal isolation circuit (41) is connected with the 5V output end of the first isolation power supply circuit (31) and the power supply end C of the voltage and current acquisition circuit (44), the data signal end of the signal isolation circuit (41) is connected with the data signal end D of the voltage and current acquisition circuit (44), and the output end of the optical coupling isolation circuit (22) is connected with the input end A of the gate driver (23) and the output end of the overload short-circuit conditioning circuit (42); the input end A of the gate driver (23) is connected with the output end of the optical coupling isolation circuit (22) and the output end of the overload short-circuit conditioning circuit (42), the input end B of the gate driver (23) is connected with the 12V output end of the first isolation power supply circuit (31), and the output end of the gate driver (23) is connected with one end of the first gate resistor (51) and one end of the second gate resistor (52); the second output end of the first isolation power supply circuit (31) is 5V and is connected with a power supply end C of the voltage current acquisition circuit (44); the input end of the second isolation power supply circuit (32) is connected with a power supply end VDD and a power supply ground end GND, and the output end 5VP of the second isolation power supply circuit (32) is connected with the power supply input end of the isolation operational amplifier circuit (45); one end of a first input end current sampling resistor (55) of the overload short-circuit acquisition circuit (43) and an input end G of a voltage current acquisition circuit (44); the power supply input end of the isolation operational amplifier circuit (45) is connected with the output end 5VP of the second isolation power supply circuit (32); and the second input end of the voltage conditioning circuit (46) is connected with a high-voltage direct-current power electric ground end PG.

2. An intelligent HVDC solid-state relay according to claim 1, wherein one end of the first gate resistor (51) is connected to the output terminal of the gate driver (23) and one end of the second gate resistor (52); the grid electrode of the second high-voltage power field effect transistor (54) is connected with the second end of the second grid resistor (52); the other end of the current sampling resistor (55) is connected with the second input end of the overload short-circuit acquisition circuit (43), the input end H of the voltage current acquisition circuit (44), the source electrode of the second high-voltage power field-effect tube (54) and the first input end of the voltage conditioning circuit (46).

3. An intelligent high-voltage direct-current solid-state relay according to claim 1, wherein the input end of the first isolated power circuit (31) is connected to a power supply VDD terminal and a power ground terminal GND, the first output end of the first isolated power circuit (31) is 12V and is connected to the input end B of the gate driver (23); the signal input end of the isolation operational amplifier circuit (45) is connected with the signal output end of the voltage conditioning circuit (46), and the output end of the isolation operational amplifier circuit (45) is connected with the signal input end F of the voltage acquisition circuit; the signal output end of the voltage conditioning circuit (46) is connected with the signal input end of the isolation operational amplifier, and the first input end of the voltage conditioning circuit (46) is connected with the second end of the current sampling resistor (55) and the source electrode of the second high-voltage power field-effect tube (54).

4. An intelligent high-voltage direct-current solid-state relay according to claim 1, wherein a first terminal of the signal isolation circuit (41) is connected to a bus signal terminal SDA, a second terminal of the signal isolation circuit (41) is connected to a bus signal terminal SCL, and a clock output terminal of the signal isolation circuit (41) is connected to a clock input terminal E of the voltage and current acquisition circuit (44); the input end of the overload short-circuit conditioning circuit (42) is connected with the output end of the overload short-circuit acquisition circuit (43), and the output end of the overload short-circuit conditioning circuit (42) is connected with the output end of the optical coupling isolation circuit (22) and the input end A of the grid driver (23); a second input end of the overload short-circuit acquisition circuit (43) is connected with the other end of the current sampling resistor (55), an input end H of the voltage current acquisition circuit (44) and a source electrode of the second high-voltage power field-effect tube (54), and an output end of the overload short-circuit acquisition circuit (43) is connected with an input end of the overload short-circuit conditioning circuit (42); the power supply end C of the voltage and current acquisition circuit (44) is connected with the output end 5V of the first isolation power supply circuit (31), the data signal end D of the voltage and current acquisition circuit (44) is connected with the data signal end of the signal isolation circuit (41), the clock input end E is connected with the clock output end of the signal isolation circuit (41), the signal input end F of the voltage and current acquisition circuit (44) is connected with the output end of the isolation operational amplifier circuit (45), the input end G of the voltage and current acquisition circuit (44) is connected with one end of the current sampling resistor (55) and the first input end of the overload short-circuit acquisition circuit (43), and the input end H of the voltage and current acquisition circuit (44) is connected with the other end of the current sampling resistor (55), the second input end of the overload short-circuit acquisition circuit (43) and the source electrode of the second high-voltage power field-effect transistor (54).

5. An intelligent high-voltage direct-current solid-state relay according to claim 1, wherein the drain of the second high-voltage power fet (54) is a switch terminal S2, the source of the second high-voltage power fet (54) is connected to the second terminal of the current sampling resistor (55), the second input terminal of the overload short-circuit acquisition circuit (43) and the input terminal H of the voltage current acquisition circuit (44), one terminal of the current sampling resistor (55) is connected to the source of the first high-voltage power fet (53), the first input terminal of the overload short-circuit acquisition circuit (43) and the input terminal G of the voltage current acquisition circuit (44), and the other terminal of the first gate resistor (51) is connected to the gate of the first high-voltage power fet (53); one end of the second grid resistor (52) is connected with the output end of the grid driver (23) and one end of the first grid resistor (51), and the other end of the second grid resistor (52) is connected with the grid of the second high-voltage power field effect transistor (54); the grid electrode of the first high-voltage power field effect transistor (53) is connected with the second end of the first grid resistor (51), and the drain electrode of the first high-voltage power field effect transistor (53) is a switch end S1.

Images