CN218825458U

CN218825458U - Circuit for preventing switch from shaking or resetting normally-supplied power supply controlled by switch

Info

Publication number: CN218825458U
Application number: CN202222733828.0U
Authority: CN
Inventors: 华然; 伍景宇
Original assignee: Shenzhen Shouhang Electronics Co ltd
Current assignee: Shenzhen Shouhang Electronics Co ltd
Priority date: 2022-10-17
Filing date: 2022-10-17
Publication date: 2023-04-07
Anticipated expiration: 2032-10-17

Abstract

The utility model relates to a supply circuit technical field provides a receive on-off control's circuit that normal power supply source prevented switch shake or reset, include: the voltage control circuit comprises a voltage input end, a power supply IC, a first voltage-dividing resistor, a second voltage-dividing resistor, a filter capacitor, a diode, an inductor, an output capacitor group and a voltage output end; the voltage input end is connected with a VIN pin of a power supply IC; the EN pin of the power supply IC is connected with the IO port of the MCU; one end of the filter capacitor is connected with an EN pin of the power supply IC, the other end of the filter capacitor is grounded, one end of the second divider resistor is connected with the EN pin of the power supply IC, and the other end of the second divider resistor is grounded; the utility model discloses effectively solved the normal power supply power that receives IO mouth control, produced the switch shake or reset when IO resets, aroused that output power is unstable or turn-off the problem that the system that leads to restarts or resets.

Description

Circuit for preventing switch from shaking or resetting normally-supplied power supply controlled by switch

Technical Field

The utility model relates to a supply circuit technical field, more specifically say, relate to a receive on-off control's circuit that often supplies power source to prevent switch shake or reset.

Background

At present, with the increase of application requirements, the system design is more and more complex, two or more CPUs are often present in one system, and such a phenomenon occurs in practical applications: the system comprises two controllers, one is MCU, the other is CPU, MCU controls the power supply of CPU through IO port, MCU acquires the state of CPU through internal interface to confirm whether CPU is normal, when CPU work is abnormal and can not be recovered, MCU is needed to control the CPU power supply to carry out power-off reset through IO port, and MCU reset or operation can not influence the normal work of CPU in normal operation, when MCU abnormal reset is found in application, because IO port resets along with MCU reset, lead to CPU power supply to produce and turn-off or shake, influence the normal operation of CPU.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the present invention is to provide a circuit for preventing the switch from shaking or resetting under the control of the switch for the normally-supplied power supply, aiming at the above-mentioned defects of the prior art.

The utility model provides a technical scheme that its technical problem adopted is: a circuit for preventing switch jitter or reset of a normally-supplied power supply controlled by a switch is provided, which comprises: the voltage control circuit comprises a voltage input end, a power supply IC, a first voltage-dividing resistor, a second voltage-dividing resistor, a filter capacitor, a diode, an inductor, an output capacitor group and a voltage output end; the voltage input end is connected with a VIN pin of a power supply IC; the EN pin of the power supply IC is connected with the IO port of the MCU; one end of the filter capacitor is connected with an EN pin of the power supply IC, the other end of the filter capacitor is grounded, one end of the second divider resistor is connected with the EN pin of the power supply IC, and the other end of the second divider resistor is grounded; the SW pin of the power supply IC is connected with the voltage output end through an inductor; the positive electrode of the output capacitor bank is connected with the voltage output end, and the other end of the output capacitor bank is grounded; the positive electrode of the output capacitor bank is also connected with the positive electrode of a diode, the negative electrode of the diode is connected with one end of a first divider resistor, and the other end of the first divider resistor is connected with an EN pin of a power supply IC; and the GND pin of the power supply IC is grounded.

Preferably, the power supply further comprises a first feedback resistor and a second feedback resistor, one end of the first feedback resistor is connected with the positive electrode of the output capacitor bank, the other end of the first feedback resistor is connected with the FB pin of the power supply IC and one end of the second feedback resistor, and the other end of the second feedback resistor is grounded.

Preferably, the output capacitor group includes a first output capacitor, a second output capacitor and a third output capacitor, anodes of the first output capacitor, the second output capacitor and the third output capacitor are connected to the voltage output terminal, and the other ends of the first output capacitor, the second output capacitor and the third output capacitor are grounded.

Preferably, the voltage input end is connected with the positive electrode of the input capacitor bank, and the other end of the input capacitor bank is grounded.

Preferably, the input capacitor bank includes a first input capacitor, a second input capacitor and a third input capacitor, anodes of the first input capacitor, the second input capacitor and the third input capacitor are connected to the voltage input terminal, and the other ends of the first input capacitor, the second input capacitor and the third input capacitor are grounded.

The beneficial effects of the utility model reside in that: when the voltage input end is powered on, an IO port pin MCU _ IO _ EN of the MCU is initialized, the IO port pin MCU _ IO _ EN of the MCU inputs a low level to an EN pin of the power supply IC through a filter capacitor and a second divider resistor, the power supply IC is not started, and the voltage output by the voltage output end is 0V; when the MCU normally works, the IO port pin MCU _ IO _ EN of the MCU inputs a high level to the EN pin of the power supply IC through the filter capacitor and the second divider resistor, the power supply IC is started, and the power supply IC enables the voltage output end to output stable voltage through the inductor, the output capacitor group, the first feedback resistor and the second feedback resistor; when the MCU is reset or restarted, an IO port pin MCU _ IO _ EN of the MCU is reset or restarted therewith, which may cause a power supply IC to be in a closed state, at the moment, the output capacitor bank discharges, the voltage output end is maintained to output stable voltage, and meanwhile, the diode is conducted, so that the discharged voltage of the capacitor bank enables the power supply IC to be in an open state through the diode and the first divider resistor, thereby enabling the voltage output end to output stable voltage, and solving the problem that the normal power supply controlled by the IO port generates switch jitter or reset when the IO is reset, which causes the system restart or reset caused by unstable or cut-off of the output power supply.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the present invention will be further described below with reference to the accompanying drawings and embodiments, wherein the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained without inventive work according to the drawings:

fig. 1 is a circuit diagram of a circuit of a switch-controlled constant power supply for preventing the switch from shaking or resetting according to a preferred embodiment of the present invention.

Detailed Description

The terms "first," "second," "third," and "fourth," etc. in the description and claims and in the drawings of the present invention are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

"plurality" means two or more. "and/or" describes the association relationship of the associated object, indicating that there may be three relationships, for example, a and/or B, which may indicate: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship;

in order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, a clear and complete description will be given below with reference to the technical solutions of the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

The utility model discloses a circuit that normal power supply source that receives switch control prevents the switch shake or resets of preferred embodiment, as shown in figure 1, include: the voltage-controlled power supply comprises a voltage input end, a power supply IC U1, a first voltage-dividing resistor R4, a second voltage-dividing resistor R5, a filter capacitor C7, a diode D1, an inductor L8, an output capacitor group and a voltage output end; the voltage input end is connected with a VIN pin of a power supply IC U1; the EN pin of the power supply IC U1 is connected with the IO port of the MCU; one end of the filter capacitor C7 is connected with an EN pin of the power supply IC U1, the other end of the filter capacitor C is grounded, one end of the second divider resistor R5 is connected with the EN pin of the power supply IC U1, and the other end of the second divider resistor R5 is grounded; the SW pin of the power supply IC U1 is connected with the voltage output end through an inductor L8; the positive electrode of the output capacitor bank is connected with the voltage output end, and the other end of the output capacitor bank is grounded; the positive electrode of the output capacitor bank is also connected with the positive stage of a diode D1, the negative stage of the diode D1 is connected with one end of a first divider resistor R4, and the other end of the first divider resistor R4 is connected with an EN pin of a power supply IC U1; and the GND pin of the power supply IC U1 is grounded.

When the voltage input end is powered on, an IO port pin MCU _ IO _ EN of the MCU is initialized, the IO port pin MCU _ IO _ EN of the MCU inputs a low level to an EN pin of the power supply IC through a filter capacitor and a second divider resistor, the power supply IC is not started, and the voltage output by the voltage output end is 0V; when the MCU normally works, the IO port pin MCU _ IO _ EN of the MCU inputs a high level to the EN pin of the power supply IC through the filter capacitor and the second divider resistor, the power supply IC is started, and the power supply IC enables the voltage output end to output stable voltage through the inductor, the output capacitor group, the first feedback resistor and the second feedback resistor; when the MCU is reset or restarted, an IO port pin MCU _ IO _ EN of the MCU is reset or restarted therewith, which may cause a power supply IC to be in a closed state, at the moment, the output capacitor bank discharges, the voltage output end is maintained to output stable voltage, and meanwhile, the diode is conducted, so that the discharged voltage of the capacitor bank enables the power supply IC to be in an open state through the diode and the first divider resistor, thereby enabling the voltage output end to output stable voltage, and solving the problem that the normal power supply controlled by the IO port generates switch jitter or reset when the IO is reset, which causes the system restart or reset caused by unstable or cut-off of the output power supply.

The circuit for preventing the switch from shaking or resetting for the switch-controlled normal power supply further comprises a first feedback resistor R2 and a second feedback resistor R3, wherein one end of the first feedback resistor R2 is connected with the anode of the output capacitor bank, the other end of the first feedback resistor R2 is connected with the FB pin of the power supply IC U1 and one end of the second feedback resistor R3, and the other end of the second feedback resistor R3 is grounded; the first feedback resistor and the second feedback resistor are arranged on the circuit, so that the connection condition of the circuit can be timely and quickly checked, and the condition of short circuit or open circuit of the circuit is avoided.

Specifically, the output capacitor bank comprises a first output capacitor C1, a second output capacitor C2 and a third output capacitor C3, the anodes of the first output capacitor C1, the second output capacitor C2 and the third output capacitor C3 are connected with the voltage output end, the other ends of the first output capacitor C1, the second output capacitor C2 and the third output capacitor C3 are grounded, the connection is simple, and the voltage output by the voltage output end is more stable through the plurality of output capacitor banks.

Specifically, the voltage input end is connected to a positive electrode of the input capacitor bank, and the other end of the input capacitor bank is grounded.

Specifically, the input capacitor bank includes a first input capacitor C4, a second input capacitor C5, and a third input capacitor C6, anodes of the first input capacitor C4, the second input capacitor C5, and the third input capacitor C6 are connected to a voltage input terminal, and the other ends of the first input capacitor C4, the second input capacitor C5, and the third input capacitor C6 are grounded.

The working principle is as follows: when the voltage input end is powered on, an IO port pin MCU _ IO _ EN of the MCU is initialized, the IO port pin MCU _ IO _ EN of the MCU inputs a low level to an EN pin of the power supply IC through a filter capacitor and a second divider resistor, the power supply IC is not started, and the voltage output by the voltage output end is 0V; when the MCU normally works, the IO port pin MCU _ IO _ EN of the MCU inputs a high level to the EN pin of the power supply IC through the filter capacitor and the second divider resistor, the power supply IC is started, and the power supply IC enables the voltage output end to output stable voltage through the inductor, the output capacitor group, the first feedback resistor and the second feedback resistor; when the MCU is reset or restarted, the pin MCU _ IO _ EN of the IO port of the MCU is reset or restarted therewith, which may cause the power supply IC to be in a closed state, at this moment, the output capacitor bank discharges, the voltage output end is maintained to output stable voltage, and meanwhile, the diode is conducted, so that the discharged voltage of the capacitor bank enables the power supply IC to be in an open state through the diode and the first divider resistor, thereby enabling the voltage output end to output stable voltage, and avoiding the situation that the IO port resets along with the MCU resetting, which causes the CPU power supply to be turned off or shaken, and the normal operation of the CPU is influenced.

It will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are considered to be within the scope of the invention as defined by the following claims.

Claims

1. A circuit for preventing jitter or reset of a switch in a normally-supplied power supply controlled by the switch, comprising: the voltage control circuit comprises a voltage input end, a power supply IC, a first voltage-dividing resistor, a second voltage-dividing resistor, a filter capacitor, a diode, an inductor, an output capacitor group and a voltage output end; the voltage input end is connected with a VIN pin of a power supply IC; the EN pin of the power supply IC is connected with the IO port of the MCU; one end of the filter capacitor is connected with an EN pin of the power supply IC, the other end of the filter capacitor is grounded, one end of the second divider resistor is connected with the EN pin of the power supply IC, and the other end of the second divider resistor is grounded; the SW pin of the power supply IC is connected with the voltage output end through an inductor; the positive electrode of the output capacitor bank is connected with the voltage output end, and the other end of the output capacitor bank is grounded; the positive electrode of the output capacitor bank is also connected with the positive electrode of a diode, the negative electrode of the diode is connected with one end of a first divider resistor, and the other end of the first divider resistor is connected with an EN pin of a power supply IC; and the GND pin of the power supply IC is grounded.

2. The circuit for preventing the switch from shaking or resetting for the switch-controlled power supply according to claim 1, further comprising a first feedback resistor and a second feedback resistor, wherein one end of the first feedback resistor is connected to the positive electrode of the output capacitor bank, the other end of the first feedback resistor is connected to the FB pin of the power supply IC and one end of the second feedback resistor, and the other end of the second feedback resistor is grounded.

3. A circuit for preventing a switch from jittering or resetting according to claim 2, wherein the output capacitor set comprises a first output capacitor, a second output capacitor and a third output capacitor, the positive electrodes of the first output capacitor, the second output capacitor and the third output capacitor are connected with the voltage output terminal, and the other ends of the first output capacitor, the second output capacitor and the third output capacitor are grounded.

4. A circuit for preventing jitter or reset of a switch in a switch-controlled power supply according to any one of claims 1 to 3, wherein the voltage input terminal is connected to the positive pole of the input capacitor bank, and the other terminal of the input capacitor bank is grounded.

5. The circuit for preventing the switch from shaking or resetting for the switch-controlled constant power supply according to claim 4, wherein the input capacitor bank comprises a first input capacitor, a second input capacitor and a third input capacitor, the positive electrodes of the first input capacitor, the second input capacitor and the third input capacitor are connected with the voltage input end, and the other ends of the first input capacitor, the second input capacitor and the third input capacitor are grounded.