CN218771385U - Super capacitor charging circuit - Google Patents
Super capacitor charging circuit Download PDFInfo
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- CN218771385U CN218771385U CN202223369802.9U CN202223369802U CN218771385U CN 218771385 U CN218771385 U CN 218771385U CN 202223369802 U CN202223369802 U CN 202223369802U CN 218771385 U CN218771385 U CN 218771385U
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Abstract
The utility model discloses a super capacitor charging circuit, electric capacity C8 and electric capacity C9 are established ties in the circuit, and diode D6's negative pole, super capacitor voltage, resistance R43 are connected respectively to electric capacity C8's one end, and the other end of electric capacity C8, one end of electric capacity C9 are connected resistance R43's the other end, resistance R44 respectively, and the other end of resistance R4, the other end of electric capacity C9 ground connection respectively; the anode of the diode D6 is connected to the resistor R45, the capacitor C43 and the inductor L4, the other end of the resistor R45 is connected to the FB pins of the resistors R46 and U4, the other end of the resistor R46 is connected to the ground and the resistor R40, the other end of the resistor R40 is connected to the capacitor C41, and the other end of the capacitor C41 is connected to the power input and the EN pin and the VIN pin of the U4. The utility model discloses can accurate control charge cutoff voltage and maximum charging current.
Description
Technical Field
The utility model belongs to the technical field of the circuit, especially, relate to a super capacitor charging circuit.
Background
The super capacitor is an electrochemical element for storing energy through a polarized electrolyte, is a power source which is arranged between a traditional capacitor and a battery and has special performance, and mainly stores electric energy by electric double layers and redox capacitance charges, but does not generate chemical reaction in the energy storage process, and the energy storage process is reversible, so that the super capacitor can be repeatedly charged and discharged.
Intervals exist between peak power pulses in the charging process of the super capacitor, and if the pulse intervals are too far away, the charging efficiency of the super capacitor is not high. The existing super capacitor charging circuit generally uses a linear charging circuit, so that the super capacitor charging efficiency is not high enough, and the charging cut-off voltage and the maximum charging current of the circuit are inconvenient to adjust.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides a super capacitor charging circuit.
The utility model discloses a super capacitor charging circuit, electric capacity C8 and electric capacity C9 are established ties in the circuit, and diode D6's negative pole, super capacitor voltage, resistance R43 are connected respectively to electric capacity C8's one end, and the other end of electric capacity C8, one end of electric capacity C9 are connected resistance R43's the other end, resistance R44 respectively, and the other end of resistance R4, the other end of electric capacity C9 ground connection respectively; the anode of the diode D6 is respectively connected with a resistor R45, a capacitor C43 and an inductor L4, the other end of the resistor R45 is respectively connected with a resistor R46 and an FB pin of the power chip U4, the other end of the resistor R46 is respectively connected with a ground and a resistor R40, the other end of the resistor R40 is connected with a capacitor C41, and the other end of the capacitor C41 is respectively connected with a power input, an EN pin and a VIN pin of the chip U4; the other end of the capacitor C43 is grounded and a GND pin of the chip U4 respectively; the other end of the inductor L4 is connected with a SW pin of the chip U4 and a capacitor C42 respectively, and the other end of the capacitor C42 is connected with a BS pin of the chip U4;
the capacitor C41, the capacitor C42, the capacitor C43, the inductor L4 and the chip U4 form a DC-DC voltage reduction charging circuit, the resistor R43 and the resistor R44 form a balance circuit, the resistor R40, the resistor R45 and the resistor R46 form a voltage and current acquisition feedback circuit, and the diode D6 is an anti-reverse-charging circuit.
Further, the model of the chip U4 is MT2492.
The utility model has the advantages as follows:
the utility model discloses the circuit uses DC-DC step-down charging circuit as super capacitor charging circuit's main part, and the circuit that inductance and electric capacity constitute when charging makes the interval between each pulse of peak power nearer apart, can improve charge efficiency, compares linear charging circuit and can practice thrift charge time and electric energy to accurate control charges cut-off voltage and maximum charging current.
Drawings
Fig. 1 is a schematic circuit diagram of the present invention.
Detailed Description
The following description of the present invention is provided with reference to the accompanying drawings, which are not intended to limit the present invention in any way, and any alterations or replacements made based on the teachings of the present invention are all within the protection scope of the present invention.
The utility model discloses a super capacitor DC-DC step-down charging circuit, voltage electric current gathers feedback circuit, prevents the reverse circuit of irritating, voltage balance circuit.
The voltage and current acquisition feedback circuit acquires the charging voltage and current of the super capacitor and feeds the charging voltage and current back to the DC-DC voltage reduction charging circuit, so that the DC-DC voltage reduction charging circuit outputs proper voltage and current.
The reverse-filling prevention circuit prevents unnecessary loss caused by reverse flowing of electricity in the super capacitor after power failure.
The voltage balancing circuit equalizes the voltage between the super capacitors connected in series.
A capacitor C8 and a capacitor C9 in the super capacitor charging circuit are connected in series, one end of the capacitor C8 is connected with the cathode of the diode D6, the power supply and the resistor R43 respectively, the other end of the capacitor C8 and one end of the capacitor C9 are connected with the other end of the resistor R43 and the resistor R44 respectively, and the other end of the resistor R4 and the other end of the capacitor C9 are grounded respectively; the anode of the diode D6 is respectively connected with a resistor R45, a capacitor C43 and an inductor L4, the other end of the resistor R45 is respectively connected with a resistor R46 and an FB pin of the power chip U4, the other end of the resistor R46 is respectively connected with a ground and a resistor R40, the other end of the resistor R40 is connected with a capacitor C41, and the other end of the capacitor C41 is respectively connected with a power supply, an EN pin and a VIN pin of the chip U4; the other end of the capacitor C43 is grounded and a GND pin of the chip U4 respectively; the other end of the inductor L4 is connected with the SW pin of the chip U4 and the capacitor C42 respectively, and the other end of the capacitor C42 is connected with the BS pin of the chip U4.
Wherein C8 and C9 are two super capacitors connected in series; the capacitor C41, the capacitor C42, the capacitor C43, the inductor L4 and the chip U4 form a DC-DC voltage reduction charging circuit, the resistor R43 and the resistor R44 form a balance circuit, and the variable resistors R40, R45 and R46 are voltage and current acquisition feedback circuits; the resistors R43 and R44 are balance circuits; r40, R45 and R46 are voltage and current acquisition feedback circuits.
Diode D6 is the anti-reverse-charging circuit, VCC and GND are the power supply inputs, and V _ SC and GNDSC are the super capacitor voltage.
The maximum charging current can be adjusted by adjusting the resistance of the R40 resistor:
Imax＝0.6V÷R40。
the charge cutoff voltage can be adjusted by adjusting the resistance values of R45 and R46:
Vmax＝0.6V×(R45+R46)÷R46。
the utility model has the advantages as follows:
the utility model discloses the circuit uses DC-DC step-down charging circuit as super capacitor charging circuit's main part, and the circuit that inductance and electric capacity constitute when charging makes the interval between each pulse of peak power nearer apart, can improve charge efficiency, compares linear charging circuit and can practice thrift charge time and electric energy to accurate control charges cut-off voltage and maximum charging current.
The word "preferred" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "preferred" is not necessarily to be construed as advantageous over other aspects or designs. Rather, use of the word "preferred" is intended to present concepts in a concrete fashion. The term "or" as used in this application is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise or clear from context, "X employs A or B" is intended to include either of the permutations as a matter of course. That is, if X employs A; x is B; or X employs both A and B, then "X employs A or B" is satisfied in any of the foregoing examples.
Also, although the disclosure has been shown and described with respect to one or an implementation, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The present disclosure includes all such modifications and alterations, and is limited only by the scope of the appended claims. In particular regard to the various functions performed by the above described components (e.g., elements, etc.), the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the disclosure. In addition, while a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or other features of the other implementations as may be desired and advantageous for a given or particular application. Furthermore, to the extent that the terms "includes," has, "" contains, "or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term" comprising.
The functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist physically alone, or a plurality of or more units are integrated into one module.
To sum up, the above embodiment is an implementation manner of the present invention, but the implementation manner of the present invention is not limited by the embodiment, and any other changes, modifications, replacements, combinations, and simplifications made under the spirit and principle of the present invention should be equivalent replacement manners, and all included in the protection scope of the present invention.
Claims (2)
1. A super capacitor charging circuit is characterized in that a capacitor C8 and a capacitor C9 are connected in series in the circuit, one end of the capacitor C8 is connected with the negative electrode of a diode D6, the voltage of a super capacitor and a resistor R43 respectively, the other end of the capacitor C8 and one end of the capacitor C9 are connected with the other end of the resistor R43 and a resistor R44 respectively, and the other end of a resistor R4 and the other end of the capacitor C9 are grounded respectively; the anode of the diode D6 is respectively connected with a resistor R45, a capacitor C43 and an inductor L4, the other end of the resistor R45 is respectively connected with a resistor R46 and an FB pin of the power chip U4, the other end of the resistor R46 is respectively connected with a ground and a resistor R40, the other end of the resistor R40 is connected with a capacitor C41, and the other end of the capacitor C41 is respectively connected with a power input, an EN pin and a VIN pin of the chip U4; the other end of the capacitor C43 is grounded and a GND pin of the chip U4 respectively; the other end of the inductor L4 is connected with a SW pin of the chip U4 and a capacitor C42 respectively, and the other end of the capacitor C42 is connected with a BS pin of the chip U4;
the capacitor C41, the capacitor C42, the capacitor C43, the inductor L4 and the chip U4 form a DC-DC voltage reduction charging circuit, the resistor R43 and the resistor R44 form a balance circuit, the resistor R40, the resistor R45 and the resistor R46 form a voltage and current acquisition feedback circuit, and the diode D6 is an anti-reverse-charging circuit.
2. The supercapacitor charge circuit according to claim 1, wherein the chip U4 is of the type MT2492.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223369802.9U CN218771385U (en) | 2022-12-15 | 2022-12-15 | Super capacitor charging circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223369802.9U CN218771385U (en) | 2022-12-15 | 2022-12-15 | Super capacitor charging circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218771385U true CN218771385U (en) | 2023-03-28 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223369802.9U Active CN218771385U (en) | 2022-12-15 | 2022-12-15 | Super capacitor charging circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218771385U (en) |
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2022
- 2022-12-15 CN CN202223369802.9U patent/CN218771385U/en active Active
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