CN218632050U - Grid structure and semiconductor device - Google Patents
Grid structure and semiconductor device Download PDFInfo
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- CN218632050U CN218632050U CN202222253480.5U CN202222253480U CN218632050U CN 218632050 U CN218632050 U CN 218632050U CN 202222253480 U CN202222253480 U CN 202222253480U CN 218632050 U CN218632050 U CN 218632050U
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Abstract
The utility model discloses a grid structure and semiconductor device. The grid structure comprises a grid root and a grid cap, wherein the grid root and the grid cap are intersected at a second endpoint, the grid root comprises a grid bottom surface and a first side surface of the grid root, the two surfaces are intersected at a first endpoint, and the frequency characteristic is improved by requiring the position, distance and size balance relationship between the first endpoint and the second endpoint; the gate cap portions are connected in a non-vertical manner, so that the effect of optimizing electric field distribution in the semiconductor device structure is achieved, and the reliability and the stability of the semiconductor device are improved.
Description
Technical Field
The utility model relates to the field of semiconductor technology, especially, relate to a grid structure and semiconductor device.
Background
The gallium nitride material has the remarkable advantages of large forbidden bandwidth, high electron saturation drift rate, high breakdown field strength, high temperature resistance and the like, is more suitable for manufacturing electronic devices with high temperature, high voltage, high frequency and high power compared with the first generation semiconductor silicon and the second generation semiconductor gallium arsenide, has wide application prospect, and becomes a hotspot of current semiconductor industry research.
With the coming of 5G and new energy era, the requirements of scientific and technological products on high frequency, high-speed operation and high-speed charging are increased, the temperature, the frequency and the power of the first generation semiconductor and the second generation semiconductor represented by silicon and gallium arsenide reach the limit, and the electric quantity and the speed are difficult to increase; particularly, when the operating temperature is too high, products corresponding to the first and second generation semiconductors are liable to malfunction, and thus cannot be used under severe environments. And the third generation semiconductor can still maintain excellent performance and reliability even in a high-frequency state, and meanwhile, the size is smaller, the heat dissipation is better, and the size of the whole circuit can be further reduced. The gallium nitride High Electron Mobility Transistor (HEMT) is a high electron mobility device formed by utilizing two-dimensional electron gas at an AlGaN/GaN heterojunction, can be better applied to the fields of high frequency, high voltage and high power, and is naturally favored in the field of 5G communication.
In the communication field, the requirements on the bandwidth and the high frequency of a semiconductor radio frequency device are high, and the design of a grid structure has a close relation with the frequency characteristic of the semiconductor device, so that the working frequency of the semiconductor device is directly influenced; the gate cap metal design of the gate has a large influence on the electric field of the device, and is extremely important for maintaining the reliability and stability of the semiconductor device. Therefore, in the design and manufacturing process of semiconductor devices, the gate design is particularly important, and plays a key role in the reliability and the stability of the working performance of the semiconductor devices.
Therefore, how to further improve the bandwidth and high frequency performance of the semiconductor device, and simultaneously improve the reliability and stability of the semiconductor device, and can be used for realizing large-scale commercial production preparation, becomes a problem which needs to be solved at present.
SUMMERY OF THE UTILITY MODEL
The utility model provides a grid structure and semiconductor device can satisfy further bandwidth and the high frequency performance who improves semiconductor device, can improve semiconductor device's reliability and stability simultaneously again.
According to an aspect of the present invention, there is provided a gate structure, the gate structure including a gate root and a gate cap, the gate root including a gate bottom surface, a side surface adjacent to the gate bottom surface being a gate root first side surface, one end of the gate root first side surface being connected to the gate bottom surface, defining the connection point as a first end point; the grid root is connected with the grid cap, and the connection point is defined as a second end point; a plane which is bisected and is vertical to the bottom surface of the grid is a bisecting plane, wherein the second endpoint is positioned on one side, away from the bisecting plane, of the plane where the first endpoint is positioned and is parallel to the bisecting plane; l0 is the distance between the two end points (two first end points) of the bottom surface of the gate; m0 is the projection distance of the second end point on one side of the bisection plane and the first end point in the plane direction of the bottom surface of the grid electrode, and M0' is the projection distance of the second end point on the other side of the bisection plane and the first end point in the plane direction of the bottom surface of the grid electrode; and the relationship L0 between the first end point and the second end point is the distance between two end points (two first end points) of the bottom surface of the gate; m0 is a projection distance of the second end point on one side of the bisection plane and the first end point in the plane direction of the bottom surface of the gate, and M0' is a projection distance of the second end point on the other side of the bisection plane and the first end point in the plane direction of the bottom surface of the gate: m0 is less than L0, and M0' is less than L0.
Optionally, the distance relationship between the second end point and the bottom surface of the gate is: m0 is not more than D0; wherein D0 is the vertical distance between the second end point and the bottom surface of the gate.
Optionally, the grid root further includes a second side surface of the grid root, one end of the second side surface of the grid root is connected with the first side surface of the grid root, the other end of the second side surface of the grid root is connected with the grid cap, a connection point of the first side surface of the grid root and the second side surface of the grid root is a third end point, and a projection of the second end point on a plane where the bottom surface of the grid electrode is located on one side, away from the first end point, of a projection of the third end point on the plane where the bottom surface of the grid electrode is located; or the projection of the third end point on the plane of the bottom surface of the grid is superposed with the projection of the second end point on the plane of the bottom surface of the grid.
Optionally, the gate cap includes at least two gate cap sub-portions, wherein a terminal point of a lower surface of a gate cap sub-portion adjacent to the gate root is located on a side, close to the gate root, of a starting terminal point of a lower surface of an upper gate cap sub-portion, the starting terminal point of the lower surface of the upper gate cap sub-portion coincides with a terminal point of an upper surface of a lower gate cap sub-portion, the upper side is a direction away from the gate root, the lower side is a direction close to the gate root, the starting terminal point is a terminal point of a surface of the gate cap sub-portion in a direction close to the gate electrode, the terminal point is a terminal point of the surface of the gate cap sub-portion in a direction away from the gate root, and the starting terminal point and the terminal point are located on the same side of the bisecting plane.
Optionally, M0= M0'.
Optionally, the position relationship of the adjacent gate cap portions is: m1 is less than L1 and M1 is less than D1;
wherein, M1 is a projection distance of a start point of the lower surface of the upper gate cap sub-portion and a terminal point of the lower surface of the lower gate cap sub-portion on the same side of the bisection plane in the plane direction of the gate bottom surface, D1 is a distance of the start point of the lower surface of the upper gate cap sub-portion and the terminal point of the lower surface of the lower gate cap sub-portion on the same side of the bisection plane in the plane direction perpendicular to the gate bottom surface, and L1 is a distance between the start point of the lower surface of the lower gate cap sub-portion and the terminal point of the lower surface on the same side of the bisection plane.
Optionally, the position relationship of the adjacent gate cap portions is: l1 is less than L2;
wherein, L1 is a distance between a starting end point of the lower surface of the lower gate cap sub-portion and a terminal point of the lower surface on the same side of the bisection plane, and L2 is a distance between a starting end point of the lower surface of the upper gate cap sub-portion and a terminal point of the lower surface on the same side of the bisection plane.
According to another aspect of the present invention, there is provided a semiconductor device, including:
a substrate;
a semiconductor layer formed on one side of the substrate;
the source electrode and the drain electrode are formed on one side of the semiconductor layer, which is far away from the substrate;
the passivation layer is formed on one side, far away from the substrate, of the semiconductor layer;
as described in the above utility model, the gate structure is formed on the side of the passivation layer away from the substrate, and the gate cap is located on the side of the gate base away from the semiconductor layer.
Optionally, the dimensional relationship of the same gate cap portion on different sides of the gate bottom is as follows: l1 is more than or equal to L1', and the position relation between the gate cap part farthest from the gate root and the gate structure is as follows: LN is more than or equal to LN';
wherein L1 is a distance between a start end point and an end point of a lower surface of the gate cap section adjacent to the gate root in the drain direction, L1 'is a distance between a start end point and an end point of a lower surface of the gate cap section adjacent to the gate root in the source direction, LN is a distance between a start end point and an end point of a lower surface of the gate cap section farthest from the gate root in the drain direction, and LN' is a distance between a start end point and an end point of a lower surface of the gate cap section farthest from the gate root in the source direction.
Optionally, the semiconductor layer includes a nucleation layer, a buffer layer, a channel layer, and a barrier layer sequentially arranged in a direction away from the substrate layer, wherein the channel layer and the barrier layer form a heterojunction together, and a two-dimensional electron gas layer is formed at the heterojunction;
the position relation between the adjacent gate cap parts and the two-dimensional electron gas layer is as follows: l1 < 5.5 × d2, L2 < 5.5 × d3;
wherein L1 is a distance between a start end point and an end point of a lower surface of the lower gate cap portion in a direction approaching the drain or the source, L2 is a distance between a start end point and an end point of a lower surface of the upper gate cap portion in a direction approaching the drain or the source, D2 is a vertical distance between the lower surface of the lower gate cap portion and the two-dimensional electron gas layer, and D3 is a vertical distance between the lower surface of the upper gate cap portion and the two-dimensional electron gas layer.
The embodiment of the utility model provides a grid structure includes bars root and bars cap, and this grid structure includes that bars root and bars cap intersect in the second extreme point, and bars root includes grid bottom surface and bars root first side and intersects in first extreme point, realizes improving the frequency characteristic through position, distance and the balanced relation of size between first extreme point and the second extreme point of requirement; the grid cap comprises at least two grid cap sub-parts, the grid cap sub-parts are adjacent to each other, the tail end point of the lower surface of the lower grid cap sub-part is positioned on one side, close to the grid root, of the starting end point of the lower surface of the upper grid cap sub-part, and the starting end point of the lower surface of the upper grid cap sub-part is overlapped with the tail end point of the upper surface of the lower grid cap sub-part. The effect of optimizing electric field distribution is realized by arranging non-vertical connection between adjacent gate cap parts, so that the reliability and stability of the semiconductor device are improved.
It should be understood that the statements in this section are not intended to identify key or critical features of the embodiments of the present invention, nor are they intended to limit the scope of the invention. Other features of the present invention will be readily apparent from the following specification.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained without creative efforts.
Fig. 1 is a schematic cross-sectional view of a gate structure according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional view of another gate structure according to an embodiment of the present invention;
fig. 3 is a schematic cross-sectional view of another gate structure provided in an embodiment of the present invention;
fig. 4 is a schematic cross-sectional view of a partial structure of a gate structure according to an embodiment of the present invention;
fig. 5 is a schematic partial cross-sectional view illustrating another gate structure according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a semiconductor device according to a second embodiment of the present invention;
fig. 7 is a schematic structural diagram of another semiconductor device according to an embodiment of the present invention
Detailed Description
In order to make the technical solution of the present invention better understood, the technical solution of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts shall belong to the protection scope of the present invention.
It should be noted that the terms "comprises" and "comprising," and any variations thereof, in the description and claims of this invention and the above-described drawings are intended to cover non-exclusive inclusions, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example one
Fig. 1 is a schematic cross-sectional view of a gate structure according to an embodiment of the present invention. As shown in fig. 1, the gate structure 10 includes a gate root 11 and a gate cap 12. The grid root 11 comprises a grid bottom surface 110, the side surface adjacent to the grid bottom surface 110 is a grid root first side surface 111, one end of the first side surface of the grid root 11 is connected with the grid bottom surface 110, and the connection point is defined as a first end point 1111; the grid root 11 is connected with the grid cap 12, and the connection point is defined as a second end point 1112; m0 is a projection distance of the second endpoint 1112 and the first endpoint 1111 on the same side of the gate bottom surface 110 in the plane direction of the gate bottom surface 110, and M0' is a projection distance of the second endpoint 1112' and the first endpoint 1111' on the other side of the gate bottom surface 110 in the plane direction of the gate bottom surface 110; l0 is the distance between the two end points (the two first end points 1111 and 1111') of the gate bottom surface 110. A plane which is bisected and perpendicular to the bottom surface 110 of the gate electrode is defined as a bisecting plane (refer to fig. 2), wherein the second end point 1112 is located on a side, away from the bisecting plane, of a plane where the first end point 1111 is located and parallel to the bisecting plane; the first side surface 111 of the gate root is located on one side of the first end point 1111 away from the plane where the bottom surface 110 of the gate is located, and the distance relationship between the first end point 1111 and the second end point 1112 satisfies: m0 is less than L0, and M0' is less than L0. In this embodiment, the first end points 1111 and 1111' are not substantially different, but are to distinguish whether the end points are on the same side of the bisecting plane, wherein the first end point 1111 and the second end point 1112 are on the same side, and wherein the first end point 1111' and the second end point 1112' are on the other side.
Preferably, the distance relationship between the first end 1111 and the second end 1112 of the gate structure satisfies: m0 is more than L0/4, and M0' is less than L0/4; the frequency characteristics can be effectively improved.
In other embodiments, the structure of the gate root 11 satisfies M0= M0', which may make the gate structure better applied in the field of radio frequency communication.
In one embodiment, the first gate root side surface 111 is located on one side of the first end point 1111 away from the plane of the gate bottom surface 110, the first gate root side surface 111 is located on one side of the plane parallel to the bisecting plane and away from the bisecting plane, and the projection distance between the second end point 1112 and the first end point 1111 located on the same side of the bisecting plane in the plane direction of the gate bottom surface 110 and the vertical distance between the first end point 1111 and the gate bottom surface 110 satisfy the following conditions, wherein M0 is greater than or equal to D0, and M0 'is greater than or equal to D0'; where D0 and D0 'are the vertical distances between the second end points 1112 and 1111' on both sides of the bottom surface 110 of the gate electrode and the bottom surface 110 of the gate electrode, respectively.
The present invention is provided with a non-perpendicular connection between the gate bottom surface 110 and the gate root first side surface 111, or between the gate bottom surface 110 and the gate cap 12, and the frequency characteristic is improved by requiring a distance between the first end 1111 and the second end 1112 and a size balance relationship.
In another embodiment provided by the present invention, as shown in fig. 2, the grid root 11 further includes a second side surface 112 of the grid root, one end of the second side surface 112 of the grid root is connected to the first side surface 111 of the grid root, and the connection point is defined as a third end point 1113; the other end of the grid root second side surface 112 is connected with the grid cap 12, and the connection point is a second end 1112; the projection of the second end point 1112 on the plane of the gate bottom surface 110 is on the side, away from the first end point 1111, of the projection of the third end point 1113 on the plane of the gate bottom surface 110; or in another embodiment, the projection of the third end point 1113 on the plane of the gate bottom surface 110 coincides with the projection of the second end point 1112 on the plane of the gate bottom surface 110; wherein the third end 1113 is located on the same side of the plane of bisection as the second end 1112.
The side of the connection between the first end 1111 and the second end 1112 may be a plane or a curved surface. In an alternative embodiment, there is a multi-turn surface connection between the first end 1111 and the second end 1112.
The gate structure 10 further includes a gate cap 12, wherein a connection point 1112 of the gate cap 12 and the gate root 11 coincides with an initial end point of the gate cap, and optionally, the gate cap 12 includes at least two gate cap portions. In two adjacent gate cap portions, the end point of the lower surface of the lower gate cap portion is located on the side, close to the gate root 11, of the start end point of the lower surface of the upper gate cap portion, the start end point of the lower surface of the upper gate cap portion is coincident with the end point of the upper surface of the lower gate cap portion, wherein the upper portion is in the direction away from the gate root 11, the lower portion is in the direction close to the gate root 11, the start end point is the end point of the surface of the gate cap portion in the direction close to the gate root 11, and the end point is the end point of the surface of the gate cap portion in the direction away from the gate root 11.
Fig. 3 is a schematic cross-sectional view of another gate structure according to an embodiment of the present invention. Specifically, the gate cap 12 includes a first gate cap portion 121 (a lower gate cap portion) and a second gate cap portion 122 (an upper gate cap portion) along a direction away from the gate root 11, as shown in fig. 3, a connection point 1112 of the gate cap 12 and the gate root 11 coincides with a start end point 1211 of the first gate cap portion 121, a start end point 1212 of a lower surface of the first gate cap portion 121 is located on a side of a start end point 1221 of a lower surface of the second gate cap portion 122 close to the gate root 11, and a start end point 1221 of a lower surface of the second gate cap portion 122 coincides with a start end point 1213 of an upper surface of the first gate cap portion 121.
Fig. 4 is a schematic structural diagram of another gate structure according to the first embodiment of the present invention, and fig. 4 exemplarily shows that the gate cap 12 includes a first gate cap sub-portion 121, a second gate cap sub-portion 122, a 8230, and an nth gate cap sub-portion 12N along a direction away from the gate root 11, and as shown in fig. 4, in two adjacent gate cap sub-portions, an a-th gate cap sub-portion 12A is away from the gate root 11, an a-1-th gate cap sub-portion 12 (a-1) is close to the gate root 11, wherein 1 < a ≦ N, the end point of the lower surface of the a-1 th (lower) gate cap portion 12 (a-1) is located at the side of the start end point of the lower surface of the a-th (upper) gate cap portion 12A close to the gate root 11, the start end point of the lower surface of the a-th (upper) gate cap portion 12A coincides with the end point of the upper surface of the a-1 th (lower) gate cap portion 12 (a-1), wherein the upper is a direction away from the gate root 11, the lower is a direction close to the gate root 11, the start end point is an end point of the surface of the gate cap portion in a direction close to the gate root 11, and the end point is an end point of the surface of the gate cap portion in a direction away from the gate root 11. The adjacent gate cap parts are connected in a non-vertical way, namely the side surface of the lower gate cap part is connected with the lower surface of the upper gate cap part in a non-vertical way, so that the effect of optimizing electric field distribution is realized, and the reliability and the stability of the semiconductor device are improved. In alternative embodiments, the side surface of the uppermost 12N-th gate cap portion 12N may be a side surface perpendicular to the upper surface of the lower gate cap portion, or may be a side surface not perpendicular to the upper surface of the lower gate cap portion.
In other embodiments, the gate cap may include a plurality of gate cap portions, and preferably, the gate cap includes X gate cap portions, X ∈ [2,4], X being an integer.
Fig. 1 and 2 illustrate an example of a connection between adjacent gate cap portions, and in an embodiment, as shown in fig. 5, the adjacent gate cap portions are connected by a curved line, that is, a side surface where the lower surface of the lower gate cap portion is connected with the lower surface of the upper gate cap portion is a curved surface. In an alternative embodiment, the adjacent gate cap portions are connected by multiple turning surfaces, that is, the side surface where the lower surfaces of the lower gate cap portion and the upper gate cap portion are connected is a multiple turning surface. In an alternative embodiment, the side surface of the 12N-th uppermost gate cap portion (N = 3) may be a side surface perpendicular to the upper surface of the lower gate cap portion, or may be a curved surface.
Optionally, taking fig. 3 as an example, in two adjacent gate cap portions, the positional relationship between the adjacent gate cap portions is: m1 < L1 and M1 < D1.
Where M1 is a distance between a starting end point 1221 of the lower surface of the second gate cap part 122 (the upper gate cap part) and a terminal point 1212 of the lower surface of the first gate cap part 121 (the lower gate cap part) in a direction parallel to the contact surface between the gate root 11 and the gate cap 12, D1 is a distance between the starting end point 1221 of the lower surface of the second gate cap part 122 (the upper surface of the first gate cap part 121 (the terminal point 1213) and the terminal point 1212 of the lower surface of the first gate cap part 121 (the lower gate cap part) in a direction perpendicular to the contact surface between the gate root 11 and the gate cap 12, and L1 is a distance between the starting end point 1211 of the lower surface of the first gate cap part 121 (the lower gate cap part) and the terminal point 1212 of the lower surface in a direction parallel to the contact surface between the gate root 11 and the gate cap 12. Thereby reducing parasitic capacitance caused by non-vertical connection of the gate cap portion and improving bandwidth and high frequency performance of the semiconductor device.
Optionally, taking fig. 3 as an example, in two adjacent gate cap portions, the positional relationship between the adjacent gate cap portions is: l1 is less than L2.
Where L1 is a distance between a starting point 1211 of the lower surface of the first gate cap part 121 (the lower gate cap part) and a terminal point 1212 of the lower surface in a direction parallel to the contact surface of the gate root 11 and the gate cap 12, and L2 is a distance between a starting point 1221 of the lower surface of the second gate cap part 122 (the upper gate cap part) and a terminal point 1222 of the lower surface in a direction parallel to the contact surface of the gate root 11 and the gate cap 12. Thereby optimizing the electric field distribution under the gate cap and reducing the dielectric breakdown risk of the gate cap.
It is to be understood that the above exemplary description is given of the positional relationship between two adjacent gate cap portions when the gate cap includes two gate cap portions, and the positional relationship between two adjacent gate cap portions when the gate cap includes a plurality of gate cap portions also satisfies the above relationship, and the description of the present application is omitted here.
The embodiment of the utility model provides a gate structure can extensively be used for fields such as radio frequency microwave, power electronics. The advantages of the method are more obvious especially for gallium nitride electronic devices with large forbidden band width, high electron mobility, high breakdown field strength and good heat conduction performance, the quality of the formed metal electrode is good, the stability of the electrode is good, the electrical performance of the electrode is obviously improved, and the method can better meet the high performance requirements in the fields of fast-developing electronic communication and the like.
Example two
Fig. 6 is a schematic structural diagram of a semiconductor device according to a second embodiment of the present invention, and as shown in fig. 6, the semiconductor device 100 includes a substrate 60, a semiconductor layer 50, a source electrode 20, a drain electrode 30, a passivation layer 40, and a gate structure 10, wherein the semiconductor layer 50 is formed on one side of the substrate 60. The source electrode 20 and the drain electrode 30 are formed on a side of the semiconductor layer 50 remote from the substrate 60. A passivation layer 40 is formed on a side of the semiconductor layer 50 remote from the substrate 60. The gate structure 10 is formed on a side of the passivation layer 40 remote from the substrate 60. And the gate cap 12 is located on the side of the gate stub 11 away from the semiconductor layer 50.
Preferably, in one embodiment of the present application, the passivation layer includes silicon nitride and/or silicon oxynitride. The substrate may be formed of one of silicon, sapphire, silicon carbide, and gallium arsenide, and the semiconductor layer may be formed of one or more of gallium nitride, aluminum gallium nitride, or indium gallium nitride.
In one embodiment, M0 is a projection distance between a second endpoint 1112 at a side of the gate root 11 close to the drain 30 and a first endpoint 1111 at a side of the gate root 11 close to the drain 30 in a plane direction of the gate bottom surface 110, M0' is a projection distance between the second endpoint 1112 at a side of the gate root 11 close to the source 20 and the first endpoint 1111 at a side of the gate root 11 close to the source 20 in the plane direction of the gate bottom surface 110, L0 is a distance between two end points of the gate bottom surface 110, and D0 is a perpendicular distance between the second endpoint 1112 at two sides of the gate bottom surface 110 and the gate bottom surface 110. Thereby reducing parasitic capacitance and improving bandwidth and high frequency performance of the semiconductor device.
Specifically, the second end point 1112 on the side close to the drain electrode 30 of the gate root 11 is located on the side far from the gate root 11 of the first end point 1111 on the side close to the drain electrode 30 of the gate root 11, and the second end point 1112 on the side close to the source electrode 20 of the gate root 11 is located on the side far from the gate root 11 of the second end point 1112 on the side close to the source electrode 20 of the gate root 11; and the first end 1111 and the second end 1112 near the source 20 are located in the following relationship: m0 is more than L0; and the first end 1111 and the second end 1112 near one side of the drain 30 have the following positional relationship: m0' < L0; preferably, the positions of the first end 1111 and the second end 1112 near the source 20 side satisfy the relationship: m0 is more than L0/4; the positions of the first end 1111 and the second end 1112 near the drain electrode 30 side satisfy the relationship: m0' < L0/4.
Alternatively, referring to fig. 4 and fig. 6, the gate cap portion 121 adjacent to the gate root 11 is related to the gate structure 10 in terms of position: l1= L1'; the positional relationship between the nth gate cap portion 12N farthest from the gate root 11 and the gate structure 10 is: LN = LN'. Therefore, the electric field of the grid electrode close to one end of the source electrode is optimized, and the reliability and the stability of the semiconductor device are improved. In this embodiment, M0= M0' in the structure of the gate root 11. The gate root 11 and the gate cap 12 of the present embodiment are both symmetrical structures.
In other embodiments, the gate cap portion 121 adjacent to the gate root 11 is related to the gate structure 10 in position: l1> L1'; the positional relationship between the nth gate cap portion 12N farthest from the gate root 11 and the gate structure 10 is: LN > LN'. Because the grid-drain voltage is far greater than the grid-source voltage when the semiconductor device works, L1 is greater than L1', LN is greater than LN', thereby avoiding parasitic capacitance introduced by L1 'and LN', and improving the bandwidth and high-frequency performance of the semiconductor device. In this embodiment, the structure of the gate root 11 satisfies M0> M0'. The gate root 11 and the gate cap 12 of the present embodiment are both asymmetric structures.
Preferably, in other embodiments, the structure of the gate root 11 satisfies M0= M0', which may improve the rf characteristics, and the positional relationship between the first to nth gate caps 121 to 12N and the gate structure 10 is: LN > LN'. Therefore, the electric field of the grid electrode close to one end of the source electrode is optimized, and the reliability and the stability of the semiconductor device are improved. The gate root 11 of the present embodiment is a symmetric structure, and the gate cap 12 is an asymmetric structure.
Preferably, in other embodiments, the structure of the gate root 11 satisfies M0= M0', and the positional relationship between the first gate cap portion 121 adjacent to the gate root 11 and the gate structure 10 is: l1= L1'; the positional relationship between the gate structure 10 and the other gate cap portions 2 to 12N farther from the gate root is as follows: LN > LN'. Therefore, the electric field of the grid electrode close to one end of the source electrode is optimized, and the reliability and the stability of the semiconductor device are improved. In this embodiment, the gate root 11 and the first gate cap portion 121 are symmetric, and the other gate cap portions are asymmetric.
Where L1 is a distance between a start point and a tail end point of the lower surface of the 1 st gate cap portion 121 adjacent to the gate root 11 in the direction close to the drain 30, L1 'is a distance between a start point and a tail end point of the lower surface of the 1 st gate cap portion 121 adjacent to the gate root 11 in the direction close to the source 20, LN is a distance between a start point and a tail end point of the lower surface of the N-th gate cap portion 12N farthest from the gate root 11 in the direction close to the drain, and LN' is a distance between a start point and a tail end point of the lower surface of the N-th gate cap portion 12N farthest from the gate root 11 in the direction close to the source 20.
Optionally, on the basis of the above embodiment, as shown in fig. 7, the semiconductor layer 50 further includes a nucleation layer 51, a buffer layer 52, a channel layer 53, a barrier layer 54, and optionally a cap layer (not shown) sequentially arranged in a direction away from the substrate 60. In this embodiment, the barrier layer 54 forms an ohmic contact with the source electrode 20 and the drain electrode 30. The channel layer 53 and the barrier layer 54 collectively form a heterojunction at which a two-dimensional electron gas layer 55 is formed. The gate bottom surface 110 may be in contact with the upper surface of the barrier layer 54 or may be located inside the barrier layer 54.
Fig. 7 is a schematic structural diagram of another semiconductor device according to the second embodiment of the present invention, in which the positional relationship between the adjacent gate cap portions and the two-dimensional electron gas layer 55 is L1 < 5.5 × d2, and L2 < 5.5 × d3. The relationship of D0, L1, D1, L2 needs to be properly adjusted according to the positional relationship between the gate bottom surface 110 and the barrier layer 54 to satisfy the distance requirement between the gate cap and the two-dimensional electron layer 55.
Where L1 is a distance between a start point and an end point of a lower surface of the a-1 th gate cap part 12 (a-1) (lower gate cap part) in the adjacent gate cap part in a direction approaching the source electrode 20 or a direction approaching the drain electrode 30. L2 is a distance between a start point and an end point of a lower surface of the adjacent gate cap portion a-th gate cap portion 12A (upper gate cap portion) in a direction approaching the source electrode 20 or a direction approaching the drain electrode 30. D2 is a vertical distance between the lower surface of the a-1 gate cap portion 12 (a-1) in the adjacent gate cap portion and the two-dimensional electron gas layer 55. D3 is a vertical distance between the lower surface of the a-th gate cap portion 12A in the adjacent gate cap portion and the two-dimensional electron gas layer 55. Specifically, when L1>5.5 × d2 (and L2>5.5 × d 3), further increasing the gate cap length does not further mitigate the electric field and increases the parasitic capacitance. Because the distance between the gate cap and the two-dimensional electron gas has great influence on the performance of the device, the thickness of the gate cap can be adjusted according to the depth of the grid structure extending to the semiconductor layer to control the ranges of D2 and D3, and therefore adjustable setting of different power devices is achieved.
Utilize the utility model discloses a gallium nitride radio frequency device that semiconductor device structure formed can improve gallium nitride radio frequency device's power and frequency under the prerequisite that keeps semiconductor device stable performance to more be suitable for high frequency 5G communication field.
In the above-mentioned embodiments, the connection point is only for the connection surface in the cross-sectional view, and the connection surface is specifically corresponding to the three-dimensional structure, and does not limit the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A grid structure comprises a grid root and a grid cap, wherein the grid root comprises a grid bottom surface and a first grid root side surface, the side surface adjacent to the grid bottom surface is the first grid root side surface, one end of the first grid root side surface is connected with the grid bottom surface, and the connection point is a first endpoint; the grid root is connected with the grid cap, and the connection point is a second endpoint; a plane which is bisected and is vertical to the bottom surface of the grid is a bisecting plane, wherein the second endpoint is positioned on one side, away from the bisecting plane, of the plane where the first endpoint is positioned and is parallel to the bisecting plane; it is characterized in that the preparation method is characterized in that,
the distance relationship between the first end point and the second end point is as follows: m0 is more than L0, and M0' is more than L0;
wherein L0 is the distance between two end points of the bottom surface of the grid; m0 is the projection distance of the second end point on one side of the bisection plane and the first end point in the plane direction of the bottom surface of the grid electrode, and M0' is the projection distance of the second end point on the other side of the bisection plane and the first end point in the plane direction of the bottom surface of the grid electrode.
2. The gate structure of claim 1, wherein a distance relationship between the second end point and a bottom surface of the gate is: m0 is not more than D0; wherein D0 is the vertical distance between the second end point and the bottom surface of the gate.
3. The gate structure of claim 1, wherein the gate root further comprises a gate root second side surface, one end of the gate root second side surface is connected with the gate root first side surface, the other end of the gate root second side surface is connected with the gate cap, a connection point of the gate root first side surface and the gate root second side surface is a third end point, and a projection of the second end point on a plane where the bottom surface of the gate is located on one side, away from the first end point, of a projection of the third end point on the plane where the bottom surface of the gate is located; or the projection of the third end point on the plane of the bottom surface of the grid is coincident with the projection of the second end point on the plane of the bottom surface of the grid.
4. The gate structure of claim 1, wherein the gate cap comprises at least two gate cap portions, wherein the gate cap portion located on a side away from the bottom surface of the gate is an upper gate cap portion, and the gate cap portion located on a side close to the bottom surface of the gate adjacent to the upper gate cap portion is a lower gate cap portion; the lower surface of the lower gate cap sub-portion adjacent to the gate root has a terminal point located on a side of a starting terminal point of the lower surface of the upper gate cap sub-portion close to the gate root, the starting terminal point of the lower surface of the upper gate cap sub-portion coincides with a terminal point of the upper surface of the lower gate cap sub-portion, wherein the upper side is a direction away from the gate root, the lower side is a direction close to the gate root, the starting terminal point is a terminal point of the surface of the gate cap sub-portion close to the gate electrode, the terminal point is a terminal point of the surface of the gate cap sub-portion far from the gate root, and the starting terminal point and the terminal point are located on the same side of the bisecting plane.
5. The gate structure of any of claims 1-4, wherein M0= M0'.
6. The gate structure of claim 4, wherein the relationship between the positions of adjacent gate cap portions is: m1 is less than L1 and M1 is less than D1;
wherein M1 is a projection distance of a start end point of the lower surface of the upper gate cap sub-portion and a terminal point of the lower surface of the lower gate cap sub-portion on the same side of the bisection plane in the plane direction of the gate bottom surface, D1 is a distance of the start end point of the lower surface of the upper gate cap sub-portion and the terminal point of the lower surface of the lower gate cap sub-portion on the same side of the bisection plane in the plane direction perpendicular to the gate bottom surface, and L1 is a distance between the start end point of the lower surface of the lower gate cap sub-portion and the terminal point of the lower surface on the same side of the bisection plane.
7. The gate structure of claim 1, wherein the gate cap comprises at least two gate cap portions, wherein the gate cap portion located on a side away from the bottom surface of the gate is an upper gate cap portion, and the gate cap portion located on a side close to the bottom surface of the gate adjacent to the upper gate cap portion is a lower gate cap portion; wherein, the position relation of the adjacent gate cap parts is as follows: l1 is less than L2;
wherein L1 is a distance between a start point and a tail point of the lower surface of the lower gate cap part on the same side of the bisection plane, and L2 is a distance between a start point and a tail point of the lower surface of the upper gate cap part on the same side of the bisection plane.
8. A semiconductor device, characterized in that the semiconductor device comprises:
a substrate;
a semiconductor layer formed on one side of the substrate;
the source electrode and the drain electrode are formed on one side of the semiconductor layer, which is far away from the substrate;
the passivation layer is formed on one side, far away from the substrate, of the semiconductor layer;
the gate structure of any of claims 1-7, wherein the gate structure is formed on a side of the passivation layer away from the substrate, and the gate cap is on a side of the gate stub away from the semiconductor layer.
9. The semiconductor device of claim 8, wherein the gate cap comprises at least two gate cap segments, and the gate cap segments are located on different sides of the gate bottom in a dimensional relationship of: l1 is more than or equal to L1', and the position relation between the gate cap part farthest from the gate root and the gate structure is as follows: LN is more than or equal to LN';
wherein L1 is a distance between a start end point and an end point of a gate cap portion adjacent to the gate root near the lower surface in the drain direction, L1 'is a distance between a start end point and an end point of a gate cap portion adjacent to the gate root near the lower surface in the source direction, LN is a distance between a start end point and an end point of a gate cap portion farthest from the gate root near the lower surface in the drain direction, and LN' is a distance between a start end point and an end point of a gate cap portion farthest from the gate root near the lower surface in the source direction.
10. The semiconductor device according to claim 8, wherein the semiconductor layer comprises a nucleation layer, a buffer layer, a channel layer, and a barrier layer arranged in this order in a direction away from the substrate, wherein the channel layer and the barrier layer together form a heterojunction at which a two-dimensional electron gas layer is formed; the grid cap comprises at least two grid cap parts, wherein in the at least two grid cap parts, the grid cap part positioned on one side far away from the bottom surface of the grid is an upper grid cap part, and the grid cap part adjacent to the upper grid cap part positioned on one side close to the bottom surface of the grid is a lower grid cap part;
the position relation between the adjacent gate cap part and the two-dimensional electron gas layer is as follows: l1 < 5.5 × d2, L2 < 5.5 × d3;
wherein L1 is a distance between a start end point and an end point of the lower surface of the lower gate cap portion in the direction of the drain or the source, L2 is a distance between a start end point and an end point of the lower surface of the upper gate cap portion in the direction of the drain or the source, D2 is a vertical distance between the lower surface of the lower gate cap portion and the two-dimensional electron gas layer, and D3 is a vertical distance between the lower surface of the upper gate cap portion and the two-dimensional electron gas layer.
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| CN202222253480.5U CN218632050U (en) | 2022-08-25 | 2022-08-25 | Grid structure and semiconductor device |
| PCT/CN2023/114844 WO2024041626A1 (en) | 2022-08-25 | 2023-08-25 | Gate structure, semiconductor device, and method for preparing semiconductor device |
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| WO2024041626A1 (en) * | 2022-08-25 | 2024-02-29 | 苏州能讯高能半导体有限公司 | Gate structure, semiconductor device, and method for preparing semiconductor device |
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| WO2024041626A1 (en) * | 2022-08-25 | 2024-02-29 | 苏州能讯高能半导体有限公司 | Gate structure, semiconductor device, and method for preparing semiconductor device |
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