CN106876467A - MISFET devices based on vertical-channel and preparation method thereof - Google Patents

MISFET devices based on vertical-channel and preparation method thereof Download PDF

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Publication number
CN106876467A
CN106876467A CN201710087137.9A CN201710087137A CN106876467A CN 106876467 A CN106876467 A CN 106876467A CN 201710087137 A CN201710087137 A CN 201710087137A CN 106876467 A CN106876467 A CN 106876467A
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China
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grid
semiconductor
contact ring
source electrode
drain electrode
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CN201710087137.9A
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Chinese (zh)
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董志华
张佩佩
张辉
蔡勇
刘国华
柯华杰
周涛
程知群
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杭州电子科技大学
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Publication of CN106876467A publication Critical patent/CN106876467A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827Vertical transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/452Ohmic electrodes on AIII-BV compounds
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666Vertical transistors

Abstract

The invention discloses a kind of MISFET (metal-insulator dielectric semiconductor FET) device based on vertical-channel and preparation method thereof.The MISFET devices include source electrode, drain electrode, grid and MIS structure, the axis of the MIS structure is basically perpendicular to a selected plane, the MIS structure includes semiconductor structure and the dielectric set around semiconductor structure, and it is formed with raceway groove in the interface of the semiconductor structure and dielectric, the source electrode is electrically connected with drain electrode through the raceway groove, and the grid is distributed between source electrode and drain electrode.MISFET devices of the invention have that grid-control ability is good, working frequency is high, and technology difficulty is low, it is easy to make, the advantages of high yield rate.

Description

MISFET devices based on vertical-channel and preparation method thereof

Technical field

The present invention relates to a kind of semiconductor devices, more particularly to a kind of MISFET (Vertical based on vertical-channel Channel Heterostructure Metal-Insulator-Semiconductor Field-effect Transistor, VC-MISFET) device and preparation method thereof.

Background technology

With the development of microelectric technique, cmos device and integrated circuit have stepped into the so-called rear mole epoch, that is, The development of integrated circuit has progressively deviateed the curve of " Moore's Law ".Particularly when the grid of device are long and channel length increasingly " short-channel effect ", " DIBL effects " (the Drain Induced Barrier brought during short, gate dielectric layer more and more thinner Lowering, the potential barrier reduction that drain terminal is introduced) and the direct tunnelling of source and drain etc. so that device dimensions shrink is more and more difficult.And And shortened because grid are long, grid-control ability declines, and makes the subthreshold amplitude of oscillation of device and switching current than declining, and brings power consumption increase etc. A series of problems.In order to solve problem above, researcher proposes Si base Fin-FET, Si bases vertical channel device, based on receiving The solutions such as the vertical devices of rice noodles.But these solutions still suffer from some defects.For example, Fin-FET still will be by Photoetching technique is long to obtain smaller grid.And for example, device based on Si nano wires etc. must carry out local doping, which increase work Skill difficulty.For another example, Si bases vertical channel device can in advance form the structure of multilayer difference doping type and etch to form vertical again Channel structure, but, this undoubtedly more increases the complexity of technique, and Si material systems by its material character institute Limit, it is not satisfactory in the performance of the aspects such as high pressure resistant and high temperature resistant, radioresistance.

The content of the invention

It is a primary object of the present invention to provide a kind of MISFET (Metal-Insulator- based on vertical-channel Semiconductor Field-effect Transistor, metal-insulator medium or oxide semiconductor field effect pipe) device Part and preparation method thereof, to overcome the deficiencies in the prior art.

For achieving the above object, present invention employs following technical scheme:

The embodiment of the invention provides the MISFET devices based on vertical-channel, including source electrode, drain electrode, grid and MIS Structure, it is characterised in that:The MIS structure includes that at least semiconductor structure and the insulation set around semiconductor structure are situated between Matter, and raceway groove is formed with the interface of the semiconductor structure and dielectric, the axis of the raceway groove is basically perpendicular to one Selected plane, the source electrode is electrically connected with drain electrode through the raceway groove, and the grid is distributed between source electrode and drain electrode.

In some preferred embodiments, the MISFET devices include a plurality of semiconductor structures of array distribution, and The channel array being made up of a plurality of described raceway grooves is formed between a plurality of semiconductor structures and dielectric.

In some preferred embodiments, at least one of the source electrode, drain electrode and grid are parallel to described selected flat Face.Further, the source electrode, drain electrode and the semiconductor structure form Ohmic contact.

Further, the material of the semiconductor structure can be selected from III~V races semiconductor.

The embodiment of the present invention additionally provides a kind of preparation method of the MISFET devices based on vertical-channel, and it includes:

In MIS structure is formed on substrate principal plane, the MIS structure includes at least semiconductor structure and around semiconductor The dielectric of structure setting, and raceway groove is formed with the interface of the semiconductor structure and dielectric, the raceway groove Axis is basically perpendicular to a selected plane;

Source electrode, grid and drain electrode are made, and the source electrode is electrically connected through the raceway groove with drain electrode, the grid is distributed in Between source electrode and drain electrode.

In some preferred embodiments, described preparation method also includes:Array is formed on the substrate principal plane A plurality of semiconductor structures and dielectric of distribution, and make to be formed between a plurality of semiconductor structures and dielectric by multiple The channel array of several described raceway groove compositions.

In some preferred embodiments, at least one of the source electrode, drain electrode and grid are parallel to described selected flat Face.Further, the source electrode, drain electrode and the semiconductor structure form Ohmic contact.

Further, the material of the semiconductor structure can be selected from III~V races semiconductor.

Than prior art, the present invention at least has the following advantages that:

(1) grid of MISFET devices of the present invention can realize that full angle is surrounded to raceway groove, therefore can carry to greatest extent Grid-control ability high.

(2) grid length of MISFET devices of the present invention is determined by the gate metal thickness for depositing, therefore its thickness limit Monoatomic layer thickness can be reached, i.e. the limit of photoetching can be broken through, and then device operating frequencies can be greatly improved.

(3) MISFET devices of the invention can form Ohmic contact because of III-V devices through high-temperature alloy mode, so Do not need to carry out local doping to the semiconductor at source, drain contact, simplify technique;

(4) MISFET devices of the invention make when, without consider as existing planar structure device grid, leak Pole, the lead crossover problem of source electrode, can greatly simplify technology difficulty, improve yield rate.

Brief description of the drawings

In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this Some embodiments described in invention, for those of ordinary skill in the art, on the premise of not paying creative work, Other accompanying drawings can also be obtained according to these accompanying drawings.

Fig. 1 is that a kind of stereochemical structure of MISFET devices based on vertical-channel in an exemplary embodiments of the invention is illustrated Figure.

Fig. 2 is a kind of front view of the MISFET devices based on vertical-channel in an exemplary embodiments of the invention.

Fig. 3 is a kind of top view of the MISFET devices based on vertical-channel in an exemplary embodiments of the invention.

Fig. 4 is a kind of left view of the MISFET devices based on vertical-channel in an exemplary embodiments of the invention.

Fig. 5 is a kind of front view of the MISFET devices based on vertical-channel in another exemplary embodiments of the invention.

Fig. 6 is a kind of top view of the MISFET devices based on vertical-channel in another exemplary embodiments of the invention.

Fig. 7 is a kind of left view of the MISFET devices based on vertical-channel in another exemplary embodiments of the invention.

Specific embodiment

A kind of MISFET devices (VC-MISFET) based on vertical-channel that the one side of the embodiment of the present invention is provided can So that including source electrode, drain electrode, grid and MIS structure, the MIS structure includes at least semiconductor structure and around semiconductor junction The dielectric that structure is set, and it is formed with raceway groove, the axle of the raceway groove in the interface of the semiconductor structure and dielectric Line is basically perpendicular to a selected plane, and the source electrode is electrically connected with drain electrode through the raceway groove, and the grid is distributed in source electrode and leakage Between pole.

Foregoing " being basically perpendicular to " refers to that the axis of the raceway groove is in 90 ° with the selected plane or close to 90 ° Angle, i.e., the mode that described raceway groove can stand relative to the selected plane standing or inclination is set.

Further, the axis of the MIS structure is basically perpendicular to the selected plane.

Wherein, the MIS structure can be column, its radial section can be circle, regular hexagon, triangle or its One kind in its closed polygon.That is, the MIS structure can be with cylindrical, prism-shaped etc..

Further, the semiconductor is column, and the shape of its radial section can be including the rule such as polygon or circle Or irregular shape, but not limited to this.

Further, the semiconductor structure is nano-pillar, and it can make the device with more best performance.

In some preferred embodiments, the dielectric is coaxially disposed with semiconductor structure.

Further, along raceway groove axial direction interval setting, the grid is located at source electrode and drain electrode for the source electrode and drain electrode Between.In this way, source, leakage, grid are non-coplanar, so lead crossover of grid, drain electrode, source electrode etc. need not be considered when making Problem, can greatly simplify technology difficulty.

In some embodiments, the source electrode and drain electrode can be respectively provided with the raceway groove two ends.Also, the source electrode Position with drain electrode can exchange.

Further, the source electrode and drain electrode forms Ohmic contact with semiconductor structure, so as to realize that source, drain electrode can pass through Raceway groove forms electrical connection.

In some preferred embodiments, the distance between the grid and source electrode are less than between the grid and drain electrode Distance, to obtain larger breakdown voltage.

In some preferred embodiments, the grid is set around the raceway groove.Further, the grid is around institute State MIS structure setting.That is, the grid realizes that full angle is surrounded to the raceway groove, so can to greatest extent improve grid-control Ability.

In some preferred embodiments, at least one of the source electrode, drain electrode and grid are parallel to described selected flat Face, can so make MISFET devices when making, without considering as existing planar structure device grid, drain electrode, source electrode Lead crossover problem, can greatly simplify technology difficulty, improve yield rate.

It is further preferred that the source electrode, drain electrode and grid so can further simplify each parallel to the selected plane The manufacture craft of source, leakage and grid, reduces cost of manufacture.

Further, to avoid big grid source, gate-drain parasitic capacitances, between the grid and source electrode and the grid with Overlapping area between drain electrode (is also regarded as grid and source electrode and/or drains in the friendship of the orthographic projection in the selected plane Folded area) should be as far as possible small.

Further, the length and diameter of the raceway groove can be according to being actually needed and relative set.

In some more specific embodiment, the length of the raceway groove can reach nanoscale, when it is less than symbol During the value of conjunction condition, will make the device that there is more best performance, for example, produce the performances such as ballistic transport.

Further, the length (that is, in the upward thickness of the channel axes) of the grid can be by grid metal Deposit thickness is controlled, therefore with minimum, or even can reach single electron thickness degree, breaks through the limit of photoetching, thus can So that device operating frequencies are greatly improved and terahertz wave band is extended to.

Likewise, for the source electrode and drain electrode, its length (that is, in the upward thickness of the channel axes) also may be used It is controlled with by the deposit thickness to source metal, leakage metal.

In some preferred embodiments, the MISFET devices include a plurality of semiconductor structures of array distribution, and The channel array being made up of a plurality of described raceway grooves is formed between a plurality of semiconductor structures and dielectric (can also be claimed It is raceway groove cluster), can so improve device current.Obvious, by controlling the quantity etc. of the channel array, it is right to realize The accuracy controlling of device current.Further, the channel array can be using the known lattice structure of industry.

In some embodiments, at least one of the source electrode and drain electrode between grid also retain or do not retain every From insulating medium layer.Preferably, any one of the source electrode and drain electrode between grid without isolated insulation dielectric layer.Enter one Step, the material of foregoing isolated insulation dielectric layer can be selected from the material that the industries such as silica, silicon nitride, aluminum oxide are commonly used.

In some more specific case study on implementation, the source electrode includes source contact ring, and the source contact ring surround The raceway groove is set.Further, the source contact ring can also be electrically connected through connecting line with source lead disk.

In some more specific case study on implementation, the drain electrode includes drain contact ring, and the drain contact ring surround The raceway groove is set.Further, the drain contact ring can also be electrically connected through connecting line with drain lead disk.

In some more specific case study on implementation, the grid includes gate contact ring, and the gate contact ring surround The raceway groove is set.Further, the gate contact ring can also be electrically connected through connecting line with grid lead disk.

Further, at least one of foregoing source contact ring, drain contact ring and gate contact ring and the ditch Road is coaxially disposed.

Further, at least one of foregoing source contact ring, drain contact ring and gate contact ring are parallel to institute State selected plane.

In some preferred embodiments, the grid can also have field plate structure.

In some more specific case study on implementation, the MISFET devices may also include substrate, and the selected plane is The substrate principal plane, and the raceway groove is formed on the substrate principal plane.

Further, the substrate that the substrate can be commonly used selected from industry, such as Sapphire Substrate, GaN substrate, SiC linings Bottom etc., and not limited to this.

The MISFET devices based on vertical-channel can be made up of commonly seeing process for fabricating semiconductor device.

It is summarized, compared with existing plane HEET, MISFET device of the present invention based on vertical-channel has following excellent Point:First, the gate electrode length of device is decided by the thickness of metal, it is not necessary to defined by photoetching process, therefore, it can break through Photoetching resolution is limited, and obtains minimum grid long.There is extremely important meaning for improving device frequency characteristic.Second, due to grid 360 ° of encirclement raceway grooves of electrode, it is possible to grid-control ability is greatly improved, so as to obtain very high transconductance and reduce off-state current.With Existing vertical-channel Si base devices or vertical-type Si base nano-wire devices are compared, and it equally has following advantage:The device is not Needs carry out local doping process, can substantially reduce device technology cost.

The other side of the embodiment of the present invention is additionally provided and a kind of makes the foregoing MISFET devices based on vertical-channel Method, it can include:

In MIS structure is formed on substrate principal plane, the MIS structure includes at least semiconductor structure and around semiconductor The dielectric of structure setting, and raceway groove is formed with the interface of the semiconductor structure and dielectric, the raceway groove Axis is basically perpendicular to a selected plane;

Source electrode, grid and drain electrode are made, and the source electrode is electrically connected through the raceway groove with drain electrode, the grid is distributed in Between source electrode and drain electrode.

Further, in the preparation method, can be by epitaxial growth regime known to the industries such as MOCVD, PECVD The semiconductor structure is formed equal to growth on substrate principal plane.

Further, in the preparation method, can make to form foregoing by modes such as metal sputtering, atom laminations Source electrode, drain electrode, grid etc..And the material of these electrodes can also be selected from metal or the nonmetallic materials that industry is commonly used, particularly Metal material, such as Au, Ni, Ti etc..

Further, in the preparation method, it is also possible to by physically and/or chemically depositional mode shape known to industry Into foregoing insulating medium layer etc..

Further, in described preparation method, N-shaped doping can be carried out to the semiconductor structure, to improve State the electron concentration of raceway groove in MIS structure.

Further, described preparation method may also include:The plural number of array distribution is formed on the substrate principal plane Individual semiconductor structure and dielectric, and make to be formed by a plurality of described between a plurality of semiconductor structures and dielectric The channel array of raceway groove composition.

Further, described preparation method also includes:The source electrode and drain electrode is set to form Europe with the semiconductor structure Nurse is contacted.

Below in conjunction with the accompanying drawing in the embodiment of the present invention, detailed retouching is carried out to the technical scheme in the embodiment of the present invention State, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.Based on the present invention In embodiment, the every other implementation that those of ordinary skill in the art are obtained on the premise of creative work is not made Example, belongs to the scope of protection of the invention.

It is a kind of MISFET (VC- based on vertical-channel in an exemplary embodiments of the invention to refer to shown in Fig. 1 MISFET) device, it is including substrate, MIS structure source electrode, drain electrode, grid etc..

Further, the MIS structure can be column structure, and it can be main by dielectric a and semiconductor structure b The coaxial configuration of composition.The interface of dielectric a and semiconductor structure b is formed with raceway groove (not shown).The ditch The axis in road is set perpendicular to substrate principal plane.

Wherein, around the raceway groove, particularly described MIS structure is set the grid, and between source, drain electrode.

Wherein, the source electrode and drain electrode are respectively arranged at the upper/lower terminal of raceway groove, and form ohm with first, semiconductor Contact so that source, drain electrode can be formed by raceway groove and electrically connected.

Further, isolated insulation dielectric layer can also be distributed between the grid and the drain electrode and/or source electrode, it is described The material of dielectric layer can be Si3N4, etc., and not limited to this.But it is more highly preferred to, between the grid and the drain electrode, source electrode Without isolated insulation dielectric layer.

Further, the drain electrode can include that drain contact ring c1, drain contact ring c1 can be connected by draining Line c3 is electrically connected with drain lead disk c2.

Further, the grid can include that gate contact ring e1, gate contact ring e1 can be connected by grid Line e3 is electrically connected with grid lead disk e2.

Further, the source electrode can include that source contact ring g1, source contact ring g1 can be connected by source electrode Line g3 is electrically connected with source lead disk g2.

Further, the material of aforesaid semiconductor raceway groove can be the III~V such as GaN races semi-conducting material etc..

Further, foregoing grid, source electrode, the material of drain electrode can be selected from Suitable metal materials known to industry.

Further, the material of aforementioned dielectric medium can be Si3N4Deng or all kinds of applicable metal oxides etc..

A kind of method for preparing the VC-MISFET devices in an exemplary embodiments of the invention can include following step Suddenly:

(1) the main MIS structure being made up of dielectric a and semiconductor structure b is formed on selected substrate principal plane.

(2) drain electrode is formed, including around the drain contact ring c1 of raceway groove.

(3) the isolated insulation dielectric layer between deposition grid, leakage.

(4) grid is formed, including around the gate contact ring e1 of raceway groove.

(5) the isolated insulation dielectric layer between deposition grid, source.

(6) source electrode is formed, including around the source contact ring g1 of raceway groove.

(7) grid of the removal outside lead wire tray and the isolated insulation dielectric layer between drain electrode, grid and source electrode.

(8) etching forms source electrode, grid, the contact hole of drain lead disk.

(9) source electrode, grid, drain lead are made.

Further, foregoing drain bond wires c3, gate connection line e3, source connection lines g3 are all not parallel.

Fig. 2-Fig. 4 is referred to again, and a kind of MISFET based on vertical-channel in an exemplary embodiments of the invention can be wrapped Include substrate 3, MIS structure, source electrode 4, grid 5 and drain electrode 6 etc..

Further, the MIS structure includes dielectric 2 and semiconductor structure 1, and the dielectric 2 is around described Semiconductor structure 1 is set.

Further, to collectively constitute column with the semiconductor structure 1 as core coaxial for the dielectric 2 as shell MIS structure, and it is formed with raceway groove (not shown), the channel vertical in the interface of dielectric 2 and semiconductor structure 1 It is arranged at substrate principal plane.

Further, the source electrode and drain electrode are located at the coaxial MIS structure two ends of column respectively, and form ohm with semiconductor Contact, and electrically connected by the raceway groove.

Further, the source electrode, grid, drain metal are parallel with substrate principal plane, and grid is located at source, drains it Between.

In the MISFET devices of the exemplary embodiments, semiconductor structure, the material of dielectric, diameter, length, shape Depending on can be according to being actually needed.For example, semiconductor can be InP nano wires, diameter can be 100nm, and dielectric Can be Si3N4, thickness can be about 10nm, and the two forms coaxial MIS structure, and also N-shaped doping can be carried out in InP.Absolutely The radial section of edge medium and semiconductor can be circle etc..The length of postscript, wherein raceway groove, Ye Jiyuan, drain electrode between away from Depending on can also be according to being actually needed, for example, can be 50nm.Wherein, the grid length of the MISFET devices, source, drain electrode away from Depending on also can be according to being actually needed from, grid, source electrode distance etc., the length of such as grid can be 5nm, source, drain electrode away from From that can be 30nm, grid, the distance of source electrode can be 15nm.Wherein, drain electrode may be located at MISFET devices top side, source electrode May be located at MISFET devices bottom side.Postscript, source, the thickness of drain electrode can require that size gives according to total output current of device Rationally design.

In another exemplary embodiments of the invention, a kind of MISFET (VC-MISFET) device based on vertical-channel There can be the structure shown in Fig. 5~Fig. 7, in Fig. 5~Fig. 7, the lexical or textual analysis of each reference is the same as those described above.

Further, the VC-MISFET devices are including substrate, MIS structure, source electrode and drain electrode etc..

The MIS structure includes that the dielectric is around these semiconductors by some semiconductor structure b and dielectric a Structure setting, and make these semiconductor structures that the channel array being made up of some raceway grooves is formed with dielectric.These raceway grooves are equal Set perpendicular to substrate principal plane.

Wherein, the semiconductor structure b may each be column structure.These semiconductor structures b is each perpendicular to substrate master Plane is set.

Wherein, the grid is set around each raceway groove, and between source, drain electrode.

The source electrode and drain electrode can be respectively arranged at the upper/lower terminal of each raceway groove, and form ohm with each semiconductor structure and connect Touch so that source, drain electrode can be formed by each raceway groove and electrically connected.

Aforesaid semiconductor structure can be the GaN grown along c-axis, depending on its diameter can be according to being actually needed, for example may be used Think 0~2 μm (not being 0).

Aforementioned dielectric medium can be Si3N4, its radial thickness can be 10~25nm.

The length of aforementioned trenches, depending on the distance between Ye Jiyuan, drain electrode can be according to being actually needed, for example, can be 100nm。

Aforementioned trenches array can be dot matrix form, for example, can be distributed as 3*3 square lattices.

The radial section of aforementioned dielectric medium and semiconductor structure can be the shapes such as circle.

In the MISFET devices of the exemplary embodiments, the grid length of device, source, drain electrode distance, grid, source electrode distance etc. Also depending on can be according to being actually needed, for example, grid length can be 10nm, source, drain electrode distance can be 60nm, grid, source Pole span is from can be 30nm.Wherein, drain electrode may be located at the MISFET devices bottom side, and source electrode may be located at the MISFET devices top Side.Additionally, source, the thickness of drain electrode can require that size gives rationally design according to total output current of device.

The present invention is not limited to foregoing embodiment.In fact, many utilization the technology of the present invention features can also be had not The change form of same type design.For example, in foregoing case study on implementation, between grid and drain electrode and source electrode and grid it Between also can be set alumina medium layer etc..

It should be noted that herein, term " including ", "comprising" or its any other variant be intended to non-row His property is included, so that process, method, article or equipment including a series of key elements not only include those key elements, and And also include other key elements being not expressly set out, or also include for this process, method, article or equipment institute are intrinsic Key element.In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that including institute Also there is other identical element in process, method, article or the equipment of stating key element.

It should be appreciated that the above is only specific embodiment of the invention, for the ordinary skill people of the art For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should It is considered as protection scope of the present invention.

Claims (10)

1. a kind of MISFET devices based on vertical-channel, including source electrode, drain electrode, grid and MIS structure, it is characterised in that: The MIS structure includes at least semiconductor structure and the dielectric set around semiconductor structure, and in the semiconductor The interface of structure and dielectric is formed with raceway groove, and the axis of the raceway groove is basically perpendicular to a selected plane, the source electrode Electrically connected through the raceway groove with drain electrode, the grid is distributed between source electrode and drain electrode.
2. MISFET devices based on vertical-channel according to claim 1, it is characterised in that:The MISFET devices bag Include and be formed with by a plurality of between a plurality of semiconductor structures of array distribution, and a plurality of semiconductor structures and dielectric The channel array of described raceway groove composition.
3. MISFET devices based on vertical-channel according to claim 1 and 2, it is characterised in that:The MIS structure Axis is basically perpendicular to the selected plane;Preferably, the semiconductor structure is coaxially disposed with dielectric;Preferably, institute MIS structure is stated for column;Preferably, the radial cross-sectional shape of the MIS structure includes polygon or circle;Preferably, it is described Semiconductor structure is column;Preferably, the radial cross-sectional shape of the semiconductor structure includes polygon or circle;Preferably, The semiconductor structure is nano-pillar.
4. MISFET devices based on vertical-channel according to claim 1, it is characterised in that:The source electrode, drain electrode with The semiconductor structure forms Ohmic contact;Preferably, the source electrode and drain electrode are along raceway groove axial direction interval setting;It is preferred that , the distance between the grid and source electrode are less than the distance between the grid and drain electrode;Preferably, the source electrode and drain electrode It is respectively provided with the raceway groove two ends;Preferably, the grid is set around the MIS structure;Preferably, the source electrode, leakage At least one of pole and grid are parallel to the selected plane;Preferably, the source electrode, drain electrode and grid are each parallel to described Selected plane.
5. MISFET devices based on vertical-channel according to claim 1, it is characterised in that:The source electrode includes source electrode Contact ring, the source contact ring is set around the raceway groove;Preferably, the source contact ring is through connecting line and source lead Disk is electrically connected;Preferably, the drain electrode includes drain contact ring, and the drain contact ring is set around the raceway groove;Preferably, The drain contact ring is electrically connected through connecting line with drain lead disk;Preferably, the grid includes gate contact ring, the grid Pole contact ring is set around the raceway groove;Preferably, the gate contact ring is electrically connected through connecting line with grid lead disk;It is preferred that , at least one of the source contact ring, drain contact ring and gate contact ring are coaxially disposed with the MIS structure;It is excellent Choosing, at least one of the source contact ring, drain contact ring and gate contact ring are parallel to the selected plane.
6. MISFET devices based on vertical-channel according to claim 1, it is characterised in that:In the source electrode and drain electrode At least one also retain between grid or do not retain isolated insulation dielectric layer;Preferably, appointing in the source electrode and drain electrode Without isolated insulation dielectric layer between one and grid;And/or, the grid has field plate structure;And/or, the MISFET Device also includes substrate, and the selected plane is the substrate principal plane, and the semiconductor structure forms flat in substrate master On face;And/or, the material of the semiconductor structure is selected from III~V races semiconductor.
7. a kind of preparation method of the MISFET devices based on vertical-channel, it is characterised in that including:
In MIS structure is formed on substrate principal plane, the MIS structure includes at least semiconductor structure and around semiconductor structure The dielectric of setting, and it is formed with raceway groove, the axis of the raceway groove in the interface of the semiconductor structure and dielectric It is basically perpendicular to a selected plane;
Source electrode, grid and drain electrode are made, and the source electrode is electrically connected through the raceway groove with drain electrode, the grid is distributed in source electrode And drain electrode between.
8. preparation method according to claim 7, it is characterised in that including:Array point is formed on the substrate principal plane A plurality of semiconductor structures and dielectric of cloth, and make to be formed by plural number between a plurality of semiconductor structures and dielectric The channel array of individual described raceway groove composition.
9. preparation method according to claim 7, it is characterised in that:The axis of the MIS structure is basically perpendicular to described Selected plane;Preferably, the semiconductor structure is coaxially disposed with dielectric;Preferably, the MIS structure is column;It is excellent Choosing, the radial cross-sectional shape of the MIS structure includes polygon or circle;Preferably, the semiconductor structure is column;; Preferably, the radial cross-sectional shape of the semiconductor structure includes polygon or circle;Preferably, the semiconductor structure is to receive Meter Zhu.
10. preparation method according to claim 7, it is characterised in that:The source electrode, drain electrode and the semiconductor structure Into Ohmic contact;Preferably, the source electrode and drain electrode are along raceway groove axial direction interval setting;Preferably, the grid and source electrode The distance between less than the grid with drain electrode the distance between;Preferably, the source electrode and drain electrode is respectively provided with the raceway groove At two ends;Preferably, the grid is set around the MIS structure;Preferably, in the source electrode, drain electrode and grid at least One is parallel to the selected plane;Preferably, the source electrode, drain electrode and grid are each parallel to the selected plane;Preferably, The source electrode includes source contact ring, and the source contact ring is set around the raceway groove;Preferably, the source contact ring warp Connecting line is electrically connected with source lead disk;Preferably, the drain electrode includes drain contact ring, and the drain contact ring is around described Raceway groove is set;Preferably, the drain contact ring is electrically connected through connecting line with drain lead disk;Preferably, the grid includes Gate contact ring, the gate contact ring is set around the raceway groove;Preferably, the gate contact ring is through connecting line and grid Lead wire tray is electrically connected;Preferably, at least one of the source contact ring, drain contact ring and gate contact ring with it is described MIS structure is coaxially disposed;Preferably, the source contact ring, drain contact ring are parallel with least one of gate contact ring In the selected plane;And/or, the material of the semiconductor structure is selected from III~V races semiconductor.
CN201710087137.9A 2017-02-17 2017-02-17 MISFET devices based on vertical-channel and preparation method thereof CN106876467A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1731587A (en) * 2005-08-05 2006-02-08 西安电子科技大学 Vertical type wide bandgap semiconductor device structure and making method
US8097922B1 (en) * 2007-05-29 2012-01-17 The Regents Of The University Of California Nanometer-scale transistor architecture providing enhanced carrier mobility
US20150021664A1 (en) * 2013-07-18 2015-01-22 Sensor Electronic Technology, Inc. Lateral/Vertical Semiconductor Device with Embedded Isolator
CN104823282A (en) * 2012-12-18 2015-08-05 英特尔公司 Vertical nanowire transistor with axially engineered semiconductor and gate metallization

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1731587A (en) * 2005-08-05 2006-02-08 西安电子科技大学 Vertical type wide bandgap semiconductor device structure and making method
US8097922B1 (en) * 2007-05-29 2012-01-17 The Regents Of The University Of California Nanometer-scale transistor architecture providing enhanced carrier mobility
CN104823282A (en) * 2012-12-18 2015-08-05 英特尔公司 Vertical nanowire transistor with axially engineered semiconductor and gate metallization
US20150021664A1 (en) * 2013-07-18 2015-01-22 Sensor Electronic Technology, Inc. Lateral/Vertical Semiconductor Device with Embedded Isolator

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