CN218549919U - ACARS signal processing system - Google Patents

Abstract

The utility model discloses an ACARS signal processing system, which comprises an ADC signal acquisition unit, a data transmission storage unit, a data processing unit and a power supply control unit; a first input end of the ADC signal acquisition unit collects intermediate frequency radio frequency signals; the output end of the ADC signal acquisition unit is connected with the first input end of the data processing unit; the first output end of the power supply control unit is connected with the second input end of the ADC signal acquisition unit; the second output end of the power supply control unit is connected with the second input end of the data processing unit; the first output end of the data processing unit is connected with the input end of the data transmission storage unit; and a second output end of the digital processing unit is connected with the network port chip and uploaded to the upper computer. The utility model provides the signal processing ability of ACARS system has been promoted, signal processing module's circuit structure is simplified, reduces volume and consumption, but not excessively occupies the resource.

Description

ACARS signal processing system

Technical Field

The utility model relates to a signal processing field, concretely relates to ACARS signal processing system.

Background

The ACARS system is an aircraft communication addressing and reporting system, has an important role in transmitting aircraft identity information, and is mainly used for radio communication between an aircraft and a ground base station. The signal processing of the traditional ACARS system adopts two modes, one mode is to demodulate a baseband signal by an analog mode and decode the baseband signal by a PC, which brings a great cost and needs more frequency conversion stages (frequency conversion times), resulting in a complex circuit and difficult debugging. The other method is to sample the analog intermediate-frequency signal by adopting the ADC and then directly process the digital intermediate-frequency signal, so that the consumption of resources of a post-processing unit is large, and great pressure is brought to the processing capacity of a post-digital signal processing device.

Digital Down Conversion (DDC) is a key technology in the field of communications detection, which reduces or removes the carrier frequency of a signal by spectrum shifting, filters and decimates the signal by a decimation filter to match the rate requirements of the subsequent receiving end. DDC is widely used in the fields of software radio, ultra-wideband radar, and the like. The principle is that an input digital intermediate frequency signal passes through a mixer formed by two multipliers, a digital control oscillator simultaneously generates two paths of orthogonal local oscillation signals, and the two paths of orthogonal local oscillation signals are multiplied to respectively obtain two paths of Q and I signals. Then, the digital baseband signal is output by performing decimation by a filter of the subsequent stage, which has an advantage of reducing the data rate.

SUMMERY OF THE UTILITY MODEL

To the above-mentioned not enough among the prior art, the utility model provides a pair of ACARS signal processing system has solved that current ACARS system circuit is complicated, the big problem of post processing unit consumption resource.

In order to achieve the purpose of the invention, the utility model adopts the technical scheme that: an ACARS signal processing system comprises an ADC signal acquisition unit, a data transmission storage unit, a data processing unit and a power supply control unit; a first input end of the ADC signal acquisition unit collects intermediate frequency radio frequency signals; the output end of the ADC signal acquisition unit is connected with the first input end of the data processing unit; the first output end of the power supply control unit is connected with the second input end of the ADC signal acquisition unit; the second output end of the power supply control unit is connected with the second input end of the data processing unit; the output end of the data processing unit is connected with the input end of the data transmission storage unit;

the data processing unit comprises an FPGA signal processing unit and a DSP signal processing unit; the FPGA processing unit comprises a digital down-conversion processing and digital signal modulation and demodulation unit;

the digital down-conversion processing unit comprises a digital oscillator NCO, two frequency mixing units, two CIC filters and two FIR filters; the first output end of the NCO is connected with the second input end of the first frequency mixing unit; the output end of the first frequency mixing unit is connected with the input end of the first CIC filter; the output end of the first CIC filter is connected with the input end of the first FIR filter; the output end of the first FIR filter outputs a baseband signal I; the second output end of the NCO is connected with the second input end of the second frequency mixing unit; the output end of the second frequency mixing unit is connected with the input end of the second CIC filter; the output end of the second CIC filter is connected with the input end of the second FIR filter; the output end of the FIR filter outputs a baseband signal Q; the first input end of the first frequency mixing unit and the first input end of the second frequency mixing unit are used as the input ends of the digital down-conversion processing unit;

the first output end of the digital down-conversion processing unit is connected with the first input end of the digital signal modulation and demodulation unit; the second output end of the digital down-conversion processing unit is connected with the second input end of the digital signal modulation and demodulation unit; the output end of the digital signal modulation and demodulation unit is connected with the DSP signal processing unit; the DSP signal processing unit is used as an input end of the data processing unit.

The beneficial effects of the utility model are that: the signal processing capability of the ACARS system is improved, the circuit structure of the signal processing module is simplified, the volume and the power consumption are reduced, the design is simple and convenient, and excessive resource occupation is not needed; the intermediate frequency digital signal is converted into a low frequency digital signal, so that the difficulty of subsequent signal modulation and demodulation and other processing can be reduced; the cost of the post signal processing device is reduced.

Drawings

FIG. 1 is a system block diagram;

FIG. 2 is a functional block diagram of a single channel demodulator;

fig. 3 is a block diagram of a digital down-conversion processing unit.

Detailed Description

The following description of the embodiments of the present invention is provided to enable those skilled in the art to understand the invention, and it is to be understood that the invention is not limited to the details of the embodiments, but rather, the invention is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined and defined by the appended claims.

As shown in fig. 1: an ACARS signal processing system comprises an ADC signal acquisition unit, a data transmission storage unit, a data processing unit and a power supply control unit; a first input end of the ADC signal acquisition unit collects intermediate frequency radio frequency signals; the output end of the ADC signal acquisition unit is connected with the first input end of the data processing unit; the first output end of the power supply control unit is connected with the second input end of the ADC signal acquisition unit; the second output end of the power supply control unit is connected with the second input end of the data processing unit; the output end of the data processing unit is connected with the input end of the data transmission storage unit;

as shown in fig. 2, the analog signal can directly output the required demodulation data through Digital Down Conversion (DDC) and baseband filtering, and the digital signal needs to be subjected to DDC digital down conversion, then to be subjected to carrier synchronization loop to correct the offset carrier in the signal, and then to be subjected to timing synchronization loop to obtain the correct timing clock of the signal, so as to obtain the correct code stream data. Thus, the output interface of each demodulator simultaneously provides the soft decision result, the hard decision result of the demodulated data and the I/Q data output by DDC, and one of the soft decision result, the hard decision result and the I/Q data is selected by a user to be output.

As shown in fig. 3, the digital down-conversion processing unit includes a digital oscillator NCO, two mixing units, two CIC filters and two FIR filters; the first output end of the NCO is connected with the second input end of the first frequency mixing unit; the output end of the first frequency mixing unit is connected with the input end of the first CIC filter; the output end of the first CIC filter is connected with the input end of the first FIR filter; the output end of the first FIR filter outputs a baseband signal I; the second output end of the NCO is connected with the second input end of the second frequency mixing unit; the output end of the second frequency mixing unit is connected with the input end of the second CIC filter; the output end of the second CIC filter is connected with the input end of the second FIR filter; the output end of the FIR filter outputs a baseband signal Q; the first input end of the first frequency mixing unit and the first input end of the second frequency mixing unit are used as the input ends of the digital down-conversion processing unit;

in an embodiment of the present invention, the ACARS signal processing operation process: sending the intermediate frequency analog signal after the radio frequency signal received by the antenna is processed by a receiving channel to an ADC analog-to-digital conversion unit, and sampling the 70MHz intermediate frequency analog signal; sending the sampled intermediate-frequency digital signal into an FPGA, performing down-conversion processing inside the FPGA, mixing the intermediate-frequency digital signal with a local oscillator orthogonal signal, performing extraction filtering through a CIC extraction filter, performing filtering through an FIR filter, and finally converting into a digital baseband signal; then, the digital baseband signal after down conversion is modulated and demodulated in the FPGA; the data after modulation and demodulation is sent to a DSP unit, data decoding and the like are carried out in the DSP unit, and then the decoded data are packaged and processed and uploaded to a PC end through a network interface.

The network interface chip is 88E1111 of Alaska company, the ADC chip is AD9248-40 of AD company, the FPGA chip is XC6SLX150-2FGG484I of XILINX company, and the DSP chip is TMS320C6455 of TI company.

The utility model improves the signal processing capability of the ACARS system, simplifies the circuit structure of the signal processing module, reduces the volume and the power consumption, has simple and convenient design, and does not need to occupy resources excessively; the intermediate frequency digital signal is converted into a low frequency digital signal, so that the difficulty of subsequent signal modulation and demodulation and other processing can be reduced; the cost of the post signal processing device is reduced.

Claims (1)

1. An ACARS signal processing system is characterized by comprising an ADC signal acquisition unit, a data transmission storage unit, a data processing unit and a power supply control unit; a first input end of the ADC signal acquisition unit collects intermediate frequency radio frequency signals; the output end of the ADC signal acquisition unit is connected with the first input end of the data processing unit; the first output end of the power supply control unit is connected with the second input end of the ADC signal acquisition unit; the second output end of the power supply control unit is connected with the second input end of the data processing unit; the output end of the data processing unit is connected with the input end of the data transmission storage unit;

the data processing unit comprises an FPGA signal processing unit and a DSP signal processing unit; the FPGA processing unit comprises a digital down-conversion processing and digital signal modulation and demodulation unit;

the digital down-conversion processing unit comprises a digital oscillator NCO, two frequency mixing units, two CIC filters and two FIR filters; the first output end of the NCO is connected with the second input end of the first frequency mixing unit; the output end of the first frequency mixing unit is connected with the input end of the first CIC filter; the output end of the first CIC filter is connected with the input end of the first FIR filter; the output end of the first FIR filter outputs a baseband signal I; the second output end of the NCO is connected with the second input end of the second frequency mixing unit; the output end of the second frequency mixing unit is connected with the input end of the second CIC filter; the output end of the second CIC filter is connected with the input end of the second FIR filter; the output end of the FIR filter outputs a baseband signal Q; the first input end of the first frequency mixing unit and the first input end of the second frequency mixing unit are used as the input ends of the digital down-conversion processing unit;

the first output end of the digital down-conversion processing unit is connected with the first input end of the digital signal modulation and demodulation unit; the second output end of the digital down-conversion processing unit is connected with the second input end of the digital signal modulation and demodulation unit; the output end of the digital signal modulation and demodulation unit is connected with the DSP signal processing unit; the DSP signal processing unit is used as an input end of the data processing unit.

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