CN218514576U - Circuit board and electronic device - Google Patents
Circuit board and electronic device Download PDFInfo
- Publication number
- CN218514576U CN218514576U CN202222151385.4U CN202222151385U CN218514576U CN 218514576 U CN218514576 U CN 218514576U CN 202222151385 U CN202222151385 U CN 202222151385U CN 218514576 U CN218514576 U CN 218514576U
- Authority
- CN
- China
- Prior art keywords
- layer
- circuit
- circuit board
- dielectric layer
- metal block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
A circuit board comprises a circuit substrate, a second dielectric layer, a plurality of metal blocks and a solder mask layer. The circuit substrate comprises a first dielectric layer and a first circuit layer which are arranged in a stacked mode; a second dielectric layer connected to the first line layer and connected to a surface of the first dielectric layer exposed to the first line layer; the metal blocks are arranged at intervals, and each metal block penetrates through the second dielectric layer; the solder mask layer covers the second medium layer, and the metal blocks are exposed to the solder mask layer. The circuit board provided by the embodiment of the application is equivalent to increasing the interface for electrically connecting the circuit board and the external circuit by arranging the relatively dense metal blocks, and the operational capability and the heat dissipation capability of the circuit board can be improved. The application also provides an electronic device.
Description
Technical Field
The present application relates to the field of signal transmission technologies, and in particular, to a circuit board and an electronic device.
Background
With the development of electronic technology, users have made higher demands for high-speed/high-function operations of electronic devices. The circuit board is one of the elements that fulfill the above requirements. However, the packaging density of the circuit board is low due to the limitation of the manufacturing process of the conventional circuit board, and it is difficult to satisfy the high-speed/high-function operation.
SUMMERY OF THE UTILITY MODEL
A circuit board comprises a circuit substrate, a second dielectric layer, a plurality of metal blocks and a solder mask layer. The circuit substrate comprises a first dielectric layer and a first circuit layer which are arranged in a stacked mode; a second dielectric layer connected to the first line layer and connected to a surface of the first dielectric layer exposed to the first line layer; the plurality of metal blocks are arranged at intervals, and each metal block penetrates through the second dielectric layer; the solder mask layer covers the second medium layer, and the plurality of metal blocks are exposed to the solder mask layer.
In one possible embodiment, the minimum distance between the centers of two adjacent metal blocks is 70 μm.
In a possible implementation manner, along the direction in which the first dielectric layer and the first circuit layer are stacked, the projection of the metal block is located in the projection of the first circuit layer.
In a possible implementation manner, the circuit board further includes a second circuit layer, the second circuit layer is located on a surface of the second dielectric layer, the surface of the second dielectric layer faces away from the circuit substrate, and the solder mask layer further covers the second circuit layer.
In one possible embodiment, the first circuit layer is a multilayer, and the circuit substrate further includes a conductive via electrically connecting two adjacent first circuit layers.
In a possible embodiment, the number of layers of the second dielectric layer through which the metal block is inserted is one.
In a possible embodiment, the metal block is made of one of copper, silver and gold.
In a possible implementation manner, the second dielectric layer, the metal block and the solder mask layer are disposed on two opposite surfaces of the circuit substrate.
In a possible embodiment, the material of the second dielectric layer is Ajinomoto reinforced film.
An electronic device comprises the circuit board.
The circuit board provided by the embodiment of the application is equivalent to increasing the interface for electrically connecting the circuit board and the external circuit by arranging the relatively dense metal blocks, and the operational capability and the heat dissipation capability of the circuit board can be improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a circuit substrate according to an embodiment of the present disclosure.
Fig. 2 is a schematic flow chart illustrating a process of forming a transition structure according to an embodiment of the present application.
Fig. 3 is a schematic cross-sectional view of the circuit substrate shown in fig. 1 and the transition structure shown in fig. 2 after being laminated.
Fig. 4 is a schematic cross-sectional view of the metal block after the first transition layer shown in fig. 3 is removed and a protective layer is coated on the surface of the metal block.
Fig. 5 is a schematic cross-sectional view of the second dielectric layer shown in fig. 4 after a first plating layer is formed on the surface of the second dielectric layer.
Fig. 6 is a schematic cross-sectional view of the structure shown in fig. 5 after being coated with a dry film and exposed.
Fig. 7 is a schematic cross-sectional view of the wiring groove shown in fig. 6 after a second plating layer is formed.
Fig. 8 is a schematic cross-sectional view of the second circuit layer formed by etching the first plating layer shown in fig. 7 and the second plating layer.
FIG. 9 is a schematic cross-sectional view of a dry film-formed circuit board overlying the structure of FIG. 8.
Fig. 10 is a schematic top view of a circuit board according to some embodiments.
Description of the main elements
The following detailed description will further illustrate the present application in conjunction with the above-described figures.
Detailed Description
In order that the above objects, features and advantages of the present application can be more clearly understood, a detailed description of the present application will be given below with reference to the accompanying drawings and detailed description. In addition, the embodiments and features of the embodiments of the present application may be combined with each other without conflict. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, and the described embodiments are merely some, but not all embodiments of the present application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes all and any combination of one or more of the associated listed items.
In various embodiments of the present application, for convenience in description and not limitation, the term "coupled" as used in the specification and claims of the present application is not limited to physical or mechanical connections, either direct or indirect. "upper", "lower", "above", "below", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships are changed accordingly.
Referring to fig. 1 to 9, an embodiment of the present invention provides a method for manufacturing a circuit board 100, including the following steps:
step S1: referring to fig. 1, a circuit substrate 10 is provided, where the circuit substrate 10 includes a first dielectric layer 11 and a first circuit layer 13 stacked on each other.
The first dielectric layer 11 and/or the first circuit layer 13 may be one or more layers, and when the first circuit layer 13 is a plurality of layers, the first circuit layer 13 is disposed at intervals through the first dielectric layer 11, and the plurality of layers of the first circuit layer 13 may be electrically connected to each other. In this embodiment, the first dielectric layer 11 is a single layer, the first circuit layer 13 is two layers, and the two layers of the first circuit layer 13 are located on two opposite surfaces of the first dielectric layer 11.
The circuit substrate 10 further includes a conductive via 15, and the conductive via 15 is electrically connected to two adjacent first circuit layers 13.
The conductive hole 15 may be filled with a resin 17, and the conductive hole 15 covers the resin 17.
Step S2: referring to fig. 2, a transition structure 20 is provided, where the transition structure 20 includes a first transition layer 21, a second dielectric layer 23, and a metal block 27, the second dielectric layer 23 is located on a surface of the first transition layer 21, and the metal block 27 penetrates through the second dielectric layer 23.
The step of forming the transition structure 20 may include:
step S21: and forming a first transition layer 21 and a second transition layer 25 on the two opposite surfaces of the second medium layer 23. The first transition layer 21 and the second transition layer 25 may be made of Mylar (Mylar) film.
The second dielectric layer 23 may be an Ajinomoto reinforced film (abb), and the number of layers of the ABF is one.
Step S22: a plurality of blind holes 29 are formed through the second transition layer 25 and the second dielectric layer 23, and the surface of the second transition layer 25 is exposed to the blind holes 29.
In some embodiments, the cross section of the blind hole 29 may be stepped, that is, one end of the blind hole 29 is open and the other end is open, and the end with the large opening is located on the side of the first transition layer 21.
Step S23: the blind hole 29 is filled with a metal block 27, and the metal block 27 is connected with the surface of the first transition layer 21.
Step S24: and removing the second transition layer 25 and removing a part of each metal block 27, so that the surface of the metal block 27, which faces away from the first transition layer 21, is on the same plane as the surface of the second dielectric layer 23.
The metal block 27 includes a first surface 271 and a second surface 273, which are oppositely disposed, the first surface 271 is connected to the first transition layer 21, and the second surface 273 is exposed to the second dielectric layer 23 and is on the same plane as a surface of the second dielectric layer 23 facing away from the first transition layer 21.
In the process of forming the blind via 29 in this embodiment, only the plurality of blind vias 29 need to be formed on the second transition layer 25 and the second dielectric layer 23 without the circuit layer, and there is no other circuit fabrication after the blind via 29 is filled with the metal block 27, and there is no other limitation on the process of forming the blind via 29, so that the relatively dense blind vias 29 can be formed, and the relatively dense metal block 27 is formed on the second dielectric layer 23.
And step S3: referring to fig. 3, the transition structure 20 is pressed on at least one surface of the circuit substrate 10, the metal block 27 is connected to the first circuit layer 13, and the first transition layer 21 is removed to expose the metal block 27 and the surface of the second dielectric layer 23.
Specifically, the side of the transition structure 20 having the metal block 27 is pressed toward the circuit substrate 10, so as to connect the second surface 273 with the first circuit layer 13.
During the pressing process, two heating stages may be included. In the first heating stage, hot pressing is carried out at a lower temperature to tear off the first transition layer 21, and after the first transition layer 21 is torn off, the first surface 271 of the metal block 27 is exposed to the second medium layer 23; the second heating stage is performed until the glass transition temperature (Tg) of the second dielectric layer 23 is reached, and the second dielectric layer 23 is softened and then connected to the first wiring layer 13 and to the surface of the first dielectric layer 11 exposed to the first wiring layer 13. In the present embodiment, the two opposite surfaces of the circuit substrate 10 are pressed together to form the second dielectric layer 23 and the metal block 27 penetrating through the second dielectric layer 23.
Along the direction in which the first dielectric layer 11 and the first circuit layer 13 are stacked, the projection of the metal block 27 is located in the projection of the first circuit layer 13, that is, the width of the first circuit layer 13 directly connected to the metal block 27 is greater than the width of the metal block 27 correspondingly connected to the first circuit layer, so that when the transition structure 20 is pressed against the circuit substrate 10, the metal block 27 is conveniently connected to the first circuit layer 13, and thus the reliability of electrical connection between the metal block 27 and the first circuit layer 13 is increased.
And step S4: referring to fig. 4, a protective layer 30 is covered on the surface of the metal block 27.
The first surface 271 of the metal block 27 is covered with a protective layer 30 to shield the surface of the metal block 27.
Step S5: referring to fig. 5, copper is formed on the surface of the second dielectric layer 23 to form a first plating layer 41, and the passivation layer 30 is exposed on the first plating layer 41.
Step S6: referring to fig. 6, the surface of the first plating layer 41 is covered with a dry film 50 and then exposed to form a wiring groove 51.
The exposed dry film 50 covers the protection layer 30, and the surface of the first plating layer 41 is exposed to the wiring groove 51.
Step S7: referring to fig. 7, a second plating layer 43 is formed in the wiring groove 51.
The second plating layer 43 is connected to the first plating layer 41 exposed to the wiring groove 51.
Step S8: referring to fig. 8, the dry film 50 and the passivation layer 30 are removed, and a portion of the first plating layer 41 is etched to form a second circuit layer 40.
The metal block 27 and the second circuit layer 40 are not directly connected.
Step S9: referring to fig. 9, a solder mask layer 60 is formed, thereby obtaining a circuit board 100.
The solder mask layer 60 covers the second circuit layer 40 and the second dielectric layer 23, the metal block 27 is exposed to the solder mask layer 60, and the metal block 27 can be used for electrically connecting with an external circuit.
Before the step of forming the solder mask layer 60, a step of forming conductive holes (not shown) may be further included to electrically connect the second circuit layer 40 with the first circuit layer 13.
Referring to fig. 9, an embodiment of the present application further provides a circuit board 100, where the circuit board 100 can be manufactured by the above-mentioned manufacturing method. The circuit board 100 includes a circuit substrate 10, a second dielectric layer 23, a plurality of metal blocks 27, and a solder mask layer 60.
The circuit substrate 10 includes a first dielectric layer 11 and a first circuit layer 13 stacked together. The first dielectric layer 11 and/or the first wiring layer 13 may be one or more layers.
When the first circuit layer 13 is a multilayer, the circuit substrate 10 may further include a conductive via 15, where the conductive via 15 penetrates through the first dielectric layer 11 and connects two adjacent first circuit layers 13.
The second dielectric layer 23 covers at least one surface of the circuit substrate 10, and the second dielectric layer 23 is connected to the first circuit layer 13 and is connected to the surface of the first dielectric layer 11 exposed to the first circuit layer 13.
A plurality of metal blocks 27 are arranged at intervals, and each metal block 27 penetrates through the second dielectric layer 23. Each metal block 27 includes a first surface 271 and a second surface 273 which are opposite to each other, the second surface 273 is connected to the first circuit layer 13, the first surface 271 is exposed to the solder mask layer 60, and the first surface 271 exposed to the solder mask layer 60 can be used for electrically connecting with an external circuit.
The material of the metal block 27 may be one selected from copper, silver, and gold.
The distance between the centers of two adjacent metal blocks 27 may be smaller than that in the related art. Referring to fig. 10, in the present embodiment, the minimum distance D between the centers of two adjacent metal blocks 27 may be 70 μm.
In the related art, due to the process, the lamination of the multiple second dielectric layers 23 may form a small gap between the layers, and when the two adjacent metal blocks 27 are close, a Conductive Anode Filament (CAF) penetrating through the second dielectric layer 23 may be formed between the two adjacent metal blocks 27 to cause a micro short circuit phenomenon. In the embodiment of the present invention, the number of the second dielectric layers 23 is one, which is equivalent to that a plurality of metal blocks 27 are disposed through one of the second dielectric layers 23, and a gap is not formed in one of the second dielectric layers 23 due to the pressing process, thereby preventing or reducing the possibility of generating an electrical anode wire.
The circuit board 100 may further include a second circuit layer 40, the second circuit layer 40 is located on a surface of the second dielectric layer 23 facing away from the circuit substrate 10, the solder mask layer 60 further covers the second circuit layer 40, and the second circuit layer 40 may be electrically connected to the first circuit layer 13 through a conductive hole.
The present application further provides an electronic device (not shown), which includes the circuit board 100, wherein the metal block 27 exposed on the solder mask layer 60 in the circuit board 100 is electrically connected to an external circuit as an interface of the circuit board 100 for electrical connection. Electronic devices include, but are not limited to, cell phones, automobiles, smart watches, wearable devices, and the like.
The circuit board 100 provided in the embodiment of the present application, by arranging the relatively dense metal blocks 27, is equivalent to increasing the interface for electrically connecting the circuit board 100 with an external circuit, and can improve the operational capability and the heat dissipation capability of the circuit board 100.
Although the present application has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the present application.
Claims (10)
1. A circuit board, comprising:
the circuit substrate comprises a first dielectric layer and a first circuit layer which are arranged in a stacked mode;
a second dielectric layer connected to the first line layer and connected to a surface of the first dielectric layer exposed to the first line layer;
the metal blocks are arranged at intervals, and each metal block penetrates through the second dielectric layer; and
and the solder mask layer covers the second medium layer, and the plurality of metal blocks are exposed to the solder mask layer.
2. The circuit board of claim 1, wherein the minimum distance between the centers of two adjacent metal blocks is 70 μm.
3. The circuit board of claim 1, wherein a projection of the metal block is located in a projection of the first circuit layer along a direction in which the first dielectric layer and the first circuit layer are stacked.
4. The circuit board of claim 1, further comprising a second circuit layer on a surface of the second dielectric layer facing away from the circuit substrate, wherein the solder mask layer further covers the second circuit layer.
5. The circuit board of claim 1, wherein the first circuit layers are multi-layered, and the circuit substrate further comprises conductive vias electrically connecting two adjacent first circuit layers.
6. The circuit board of claim 1, wherein the number of layers of the second dielectric layer through which the metal block is disposed is one.
7. The circuit board of claim 1, wherein the metal block is made of one of copper, silver and gold.
8. The circuit board of claim 1, wherein the second dielectric layer, the metal block and the solder mask layer are disposed on two opposite surfaces of the circuit substrate.
9. The circuit board of claim 1, wherein the second dielectric layer is an Ajinomoto enhancement film.
10. An electronic device, characterized in that the electronic device comprises a circuit board according to any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222151385.4U CN218514576U (en) | 2022-08-16 | 2022-08-16 | Circuit board and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222151385.4U CN218514576U (en) | 2022-08-16 | 2022-08-16 | Circuit board and electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218514576U true CN218514576U (en) | 2023-02-21 |
Family
ID=85209858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222151385.4U Active CN218514576U (en) | 2022-08-16 | 2022-08-16 | Circuit board and electronic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218514576U (en) |
-
2022
- 2022-08-16 CN CN202222151385.4U patent/CN218514576U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4767269B2 (en) | Method for manufacturing printed circuit board | |
| JP4558776B2 (en) | Circuit board manufacturing method | |
| CN103458628B (en) | Multilayer circuit board and making method thereof | |
| US20220254695A1 (en) | Embedded package structure and preparation method therefor, and terminal | |
| KR20010020468A (en) | Sequentially built integrated circuit package | |
| CA2329441A1 (en) | Laminated integrated circuit package | |
| CN101409238A (en) | Method for preparing seedless layer package substrate | |
| US6787896B1 (en) | Semiconductor die package with increased thermal conduction | |
| US11699671B2 (en) | Packaged circuit structure including circuit strcutre with antenna | |
| TWI712346B (en) | Multilayer circuit board and method of manufacturing the same | |
| KR100857165B1 (en) | Method for manufacturing circuit board | |
| US20200305289A1 (en) | Flexible substrate and method for fabricating the same | |
| CN105470144A (en) | Coreless layer packaging substrate and manufacturing method thereof | |
| US6432748B1 (en) | Substrate structure for semiconductor package and manufacturing method thereof | |
| CN218514576U (en) | Circuit board and electronic device | |
| KR101985234B1 (en) | Printed circuit board for semiconductor package and method of manufacturing the same | |
| US6853065B2 (en) | Tab tape, method of making same and semiconductor device | |
| KR20150043135A (en) | printed circuit board which includes metal layer and semiconductor package including the same | |
| CN101393903A (en) | Bearing board construction embedded with chip and fabrication method thereof | |
| US7642571B2 (en) | Substrate core | |
| JP2002335059A (en) | Wiring substrate and its manufacturing method | |
| CN113675158A (en) | Circulating cooling embedded packaging substrate and manufacturing method thereof | |
| CN113707638A (en) | Substrate structure and method for fabricating the same | |
| CN219876259U (en) | Multi-layer board circuit board with heat dissipation function | |
| US20240021525A1 (en) | Packaging structure for realizing chip interconnection and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |