CN218450073U

CN218450073U - Level detector, peak detection circuit and burst mode trans-impedance amplifier

Info

Publication number: CN218450073U
Application number: CN202222246134.4U
Authority: CN
Inventors: 向欣
Original assignee: Wuhan Yunling Photoelectric Co ltd
Current assignee: Wuhan Yunling Optoelectronics Co ltd
Priority date: 2022-08-25
Filing date: 2022-08-25
Publication date: 2023-02-03
Anticipated expiration: 2032-08-25

Abstract

The utility model discloses a level detector, peak detection circuit and burst mode transimpedance amplifier, level detector include amplifier and wave filter, and the amplifier has two inputs and an output, and the first input of amplifier is used for receiving voltage signal Vin, and the second input of amplifier is used for receiving first reference voltage signal Vref1, and the output of amplifier is connected with the input of wave filter, and the output of wave filter is level detector's output. The peak detection circuit comprises a comparator and a level detector, wherein the output end of the level detector is connected with the first input end of the comparator, the second input end of the comparator is connected with the output end of a reference voltage generator, and the output end of the comparator is the output end of the peak detection circuit. The peak detection circuit provides a relatively large and stable tracking voltage with small ripple by using a low pass filter and an amplifier instead of a rectifier. And the power consumption is low, the response time is short, and the rapid burst level detection capability is realized.

Description

Level detector, peak detection circuit and burst mode trans-impedance amplifier

Technical Field

The utility model belongs to the technical field of optical communication, concretely relates to level detector, peak detection circuit and burst mode transimpedance amplifier.

Background

In recent years, data rates in optical communication systems have increased dramatically in order to meet the demands of various emerging multimedia services. Fig. 1 shows a typical point-to-multipoint Time Division Multiplexing (TDM) PON system. Several Optical Network Units (ONUs) share an Optical Line Terminal (OLT) through a passive optical splitter. In this system, a transmission packet from the OLT has a constant signal level, and on the other hand, a signal received at the OLT side has a series of burst data packets with varying signal levels due to different distances and path losses between the ONUs and the OLT. In this optical system, in order to track a received burst mode signal and then appropriately restore the continuous power level of the signal, a burst mode transimpedance amplifier (BM-TIA) is a basic component widely used on the OLT side. In particular, fast response time is one of the important specifications of BM-TIA in order to meet the current XG/XGSPON system requirements or to increase the transmission capacity and improve the performance of the entire PON system. There are a variety of peak detection circuit configurations that detect pulse power levels quickly, however, these circuit configurations exhibit high power consumption to overcome the slow peak detection characteristic, since these are based on rectifier designs, and therefore have high power consumption.

The usual design is to use a rectifier to track the peak level of the signal, so the peak detection circuit (or called peak hold circuit and top hold circuit) designed in BM-TIA mainly uses a rectifier with a rectifying diode and a holding capacitor element. However, although this topology provides the exact highest level, it takes a long time to find the peak level of the signal if high currents are not used, because of the frequency characteristics of the diodes used. In fact, rectifiers with rf diode elements track faster than rectifiers with analog diodes. Similarly, diode-connected BJTs or MOS transistors have similar bandwidths. This means that these kinds of peak detection circuits have slow peak tracking characteristics because the charging capability is relatively poor and a slow charging time is obtained. This architecture is suitable for PON systems that require slow response times in excess of 100ns, but the need for fast response times or high data throughput for more challenging PON systems is more carefully considered. Rectifier-based peak detection circuits do not have fast peak detection capability due to the narrow bandwidth characteristics. In addition, the parasitic capacitance of the rectifying diode interferes with the rectification of the signal, so the hold-charge current on the load capacitance can be discharged back through the parasitic capacitance for high frequency clocks. The peak detection circuit causes the diode to lose rectification capability due to its parasitic capacitance. Finally, the final detection voltage of these peak detection circuits does not approach the peak amplitude of the clock signal, but only reaches half the peak value, due to the integrator-like charging and discharging. Since the detected peak is small and long, it is difficult for the input burst signal to distinguish between large bursts and soft bursts. Therefore, the peak detection circuit should be designed to increase the relative discrimination capability compared to the reference threshold level to avoid burst detection errors.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to overcome a defect among the prior art at least, provide a level detector, peak detection circuit and burst mode transimpedance amplifier, its consumption is lower, and response time is shorter, has quick proruption level detection ability etc..

The technical scheme of the utility model is realized like this: the utility model discloses a level detector, including amplifier and wave filter, the amplifier has two inputs and an output, and the first input of amplifier is used for receiving voltage signal Vin, and the second input of amplifier is used for receiving first reference voltage signal Vref1, and the output of amplifier is connected with the input of wave filter, the output of wave filter is level detector's output.

Further, the amplifier comprises a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor, wherein a gate of the first MOS transistor is a first input end of the amplifier, a source of the first MOS transistor is grounded, a drain of the first MOS transistor is respectively connected with a drain of the third MOS transistor, a gate of the third MOS transistor and a gate of the fourth MOS transistor, a source of the third MOS transistor is connected with a voltage VDD, a source of the fourth MOS transistor is connected with a voltage VDD, a drain of the fourth MOS transistor is an output end of the amplifier, a drain of the fourth MOS transistor is connected with one end of a resistor R1, the other end of the resistor R1 is connected with a drain of the second MOS transistor, a source of the second MOS transistor is grounded, and a gate of the second MOS transistor is a second input end of the amplifier.

Furthermore, the filter adopts a low-pass filter and comprises a resistor Rf and a capacitor Cf, one end of the resistor Rf is connected with the output end of the amplifier, the other end of the resistor Rf is respectively connected with one end of the capacitor Cf and the first input end of the comparator, and the other end of the capacitor Cf is grounded.

The utility model discloses a peak detection circuit, including the comparator and as above level detector, level detector's output is connected with the first input of comparator, the second input of comparator is connected with reference voltage generator's output, the output of comparator is peak detection circuit's output.

Further, the utility model discloses a peak detection circuit still includes the SR latch, the first input of SR latch is connected with the output of comparator, the second input of SR latch is used for receiving the RESET signal, the output of SR latch is peak detection circuit's output.

Further, the reference voltage generator includes a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor, a gate of the fifth MOS transistor is a first input terminal of the reference voltage generator and is configured to receive a first reference voltage signal Vref1, a source of the fifth MOS transistor is grounded, a drain of the fifth MOS transistor is an output terminal of the reference voltage generator and is configured to output a second reference voltage signal Vref2, a gate of the sixth MOS transistor is a second input terminal of the reference voltage generator and is configured to receive the first reference voltage signal Vref1, a source of the sixth MOS transistor is grounded, a drain of the sixth MOS transistor is connected to a drain of the eighth MOS transistor, a gate of the eighth MOS transistor, and a gate of the seventh MOS transistor, a source of the eighth MOS transistor is connected to the voltage VDD, a source of the seventh MOS transistor is connected to the voltage VDD, a drain of the seventh MOS transistor is connected to one end of the resistor R2, and another end of the resistor R2 is connected to a drain of the fifth MOS transistor.

The utility model discloses a burst mode transimpedance amplifier, including voltage input circuit and as above peak detection circuit, voltage input circuit is used for responding to the light signal, and will the light signal converts voltage signal into, peak detection circuit's first input is connected with voltage input circuit's output for receive voltage signal Vin, peak detection circuit's second input is connected with threshold voltage production circuit's output, is used for receiving first reference voltage signal Vref1, peak detection circuit's output is connected with voltage input circuit, threshold voltage production circuit's control end respectively.

Further, the voltage input circuit includes a photodiode and a TIA core amplifier, the photodiode is configured to receive a light signal and convert the light signal into a voltage signal, the TIA core amplifier is configured to receive the voltage signal output by the photodiode and output a voltage signal Vin, and an output terminal of the peak detection circuit is connected to a control terminal of the TIA core amplifier and configured to change a gain mode of the TIA core amplifier rapidly.

Further, the threshold voltage generating circuit adopts a virtual TIA and is used for generating a threshold voltage Vref1, and an output end of the peak value detecting circuit is connected with a control end of the virtual TIA and is used for changing a gain mode of the virtual TIA.

Further, the utility model discloses a burst mode transimpedance amplifier still includes single-ended to differential circuit, single-ended to differential circuit's input is connected with voltage input circuit's output for receive the voltage signal Vin of voltage input circuit output, and convert single signal into differential output.

Furthermore, an automatic maladjustment eliminating circuit and an output buffer are sequentially connected in series between the two output ends of the single-end to differential circuit and the two output ends of the mode-generating trans-impedance amplifier.

The utility model discloses following beneficial effect has at least: the utility model discloses a peak detection circuit provides voltage gain and integrator characteristic to trail the peak level safely through this filtering.

The utility model discloses a peak detection circuit provides the relatively big and stable tracking voltage who has little ripple.

The utility model discloses a peak detection circuit consumption is lower, and response time is shorter, has quick proruption level detectability.

Drawings

In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the drawings used in the description of the embodiments or the prior art will be briefly introduced, obviously, the drawings in the description below are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a typical point-to-multipoint Time Division Multiplexing (TDM) PON system;

fig. 2 is a circuit diagram of a peak detection circuit according to an embodiment of the present invention;

fig. 3 is a schematic block diagram of a burst-mode transimpedance amplifier according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

Applicants have discovered that a method of quickly tracking the peak level of the high speed preamble signal is to not use a rectifier configured with rectifier diodes. Since the rectifier does not work well at high frequencies due to parasitic capacitance, it is possible to provide a wide bandwidth, high frequency characteristics, and high resolution by using only a suitable Low Pass Filter (LPF) and amplifier instead thereof. Therefore, a level detector and a peak detection circuit as shown in fig. 2 are proposed.

Example one

Referring to fig. 2, an embodiment of the present invention provides a level detector, including an amplifier and a filter, the amplifier has two inputs and an output, the first input of the amplifier is used for receiving a voltage signal Vin, the second input of the amplifier is used for receiving a first reference voltage signal Vref1, the output of the amplifier is connected to the input of the filter, and the output of the filter is the output of the level detector.

Further, the amplifier comprises a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube, a gate of the first MOS tube is a first input end of the amplifier, a source of the first MOS tube is grounded, a drain of the first MOS tube is connected with a drain of the third MOS tube, a gate of the third MOS tube and a gate of the fourth MOS tube respectively, a source of the third MOS tube is connected with a voltage VDD, a source of the fourth MOS tube is connected with the voltage VDD, a drain of the fourth MOS tube is an output end of the amplifier, a drain of the fourth MOS tube is connected with one end of a resistor R1, the other end of the resistor R1 is connected with a drain of the second MOS tube, a source of the second MOS tube is grounded, and a gate of the second MOS tube is a second input end of the amplifier.

Example two

Referring to fig. 2, an embodiment of the present invention discloses a peak detection circuit, including a comparator and a level detector as in the first embodiment, an output of the level detector is connected to a first input terminal of the comparator, a second input terminal of the comparator is connected to an output terminal of a reference voltage generator, and an output terminal of the comparator is an output terminal of the peak detection circuit.

An SR latch is a pulsed level sensitive memory cell circuit that can change state at a particular input pulse level. Latching is the temporary storage of signals to maintain a certain level state. The latch is mainly used for caching, then completing the problem of asynchronism between a high-speed controller and a slow-speed peripheral, then solving the problem of driving, and finally solving the problem that one I/O port can output and input. Latches are inputs that control data using levels and include latches without enable control and latches with enable control.

The purpose of setting the latches is to: the signals have timing sequences and need to be synchronized for processing. The delay of the clock signal on each flip-flop is not consistent because of the different paths the clock signal takes to reach each flip-flop, reset is provided by an external circuit, the reset signal is input when needed, and the Vpeak _ D level is maintained when not needed.

The reference voltage is a fixed comparison value, and is used for performing feedback comparison with the dynamic actual value and then outputting a comparison result. DummyTIA is used to generate a voltage reference point Vref1 required by Automatic Gain Control (AGC), and then filtering is performed to output Vref2.

The novel peak detection circuit of fig. 2 includes a level detector for amplifying and tracking the signal level, a reference voltage generator for providing a differentiated level voltage, and a comparator and SR latch for outputting a 1-bit result of the pulse signal state (strong or weak). The level detector is composed of an RCLPF (low pass filter) and an amplifier. The RC-LPF with a bandwidth of about 100MHz is not a rectifier but a single-pole filter like a signal integrator. The amplifier has differential input and single output, amplifies the output signal of the TIA core, and converts the input current after the Photodiode (PD) into voltage. In addition, it has a unipolar frequency characteristic having a bandwidth slightly wider than that of the RC-LPF, so that the combination of the two parts of the RCLPF (part of the resistor Rf and the capacitor Cf) and the amplifier (MOSFETs and R1) shown on the left side of fig. 2 provides a voltage gain and an integrator characteristic to track the peak level safely by the filtering. To the right of fig. 2 is the transient result for each block associated with that state. When the burst preamble signal is input, the RC-LPF outputs an average tracking voltage of half the input amplitude as a peak detector, but the output is very small as an absolute value compared to a reference in a noise environment. Next, the amplifier outputs a relatively amplified tracking voltage, but there is a large ripple to interrupt discrimination. Finally, the proposed combined circuit comprising two parts, RCLPF (part consisting of the resistor Rf and the capacitor Cf) and the amplifier (MOSFET and R1), provides a relatively large and stable tracking voltage with small ripple.

EXAMPLE III

The whole BM-TIA block diagram is constructed by using the peak detection circuit of the second embodiment, as shown in FIG. 3. The embodiment of the utility model discloses burst mode transimpedance amplifier who contains low-power consumption peak detection circuit, include voltage input circuit and as embodiment two peak detection circuit, voltage input circuit is used for responding to the light signal, and will light signal converts voltage signal into, peak detection circuit's first input is connected with voltage input circuit's output for receive voltage signal Vin, peak detection circuit's second input and threshold voltage produce the output of circuit and be connected, be used for receiving first reference voltage signal Vref1, peak detection circuit's output is connected with voltage input circuit, threshold voltage produce the control end of circuit respectively.

Further, the threshold voltage generating circuit adopts a virtual TIA (which is equivalent to a TIA core) for generating the threshold voltage Vref1, and an output end of the peak value detecting circuit is connected with a control end of the virtual TIA for changing a gain mode of the virtual TIA. The threshold voltage Vref1 is determined by practical application.

Further, the utility model discloses a burst mode transimpedance amplifier still includes single-ended to differential circuit (S2D), the input of single-ended to differential circuit is connected with voltage input circuit' S output for receive the voltage signal Vin of voltage input circuit output, and convert single signal into differential output.

Furthermore, a first automatic offset cancellation circuit (AOC), a second automatic offset cancellation circuit (AOC) and an output buffer are sequentially connected in series between the two output ends of the single-ended to differential circuit and the two output ends of the transmit-mode transimpedance amplifier. The two AOCs are to better eliminate input signal offset caused by DC level variations.

The utility model discloses a burst mode transimpedance amplifier's theory of operation does: after the TIA core performs current-to-voltage conversion, S2D converts the single signal into a differential pair based on a reference common mode voltage (Vref 1) to achieve better common mode noise rejection and wider linear signal swing. Two AOCs and output buffers are used to eliminate input offset caused by DC level variations. A signal level detector in the BM-TIA receives an output (Vin) of the TIA core and an output (Vref 1) of the virtual TIA core and then outputs a 1-bit detection value (VpeakD) for rapidly changing gain modes (high or low) of the TIA core and the virtual TIA core.

To widen the dynamic range, vpeakD of the signal level detector in this circuit may be 2-bit or higher.

The utility model discloses with the IC direct welding of design to test PCB to install PD equivalent circuit and output matching element above that, in order to carry out electrical test. For a 10Gb/s burst preamble input, the designed IC exhibits a fast response of 25 ns. In this case, the power consumption of the chip under the power supply of 3.3V is only about 110 mW. According to the above results, the utility model discloses a scheme low power dissipation is obviously superior to prior art. The utility model discloses use RC-LPF to replace the broadband of rectifier, use two the same amplifiers to increase the resolution ratio of detected signal to and provide the bipolar effect of stable signal suppression through this kind of combination. These allow fast burst level detection with little dependence on temperature and process variations. In addition, its simple configuration allows a small layout area and reliable stable performance. Experimental results show that these techniques are suitable for improving response time.

The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A level detector, characterized by: the voltage level detector comprises an amplifier and a filter, wherein the amplifier is provided with two input ends and an output end, the first input end of the amplifier is used for receiving a voltage signal Vin, the second input end of the amplifier is used for receiving a first reference voltage signal Vref1, the output end of the amplifier is connected with the input end of the filter, and the output end of the filter is the output end of the level detector.

2. The level detector of claim 1, wherein: the amplifier comprises a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube, wherein the grid electrode of the first MOS tube is a first input end of the amplifier, the source electrode of the first MOS tube is grounded, the drain electrode of the first MOS tube is respectively connected with the drain electrode of the third MOS tube, the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube, the source electrode of the third MOS tube is connected with a voltage VDD, the source electrode of the fourth MOS tube is connected with the voltage VDD, the drain electrode of the fourth MOS tube is an output end of the amplifier, the drain electrode of the fourth MOS tube is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the drain electrode of the second MOS tube, the source electrode of the second MOS tube is grounded, and the grid electrode of the second MOS tube is a second input end of the amplifier.

3. The level detector of claim 1, wherein: the filter adopts a low-pass filter and comprises a resistor Rf and a capacitor Cf, one end of the resistor Rf is connected with the output end of the amplifier, the other end of the resistor Rf is respectively connected with one end of the capacitor Cf and the first input end of the comparator, and the other end of the capacitor Cf is grounded.

4. A peak detection circuit, characterized by: comprising a comparator and a level detector as claimed in any one of claims 1 to 3, an output of the level detector being connected to a first input of the comparator, a second input of the comparator being connected to an output of the reference voltage generator, an output of the comparator being an output of the peak detection circuit.

5. A peak detection circuit as set out in claim 4, wherein: the peak detection circuit further comprises an SR latch, wherein a first input end of the SR latch is connected with an output end of the comparator, a second input end of the SR latch is used for receiving a RESET signal, and an output end of the SR latch is an output end of the peak detection circuit.

6. A peak detection circuit as set out in claim 4, wherein: the reference voltage generator comprises a fifth MOS tube, a sixth MOS tube, a seventh MOS tube and an eighth MOS tube, wherein the grid electrode of the fifth MOS tube is a first input end of the reference voltage generator and is used for receiving a first reference voltage signal Vref1, the source electrode of the fifth MOS tube is grounded, the drain electrode of the fifth MOS tube is an output end of the reference voltage generator and is used for outputting a second reference voltage signal Vref2, the grid electrode of the sixth MOS tube is a second input end of the reference voltage generator and is used for receiving the first reference voltage signal Vref1, the source electrode of the sixth MOS tube is grounded, the drain electrode of the sixth MOS tube is respectively connected with the drain electrode of the eighth MOS tube, the grid electrode of the eighth MOS tube and the grid electrode of the seventh MOS tube, the source electrode of the eighth MOS tube is connected with a voltage VDD, the source electrode of the seventh MOS tube is connected with the voltage VDD, the drain electrode of the seventh MOS tube is connected with one end of a resistor R2, and the other end of the resistor R2 is connected with the drain electrode of the fifth MOS tube.

7. A burst mode transimpedance amplifier characterized by: comprising a voltage input circuit and a peak detection circuit according to any of claims 4 to 6, the voltage input circuit being adapted to sense an optical signal and convert the optical signal into a voltage signal, a first input of the peak detection circuit being coupled to an output of the voltage input circuit for receiving a voltage signal Vin, a second input of the peak detection circuit being coupled to an output of the threshold voltage generation circuit for receiving a first reference voltage signal Vref1, and outputs of the peak detection circuit being coupled to respective control terminals of the voltage input circuit and the threshold voltage generation circuit.

8. The burst-mode transimpedance amplifier according to claim 7, characterized in that: the voltage input circuit comprises a photodiode and a TIA kernel amplifier, the photodiode is used for receiving a light signal and converting the light signal into a voltage signal, the TIA kernel amplifier is used for receiving the voltage signal output by the photodiode and outputting a voltage signal Vin, and the output end of the peak value detection circuit is connected with the control end of the TIA kernel amplifier and used for rapidly changing the gain mode of the TIA kernel amplifier; the threshold voltage generating circuit adopts a virtual TIA and is used for generating a threshold voltage Vref1, and the output end of the peak value detecting circuit is connected with the control end of the virtual TIA and is used for changing the gain mode of the virtual TIA.

9. The burst-mode transimpedance amplifier according to claim 7, characterized in that: the voltage conversion circuit comprises a voltage input circuit, a single-ended to differential circuit and a single-ended to differential circuit, wherein the input end of the single-ended to differential circuit is connected with the output end of the voltage input circuit and is used for receiving a voltage signal Vin output by the voltage input circuit and converting a single signal into differential output.

10. The burst-mode transimpedance amplifier according to claim 9, characterized by: an automatic maladjustment eliminating circuit and an output buffer are sequentially connected in series between the two output ends of the single-end to differential circuit and the two output ends of the mode trans-impedance amplifier.