JPH08293838A - Digital optical receiving circuit - Google Patents

Abstract

PURPOSE: To provide a digital optical receiving circuit where the duty change of an output waveform and signal amplitude deterioration owing to the offsetting of an input signal are eliminated. CONSTITUTION: A signal from a photoelectric conversion element 1 is amplified to a prescribed level by the preamplifier 3 of differential output. It becomes a positive-phase signal and an opposite-phase signal and they are inputted to an ATC circuit 5. In the ATC circuit 5, they are held by the peak holding circuits 51 and 52 of the respective signals and the values are added to the positive-phase signal and the opposite-phase signal by adders 57 and 58. The signals are discriminated between logic '1' and '0' by a comparator 7. The positive-phase output of the preamplifier 3 is inputted to a self resetting circuit 9. A level detector 91 detects the arrival of the signal from the preamplifier 3. A reset pulse generator 92 generates the reset signal of a single pulse by using the detection output. A resetting circuit 93 discharges the holding capacitance of the peak holding circuit 52 by using the reset signal.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital optical receiver circuit. In particular, passive optical networks (PON: Passiv)
e Optical Network) The present invention relates to a digital optical receiver circuit applicable to burst signal transmission in an optical transmission system, an optical Ethernet communication system or the like.

[0001]

2. Description of the Related Art Generally, in a PON optical transmission system or the like,
The signal transmitted through the transmission path becomes a burst signal. Therefore, a DC coupling type optical receiver is used as an optical receiver for receiving an arbitrary signal pattern. A conventional DC coupling type optical receiving circuit is, for example, Japanese Patent Application No. 6-217404.
(Applied on September 12, 1994) Some are described.

Generally, when an optical signal having a certain offset is input, a current is applied to the photoelectric conversion element in a direction of eliminating the offset. As a configuration in which a signal without offset is output from the photoelectric conversion element,
For example, the one described in Japanese Patent Application No. 5-227104 is known.

However, in the conventional optical receiving circuit, there are cases where a signal light waveform consisting of a state in which the light does not completely reach the zero level and a light having a predetermined level or higher is input. The signal light waveform that does not completely reach the zero level at the low level occurs when the extinction ratio deteriorates due to a bias or the like added in advance in order to reduce the emission delay of the semiconductor laser that is the transmission light source. The light emission due to the deterioration of the extinction ratio is blocked at the transmitter side at times other than the burst signal so as not to affect other burst signals.

When an optical signal waveform having an offset due to deterioration of the extinction ratio is input to the optical receiver circuit, an error occurs in the duty of the waveform. That is, generally, an optical receiving circuit captures a high level and a low level of a received optical signal and obtains an optical receiving waveform with an intermediate level between the two levels as a reference. However, when the light is not completely at the zero level at the low level, the above-mentioned reference is deviated. If the duty of the waveform is determined based on this deviated reference, the duty may be apparently detected to be large.

[0005]

However, in the former optical receiving circuit, the ATC (Automatic T
The output of the threshold level control circuit is one in which the levels of the positive-phase output signal and the negative-phase output signal are out of balance. As a result, the amplitude of the output signal output from the ATC circuit decreases, and the identification value changes. The change in the discrimination value causes the deterioration of the duty of the waveform of the output signal from the comparator.

[0006] In addition, due to the duty deterioration, especially when the received signal level is small, the data identification margin is significantly deteriorated. If there is no room for data identification, the minimum light receiving level of the receiving circuit is deteriorated.

Further, this decrease in amplitude leads to deterioration of the minimum light receiving level and a decrease in dynamic range. A decrease in dynamic range leads to a decrease in system margin.

In addition, in an optical receiver that handles burst data, a method of timing extraction is generally adopted based on information of both rising and falling edges of data in order to perform operation pull-in at high speed. . Therefore, when the duty fluctuation occurs, the jitter of the extracted clock increases and the pull-in characteristic is deteriorated.

It is an object of the present invention to provide a digital optical receiver circuit which eliminates the duty change of the output waveform and the deterioration of the signal amplitude due to the offset of the input signal.

[0010]

The digital optical receiver circuit of the present invention takes in a photoelectric conversion element for converting an optical signal into an electric signal and an electric signal from the photoelectric conversion element, and amplifies this signal to a predetermined level. And a differential preamplifier that outputs a first signal and a second signal. Then, based on the first signal and the second signal from the differential type preamplifier, the first logic determination signal and the second signal for logic determination having the intermediate value of the amplitudes of the first signal and the second signal are generated. An automatic threshold control circuit for forming a logic judgment signal, and a comparator for forming a logic signal based on the first logic judgment signal and the second logic judgment signal from the automatic threshold control circuit , And a self-reset circuit that resets the peak holding capacitor in the automatic threshold control circuit from the first signal or the second signal.

According to the digital optical receiver circuit of the present invention,
When the self-reset circuit detects that the first signal or the second signal from the differential type preamplifier is higher than the optical zero level by a predetermined level or more, a reset signal is issued to automatically set the threshold value. Reset the peak hold capacity in the control circuit. As a result, the zero level of the accurately offset optical signal is held and an accurate logic signal is obtained.

In the digital optical receiver circuit of the present invention, the automatic threshold control circuit is a first peak hold circuit for holding the maximum value of the positive first signal from the differential type preamplifier. A second peak hold circuit for holding the maximum value of the opposite phase second signal from the differential preamplifier, and the positive phase first signal and second peak from the differential preamplifier Capture the output signal from the hold circuit. The digital optical receiver circuit of the present invention further includes a first adder for adding these signals to form a first logical decision signal, a second signal of the opposite phase from the differential preamplifier, and A second adder is provided which takes in the output signal from the first peak hold circuit and adds these signals to form a second logic determination signal.

The automatic threshold control circuit forms a first logic judgment signal from the maximum value of the signal from the second peak hold circuit and the first signal. Also, a second logic determination signal is formed from the maximum value of the signal from the first peak hold circuit and the second signal.

The self-reset circuit includes a level detection circuit, a reset pulse generation circuit and a reset circuit.
The level detection circuit detects that at least one of the first signal and the second signal of the differential preamplifier is at a predetermined level or higher. The self-reset circuit also generates a reset pulse based on the output signal of the level detection circuit. The self-reset circuit outputs a reset signal to maintain the zero level of the optical signal when the signal of the differential preamplifier is above a certain level, and outputs a second peak in the automatic threshold control value circuit. Reset the hold circuit. By this reset, the second peak hold circuit that holds the zero level of the optical signal is operated. The reset circuit uses a second signal in the automatic threshold control circuit based on the signal from the reset pulse generator.
Discharge the hold of the peak hold circuit.

The digital optical receiver circuit of the present invention is
A photoelectric conversion element, a differential type preamplifier, a first peak hold circuit, a second peak hold circuit, a first adder, a second adder, and an automatic threshold control circuit. , A comparator, a level detection circuit, a reset pulse generator,
And a self-reset circuit.

The differential type preamplifier takes in an electric signal from the photoelectric conversion element, amplifies this signal to a predetermined level, and outputs it as a first signal and a second signal. First
The peak hold circuit of (1) takes in the first signal of the differential type preamplifier and holds the maximum value of this first signal. The second peak hold circuit takes in the second signal of the differential type preamplifier and holds the maximum value of this second signal.

Further, the first adder takes in the first signal from the differential type preamplifier and the output signal from the second peak hold circuit to form a first logic judgment signal. The second adder takes in the second signal from the differential type preamplifier and the output signal from the first peak hold circuit to form a second logic judgment signal. The automatic threshold control circuit is composed of first and second peak hold circuits and first and second adders. The comparator forms a logic signal based on the first logic determination signal and the second logic determination signal from the automatic threshold control circuit. The level detection circuit takes in at least one of the first signal and the second signal from the differential type preamplifier and determines whether or not this signal exceeds a predetermined value.

The reset pulse generator generates a reset pulse based on the output from the level detection circuit. The self-reset circuit includes a reset circuit that discharges the hold capacity of the second peak hold circuit by the reset pulse of the reset pulse generator.

According to this digital optical receiving circuit, the self-reset circuit detects that the first signal or the second signal from the differential type preamplifier is above a certain level. At this time, a reset signal is issued to reset the peak holding capacitance in the automatic threshold control circuit. This holds the zero level of the accurately offset optical signal and provides the correct logic symbol.

In the digital optical receiver circuit of the present invention,
In the first adder, one terminal of the first resistor is connected to the output of the second peak hold circuit. One terminal of the second resistor is connected to one output terminal of the differential preamplifier. The other terminal of the first resistor and the other terminal of the second resistor are commonly connected and connected to one input terminal of the comparator. Further, in the second adder, one terminal of the third resistor is connected to the output of the first peak hold circuit, and one terminal of the fourth resistor is connected to the other output terminal of the differential type preamplifier. Has been done. The other terminal of the third resistance and the fourth resistance terminal are commonly connected and connected to the other input terminal of the comparator.

This is a specific configuration of the first adder and the second adder in the automatic threshold control circuit. On the first identification signal side or the second identification signal side, two kinds of signals are added via resistors.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, before describing the configuration of a digital optical receiver circuit of the present invention, the configuration of a conventional digital optical receiver circuit will be described in order to facilitate understanding of the invention.

FIG. 5 shows a conventional DC coupling type optical receiving circuit. In the optical receiving circuit shown in FIG. 5, the anode of the photoelectric conversion element 101 is connected to the preamplifier 103. The cathode is connected to the bias power supply. The amplifier 103 includes a differential amplifier 131 and resistors 132 and 133.
Composed of and. The output of the amplifier 103 is connected to the input terminal of the automatic threshold control circuit 105. ATC
The circuit 105 includes a first peak hold circuit 151, a second peak hold circuit 152, and resistors 153 and 15
4, 155, 156. The output of the ATC circuit 105 is connected to the input terminal of the comparison circuit 107.

The operation of this optical receiving circuit will be described with reference to FIGS. 5, 6 and 7.

FIG. 6 is a time chart showing a normal operation of the optical receiving circuit. FIG. 7 is a time chart showing the operation of the same circuit when there is an abnormality. In these figures, the horizontal axis represents time, the vertical axis (a) shows the burst signal, the vertical axis (b) shows the output waveform of the preamplifier, and the horizontal axis (c) shows the output waveform of the peak hold circuit. At (d), the output signal waveform of the comparator is
Shown respectively.

First, let us consider a case where the signal is on standby, that is, the hold capacitors of the peak hold circuits 151 and 152 are in a discharged state. As shown in FIG. 6 (a), when a burst-like optical signal in a state where there is no light and a state where there is a light level equal to or higher than a predetermined level is input to the photoelectric conversion element 101, these are converted to optoelectric conversion. It becomes the signal Sa. This signal Sa is input to the transimpedance type preamplifier 103. Differential amplifier 131 and resistor 13
From the preamplifier circuit 103 composed of
As shown in (b), differential signals Sbp and Sbm whose polarities are positive and negative are output. Differential signals Sbp, Sbm
Is input to the ATC circuit 105 composed of two adders composed of the two peak hold circuits 151 and 152 and the resistors 152 to 156. In the ATC circuit 105, the signals Sbp and Sbm are formed such that the identification value Ls used to determine the logic "1" or "0" is set to the intermediate value between the amplitudes of the signals Sdp and Sdm.
The output signals Sdp and Sdm of the ATC circuit 30 are shown in FIG.
As shown in (d), these are supplied to the comparator 107. In the comparator 107, these output signals Sd
p, Sdm, the logic "1" shown in FIG.
It is identified by the signal Se consisting of "0".

Next, as shown in FIG. 7A, when a signal light waveform consisting of a state in which the light does not completely reach the zero level and a light having a predetermined level or more is input to the conventional optical receiver. The operation of will be described. This signal light waveform has a wavelength of
This is a waveform in which the extinction ratio has deteriorated due to a bias being applied in advance. In order to prevent the light emission due to the deterioration of the extinction ratio from affecting other burst signals, the light emission is blocked at the transmitter side at times other than the burst signal.

When a signal waveform having an offset due to deterioration of the extinction ratio (FIG. 7A) is input to the photoelectric conversion element 101, these are photoelectrically converted into a signal Sa which is input to the preamplifier 103. . In the preamplifier 103, FIG.
As shown in (b), a constant bias voltage VL is added to the positive and negative polarities due to the offset. When the logical value is "1", the differential signals Sbp and Sbm, which have positive and negative polarities of the voltage (VL + VS), are output. This signal is AT
When input to the C circuit 105, the peak hold circuit 15
2 cannot accurately hold the level (-VL) of the logic "0" of the second signal Sbm having the opposite phase of the preamplifier 103. Therefore, the value in the signal waiting state before the burst signal arrives is continuously held. ATC circuit 10
As shown in FIG. 7D, the output of No. 5 is the signal Sdp whose positive phase side output is between the level (VL + VS) / 2 and the level (VL / 2). In addition, the signal Sd in which the output of the opposite phase touches between the level (VS / 2) and the level (0)
Therefore, the level balance between the positive-phase side output Sdp and the negative-phase side output Sdm is lost.

The comparator 107 outputs signals Se of logic "0" and "1" having different duty ratios. As a result, the amplitude of the output signal (logic determination signal) output from the ATC circuit 105 is reduced.

When an optical signal having an offset as shown in FIG. 7A is input, a current is applied to the photoelectric conversion element in a direction of eliminating the offset. However, in the former optical receiving circuit, as shown in FIG. 7D, the offset of the extinction ratio deterioration as shown in FIG. 7A cannot be canceled, and the output of the ATC circuit 105 is the positive phase output signal. The level balance between Sdp and the anti-phase output signal Sdm is lost. As a result, the output signal S from the comparator 109
Cause the deterioration of the waveform duty. ATC circuit 1
The amplitudes of the output signals Sdp and Sdm output from 05 decrease, and the identification value Ls changes.

This duty deterioration remarkably deteriorates the data identification margin especially when the received signal level is low.
If there is no room for data identification, the minimum light receiving level of the receiving circuit is deteriorated. In addition, in an optical receiver that handles burst data, a method of timing extraction based on information of both rising and falling edges of data is generally adopted in order to perform high-speed operation pull-in. Therefore, when the duty fluctuation occurs, the jitter of the extracted clock increases and the pull-in characteristic is deteriorated.

The decrease in amplitude causes deterioration of the minimum light receiving level and decrease of the dynamic range. A decrease in dynamic range leads to a decrease in system margin.

Next, the digital optical receiver circuit of the present invention which solves the above problems will be described in detail below.

FIG. 1 shows the configuration of an embodiment of the digital optical receiver of the present invention. Since the digital optical receiving circuit of the present invention also receives an arbitrary signal pattern, the blocks are DC-coupled.

The digital optical receiver circuit of the present invention is roughly divided into a photoelectric conversion element 1, a differential type preamplifier 3, an automatic threshold control circuit 5, a comparator 7, and a self reset circuit 9. I have it. Specifically, it is configured as follows.

The anode of the photoelectric conversion element 1 is the preamplifier 3
, And its cathode is connected to a bias power supply (not shown). The preamplifier 3 is a differential amplifier 3
1 and a resistor 32, 33 is a transimpedance type differential amplifier. Specifically, the positive phase output of the differential amplifier 31 is fed back to the negative phase input of the differential amplifier 31 via the feedback resistor 33. On the other hand, the negative phase output of the differential amplifier 31 is fed back to the positive phase input of the differential amplifier 31 via the feedback resistor 32. The first signal and the second signal from the preamplifier 3 are supplied to the input terminal of the ATC circuit 5, and the first signal is also input to the self-reset circuit 9.

The ATC circuit 5 includes a first peak hold circuit 51, a second peak hold circuit 52, and a resistor 5.
A first adder circuit 58 composed of 3, 56 and resistors 54, 5
5 and a second adder circuit 57.
In the ATC circuit 5, the logic determination signal for determining the logic "1" or "0" can be set to an intermediate value of the signal amplitude.
The positive phase output (first logic determination signal) of the ATC circuit 5 is a second peak hold circuit that holds the peak values of the positive phase output of the preamplifier 3 and the negative phase output of the preamplifier 3. It is obtained by adding the output of 52 and the output of 52. AT
The negative phase output of the C circuit 5 is obtained by adding the negative phase output of the preamplifier 30 and the output of the first peak hold circuit 51 that holds the peak value of the positive phase output of the preamplifier 3.

Each output of the ATC circuit 5 is connected to each input terminal of the comparison circuit 7. The self-reset circuit 9 includes a level detector 91 that detects arrival of a signal from the output of the preamplifier 3, a reset pulse generator 92 that generates a reset signal that is a single pulse from the output of the level detection circuit 91, and The reset circuit 93 is configured to discharge the hold capacitance of the second peak hold circuit 52 using the reset signal.

Next, the operation of the above-described digital optical receiving circuit according to one embodiment of the present invention will be described based on FIG. 1 and with reference to the timing chart shown in FIG. In the figure,
The time is plotted on the horizontal axis, the burst signal is plotted on the vertical axis (a), the output waveform of the preamplifier is plotted on the vertical axis (b), and the output waveform of the peak hold circuit is plotted on the vertical axis (c). The output signal waveform of the container is taken respectively.

First, a case will be described in which the burst signal shown in FIG. 2A is input to the digital optical receiving circuit in the signal waiting state, that is, when the hold capacity of the peak hold circuit is in the discharging state. Here, the extinction ratio of the burst signal is deteriorated due to a bias being added in advance in order to reduce the emission delay of the semiconductor laser which is the transmission light source. In order to prevent the light emission due to the deterioration of the extinction ratio from affecting other burst signals, the time other than the burst signal is when the light emission is blocked on the transmitter side.

When such an optical signal is input to the photoelectric conversion element 1, it is photoelectrically converted and the signal Sa is output. This signal Sa is amplified by the preamplifier 3 to a predetermined level. The first signal Sbp on the positive phase side output from the preamplifier 3 has the level (+ VL) set to the zero level of the signal, as shown in FIG. 2B. Maximum level [+
Let (VL + VS)] be the maximum level of the signal. In addition, the second signal Sbm on the opposite phase side, which is output from the preamplifier 3
Sets the level (-VL) to the zero level of the signal. The maximum level [-(+ VL + VS)] is the maximum level of the signal.

These signals Sbp and Sbm are held by the first peak hold circuit 51 and the second peak hold circuit 52 of the ATC circuit 5, and the signal Se shown in FIG. 2 (e) is output. However, when the signal waiting state is changed to the signal receiving state, the peak hold circuit 52
The hold capacity of is once discharged. Here, it is necessary to hold the negative phase voltage (-VL) of the preamplifier 3 corresponding to the zero level in the signal waveform, which is a value different from that in the signal standby state. For this purpose, it is necessary to discharge the hold capacity of the second peak hold circuit 52 in the ATC circuit 5.

Therefore, the reset signal Sd, which is a signal for discharging the hold capacitance of the second peak hold circuit 52, is generated as follows. At the same time as the signal is received, the output signal Sc of the level detector 91 becomes a logic "1" as shown in FIG. This signal is input to the reset pulse generator 92 to form a single pulse Rd as shown in FIG. 2 (d). When the single pulse Rd is input to the reset circuit 93, the reset circuit 93 discharges the hold capacitance of the second peak detector 52. In this way, the first peak hold circuit 51 holds the level of the signal Sbp, and finally the level [+ (VL
+ VS)] is held. Further, the second peak hold circuit 52 holds the zero level (-VL) of the signal Sbm.

These peak hold values Sep, Sem,
And positive and negative phase signals Sbp, S from the preamplifier 3
When bm is changed in each of the first adder 58 and the second adder 57, the output voltage of the ATC circuit 5 becomes, as shown in FIG.
It becomes Sfm. When the logic determination signals Sfp and Sfm are at the same level, the discrimination value Ls is just half the amplitude. The output signals Sfp and Sfm are output to the comparator 7.
2 (g), the output signal S of the normal logic "1" or "1" is compared by
g is obtained.

Now, returning to FIG. 1, the configurations and operations of the self-reset circuit 9 for sending the above-mentioned reset signal and the peak hold circuit 52 for carrying out peak hold will be described with reference to FIGS. 3 and 4. FIG. 3 shows an embodiment of these circuits, and FIG. 4 shows signal waveforms at respective portions.

As described above, the self-reset circuit 9
Is composed of a level detector 91, a reset pulse generator 92, and a reset circuit 93. The self-reset circuit 91 includes a comparator 201 and an RS flip-flop 2
02. The positive terminal of the comparator 201 is shown in FIG.
The output from the preamplifier 31 shown in FIG. −
The reference voltage V1 is applied to the terminals.

Now, the output waveform from the preamplifier 31 is
It is assumed that the signal waveform has an offset as shown by Sbp in FIG. The output signal waveform from the comparator 201 is as shown by S1. This signal is input to the RS flip-flop 202. In addition, the RS flip-flop 202 has a reset signal S as indicated by S2.
2 is input. Then, the output of the RS flip-flop 202 has the signal waveform indicated by S3.

The signal S3 is input to the reset pulse generator 92. The reset pulse generator 92 includes the delay circuit 2
03 and an exclusive OR circuit 204. The signal S392 is composed of the delay circuit 203 and the exclusive OR circuit 204. The signal S3 is branched, and one of the signals is delayed by the delay circuit 203 for a predetermined time and output (S
4). The signals S3 and S4 are output as a pulse signal S5 by the exclusive OR circuit 204.

Further, the pulse signal S2 and the pulse signal S5
Is logically output by the logical sum circuit 205 of the reset circuit 93 (S6). Then, it is output to the peak hold circuit 52 via the transistor 206. The peak hold circuit 52 performs peak hold with the capacitor 210. As shown in FIG. 3, the peak hold circuit 52 includes a comparator 207, a capacitor 210 and the like. Then, when the reset signal S6 is input, the capacitance stored in the capacitor 210 is discharged. Needless to say, the self-reset circuit 9 and the peak hold circuit 52 can be realized by other circuit configurations.

According to this embodiment, the peak hold circuit accurately holds the logic "1" or logic "0" level of the signal. Therefore, there is no deterioration of the duty of the output waveform or reduction of the output signal amplitude due to the offset of the input signal or the preamplifier.

Since there is no duty deterioration, the data identification margin does not deteriorate even when the received signal level is low,
There is no increase in the jitter of the extracted clock or deterioration of the pull-in characteristic. Furthermore, since there is no decrease in output signal amplitude,
There is no deterioration in the minimum reception level or reduction in the dynamic range, which is the receivable range.

[0052]

As described above, according to the digital optical receiver circuit of the present invention, since the peak hold circuit accurately holds the logic "1" and "0" levels of the signal, the input signal and the prefix are held. There is no deterioration of the output waveform duty or decrease of the output signal amplitude due to the offset of the amplifier. Since duty deterioration does not occur, the data identification margin does not deteriorate even when the received signal level is low. Furthermore, the jitter of the extracted clock does not increase and the pull-in characteristic does not deteriorate.

Since the output signal amplitude does not decrease, the minimum receiving level does not deteriorate and the dynamic range which is the light receiving range does not decrease. Also, the signal from the preamplifier is reliably peak-held. The hold capacity of the second peak hold circuit in the automatic threshold control circuit can be discharged, and accurate peak hold can be performed.

Since the output signal amplification is not reduced, the minimum reception level is not deteriorated and the dynamic range, which is the light receiving range, is not reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital optical receiver circuit of the present invention.

FIG. 2 is a timing chart showing an optical receiving operation by the digital optical receiving circuit of the present invention.

FIG. 3 is a circuit diagram showing an embodiment of a reset circuit in the digital optical receiver circuit of the present invention.

FIG. 4 is a timing chart showing waveforms at various parts of the reset circuit shown in FIG.

FIG. 5 is a block diagram showing an example of a configuration of a conventional digital optical receiving circuit.

FIG. 6 is a timing chart for explaining a basic function of a conventional digital optical receiver circuit.

FIG. 7 is a timing chart showing the operation of the conventional digital optical receiver circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Photoelectric conversion element 3 Preamplifier 5 ATC circuit 7 Comparator 9 Self reset circuit 51 First peak hold circuit 52 Second peak hold circuit 57 First adder circuit 58 Second adder circuit 91 Level detector 92 Reset Pulse generator 93 Reset circuit 101 Photoelectric conversion element 103 Preamplifier 105 Automatic threshold control circuit 107 Comparison circuit 131 Differential amplifier 132 Resistor 133 Resistance 151 First peak hold circuit 152 Second peak hold circuit 153 Resistance 154 Resistor 155 resistor 156 resistor 201 comparator 201 202 RS flip-flop 203 delay circuit 203 204 exclusive OR circuit 205 OR circuit 206 transistor 206 207 comparator 207 210 capacitor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H03K 5/08 H04B 10/02 10/18 H04L 25/03 25/06

Claims (16)

[Claims] 1. A photoelectric conversion means for converting an optical signal into an electric signal, and an amplification means for amplifying the electric signal output from the photoelectric conversion means to a predetermined level and outputting a first signal and a second signal. And threshold control means for transmitting a first logic judgment signal and a second logic judgment signal having an intermediate value of the amplitude values of the first signal and the second signal, and the first logic. A comparing unit that forms a logic signal based on the determination signal and the second logic determination signal, and the peak holding capacitance in the threshold value control unit is reset from the first signal or the second signal. A digital optical receiver circuit comprising a self-reset means. 2. A photoelectric conversion element which converts an optical signal into an electric signal, and a differential which amplifies the electric signal output from the photoelectric conversion element to a predetermined level and outputs a first signal and a second signal. A type preamplifier, an automatic threshold control circuit for transmitting a first logic decision signal and a second logic decision signal having an intermediate value of the amplitude values of the first signal and the second signal, A comparator that forms a logic signal based on the first logic determination signal and the second logic determination signal; and peak holding in the automatic threshold control circuit from the first signal or the second signal. A digital optical receiving circuit, comprising: a self-reset circuit for resetting a storage capacitor. 3. The automatic threshold control circuit, a first peak hold circuit for holding the maximum value of the positive phase first signal from the differential type preamplifier; A second peak-hold circuit for holding a maximum value of a negative-phase second signal from the amplifier; a positive-phase first signal from the differential preamplifier and a second peak-hold circuit from the second peak-hold circuit. A first adder for adding output signals to form a first logical decision signal; a second signal in anti-phase from the differential preamplifier and an output from the first peak hold circuit 3. A digital optical receiver circuit according to claim 2, further comprising a second adder for adding signals to form a second logical judgment signal. 4. The level detection circuit, wherein the self-reset circuit detects that at least one of the first signal and the second signal of the differential preamplifier is at a predetermined level or higher, A reset pulse generator for generating a reset pulse based on the output signal of the level detection circuit; and a second peak hold circuit in the automatic threshold control circuit based on the signal from the reset pulse generator. 3. The digital optical receiver circuit according to claim 2, further comprising a reset circuit for discharging the hold capacitance. 5. The level detector includes a comparator that compares a reference voltage with the first signal or the second signal output from the differential type preamplifier, and outputs a comparison signal. 5. An RS flip-flop that receives a comparison signal and the reset signal as an input is provided.
The described digital optical receiver circuit. 6. The delay pulse generator outputs a delay signal by branching and delaying the output signal of the RS flip-flop, and outputting an exclusive OR of the output signal and the delay signal. 5. The digital optical receiver circuit according to claim 4, further comprising an exclusive OR circuit that outputs a pulse signal. 7. The reset circuit includes a logical sum circuit that takes a logical sum of the pulse signal and the reset signal and outputs a reset signal, and a driving unit that enhances the driving capability of the reset signal. The digital optical receiver circuit according to claim 4, which is characterized in that: 8. The peak hold circuit includes: a differential amplifier in which the first signal or the second signal output from the differential preamplifier is input to a first input terminal; A capacitor whose one end is connected to the output side of the amplifier and whose other end is grounded; reset signal input means which is arranged between the output of the differential amplifier and the capacitor and which inputs the reset signal; 4. The digital optical receiver circuit according to claim 3, further comprising feedback connection means for feedback connection to the second input terminal of the differential amplifier. 9. A photoelectric conversion element for converting an optical signal into an electric signal, and a differential front element for amplifying the electric signal from the photoelectric conversion element to a predetermined level and outputting a first signal and a second signal. An on-amplifier, a first peak hold circuit that holds the maximum value of the first signal, a second peak hold circuit that holds the maximum value of the second signal, the first signal and the first signal A first adder that takes in the output signal from the second peak hold circuit to form a first logical decision signal; and a second signal from the differential preamplifier and the first peak hold circuit. On the basis of an automatic threshold value control circuit including a second adder which takes in the output signal of the second logic decision signal and forms a second logic decision signal, and the first logic decision signal and the second logic decision signal. A comparator for forming a logic signal; 2. A digital optical receiver circuit comprising: a self-reset circuit including a reset circuit for discharging the hold capacity of the second peak hold circuit. 10. The first adder has one terminal of a first resistor connected to the output of the second peak hold circuit, and one terminal of the second resistor has the differential preamplifier. Connected to one output terminal of the comparator, the other terminal of the first resistor and the other terminal of the second resistor are commonly connected to one input terminal of the comparator, and the second adder Has one terminal of a third resistor connected to the output of the first peak hold circuit, one terminal of the fourth resistor connected to the other output terminal of the differential preamplifier, and The other terminal of the resistor 3 and the fourth resistor other terminal are commonly connected,
10. The digital optical receiver circuit according to claim 9, wherein the digital optical receiver circuit is connected to the other input terminal of the comparator. 11. The automatic threshold control circuit comprises: a first peak hold circuit for holding a maximum value of a positive-phase first signal from the differential preamplifier; A second peak-hold circuit for holding a maximum value of a negative-phase second signal from the amplifier; a positive-phase first signal from the differential preamplifier and a second peak-hold circuit from the second peak-hold circuit. A first adder for adding output signals to form a first logical decision signal; a second signal in anti-phase from the differential preamplifier and an output from the first peak hold circuit 10. A digital optical receiver circuit according to claim 9, further comprising a second adder for adding signals to form a second logic judgment signal. 12. A level detection circuit for detecting that at least one of the first signal and the second signal of the differential type preamplifier is at a predetermined level or more, A reset pulse generator for generating a reset pulse based on the output signal of the level detection circuit; and a second peak hold circuit in the automatic threshold control circuit based on the signal from the reset pulse generator. 10. The digital optical receiver circuit according to claim 9, further comprising a reset circuit for discharging the hold capacitance. 13. The level detector includes a comparator that compares a reference voltage with the first signal or the second signal output from the differential amplifier type preamplifier, and outputs a comparison signal. 10. An RS flip-flop which receives the comparison signal and the reset signal as an input is provided.
The described digital optical receiver circuit. 14. The reset pulse generator includes a delay circuit for branching and delaying an output signal of the RS flip-flop to output a delayed signal, and calculating an exclusive OR of the output signal and the delayed signal. 10. The digital optical receiver circuit according to claim 9, further comprising an EX-OR circuit that outputs a pulse signal. 15. The reset circuit includes a logical sum circuit that takes a logical sum of the pulse signal and the reset signal and outputs a reset signal, and a drive circuit that enhances the drive capability of the reset signal. The digital optical receiver circuit according to claim 9, which is characterized in that. 16. The peak hold circuit includes: a differential amplifier in which the first signal or the second signal output from the differential amplifier type preamplifier is input to a first input terminal; A capacitor whose one end is connected to the output side of the dynamic amplifier and whose other end is grounded; and reset signal input means which is arranged between the output of the differential amplifier and the capacitor and which inputs the reset signal, 10. The digital optical receiver circuit according to claim 9, further comprising feedback connection means for connecting one end to the second input terminal of the differential amplifier by feedback connection.