CN218413963U - Display panel and display terminal - Google Patents

Abstract

The embodiment of the utility model discloses display panel, including scanning drive circuit, reset circuit and along many scanning lines that the first direction extends and arrange along the second direction and be a plurality of pixel unit that the array was arranged, scanning drive circuit is used for exporting scanning signal to pixel unit to control pixel unit receives the data signal that is used for image display in order to carry out image display. The reset circuit is electrically connected to the scan driving circuit, and is configured to simultaneously control all the pixel units to release charges corresponding to the retained data signals within a preset time period through the scan driving circuit and the plurality of scan lines when it is detected that the display panel stops displaying the image. Through the setting of the reset circuit, when the display panel stops displaying images, the release of electric charges in the pixel units is controlled, and the problem of shutdown afterimages is effectively solved. The embodiment of the utility model provides a still disclose a display terminal including aforementioned display panel.

Description

Display panel and display terminal

Technical Field

The utility model relates to a show technical field, especially relate to be applied to display panel and display terminal.

Background

Liquid Crystal Displays (LCD) are widely used in electronic devices such as computers, mobile phones, and televisions. The liquid crystal display generally includes an array substrate and a color filter substrate disposed opposite to each other, and a liquid crystal layer disposed between the array substrate and the color filter substrate. When the liquid crystal display displays, point voltages are respectively applied to the pixel units on the array substrate and the common electrode on the color film substrate to control the deflection of liquid crystal molecules in the liquid crystal layer. However, since the pixel unit stores part of the charges when displaying images, if the pixel unit is turned off, the charges are not released, and a residual image is left, and polarization of the liquid crystal occurs over time.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned prior art not enough, the utility model provides a can effectively eliminate display panel of shutdown ghost.

A display panel comprises a scanning driving circuit, a plurality of scanning lines extending along a first direction and distributed along a second direction, and a plurality of pixel units distributed in an array mode, wherein the scanning driving circuit is used for outputting scanning signals to the pixel units so as to control the pixel units to receive data signals for image display to execute image display. The panel further comprises a reset circuit, wherein the reset circuit is electrically connected to the scanning driving circuit and used for simultaneously controlling all the pixel units to release the charges corresponding to the reserved data signals within a preset time period through the scanning driving circuit and the plurality of scanning lines when the display panel is detected to stop displaying the images.

Optionally, the display panel further includes a level shift circuit, the level shift circuit is connected to the reset circuit, and is configured to output a plurality of clock signals with different phases to the reset circuit when the display panel performs image display and transmit the clock signals to the scan driving circuit through the reset circuit, the scan driving circuit outputs a scan signal to the pixel unit according to the plurality of clock signals, and the level shift circuit stops outputting the clock signals to the scan driving circuit when the display panel stops image display. The reset circuit comprises a selection unit and a detection control unit, wherein the selection unit is electrically connected to the detection control unit, the level conversion circuit and the scanning drive circuit and used for receiving a clock signal from the level conversion circuit and transmitting the clock signal to the scanning drive circuit so as to drive the pixel units to display an image, or the self-detection control unit receives a control signal and outputs the control signal to the scanning drive circuit, and the control signal is used for controlling all the pixel units to release the reserved charges at the same time.

Alternatively, the detection control unit is used for detecting the image display condition of the display panel, stopping outputting the control signal to the selection unit when detecting that the display panel performs image display, and outputting the control signal to the selection unit when detecting that the display panel stops the image display.

Optionally, the detection control unit includes a detection module, where the detection module is configured to detect an output cycle number of a trigger signal, the trigger signal is configured to control output of the data signal, when the display panel stops displaying the image and after the trigger signal is in a preset cycle, the data signal stops being output to the pixel unit, and the level shift circuit stops outputting the clock signal. After the detection module detects that the trigger signal is in a preset period, the detection module controls the control signal to be output to the selection unit.

Optionally, the detection module includes a clock counter, the clock counter is connected to a trigger start end of the data driving circuit, the data driving circuit is configured to output a data signal to the pixel unit after receiving a trigger signal received by the trigger start end, the clock counter is configured to count a period of the trigger signal when the display panel stops displaying an image, and when the count reaches a preset period of the trigger signal, the count signal controls the detection module to output a control signal.

Optionally, the detection control unit further includes a first resistor and a switching tube, the clock counter is connected to a gate of the switching tube, a source of the switching tube is connected to the first voltage end through the first resistor, and a drain of the switching tube is connected to the selection unit. The switch tube is conducted after receiving the counting signal, and a first voltage output by the first voltage end is output through the source electrode and the drain electrode of the switch tube and is transmitted to the selection unit as a control signal.

Optionally, the detection control unit further includes a second resistor, where the second resistor is connected between the drain of the switching tube and the ground terminal, and is used for providing the ground potential for the selection unit when the switching tube is turned off, and is used for adjusting the length of the preset time period of the control signal when the switching tube is turned on.

Optionally, the selection unit includes a plurality of or gates arranged in sequence, first input ends of the plurality of or gates are respectively connected to the drains of the switching tubes and are configured to receive a control signal, second input ends of the plurality of or gates are connected to the level conversion circuit and are configured to receive a clock signal, output ends of the plurality of or gates are connected to the scan driving circuit and are configured to output the clock signal to the scan driving circuit to drive the scan driving circuit to output a scan signal to the pixel units and control the pixel units to display an image, or output the control signal to the scan driving circuit, and the scan driving circuit is configured to simultaneously output the scan signal to all the pixel units within a preset time period to control all the pixel units to simultaneously release the remaining charges.

Optionally, when the switching tube is turned off, the first input ends of the plurality of or gates are connected to the ground end through the second resistor for controlling the potential of the first input ends to be maintained at the ground potential, and meanwhile, the second input ends of the plurality of or gates receive the clock signal from the level conversion circuit and output the clock signal to the scan driving circuit for controlling the pixel unit to display an image through the scan driving circuit.

The embodiment of the utility model provides a still disclose a display terminal, including sequential control circuit, data drive circuit and aforementioned display panel, sequential control circuit is used for exporting grid output control signal extremely scan drive circuit exports source output control signal extremely data drive circuit, in order to control scan drive circuit exports scan signal extremely pixel element, control data drive circuit output data signal extremely pixel element, pixel element foundation scan signal with data signal carries out image display.

Compared with the prior art, the output period of the trigger signal is detected through the clock counter, and when the display panel stops displaying the image, the output control signal is output to the scanning driving circuit and simultaneously output the scanning signal in the last period of the trigger signal, so that all the pixel units are controlled to be simultaneously opened to release the charges, and the problem of shutdown ghost is effectively solved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic side view of a display terminal according to a first embodiment of the present invention;

FIG. 2 is a schematic plan view of the array substrate in the display panel shown in FIG. 1;

FIG. 3 is an equivalent circuit diagram of the pixel unit in FIG. 2;

FIG. 4 is a circuit layout diagram of the display panel of FIG. 2;

FIG. 5 is a timing diagram illustrating the output of the trigger signal and the scan signal in FIG. 4.

Description of the reference numerals: the display device comprises a display terminal-1, a display panel-10, a backlight module-20, a display area-10 a, a non-display area-10 b, an array substrate-10C, a liquid crystal layer-10 e, a color film substrate-10 d, a time sequence control circuit-11, a Data driving circuit-12, a level conversion circuit-13, a reset circuit-14, a scanning driving circuit-15, a pixel unit-P, a first direction-F1, a second direction-F2, a scanning line-G, a Data line-S, a horizontal synchronizing signal-Hsyn, a vertical synchronizing signal-Vsyn, a grid output control signal-Cg, a source output control signal-Cs, a clock signal-CLK, a Data signal-Data, a liquid crystal capacitor-C1, a storage capacitor-C2, a selection detection control unit-141, a selection unit-142, a trigger signal-TP, an OR gate-Y, a first OR gate-Y1, a second OR gate-Y2, a third OR gate-Y3, an nth or gate-Yn, a clock counter-1, a first resistor-141R 1, a second resistor-R2, a voltage switch-VGR 2 and a voltage switch.

Detailed Description

In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. The preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

The following description of the various embodiments refers to the accompanying drawings, which are included to illustrate specific embodiments in which the invention may be practiced. The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connect" or "connect" as used herein includes both direct and indirect connections (connections), unless otherwise specified. Directional phrases used in this disclosure, such as "upper," "lower," "front," "rear," "left," "right," "inner," "outer," "side," and the like, refer only to the orientation of the attached drawing figures and, thus, are used in a better and clearer sense to describe and understand the present invention rather than to indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered limiting of the invention.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as being fixedly connected, detachably connected, or integrally connected; may be a mechanical connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art. It should be noted that the terms "first", "second", and the like in the description and claims of the present invention and in the drawings are used for distinguishing different objects and not for describing a particular order.

Furthermore, the terms "comprises," "comprising," "includes," "including," or "including" as used herein, specify the presence of stated features, operations, elements, and/or the like, but do not limit the presence of one or more other features, operations, elements, or the like. Furthermore, the terms "comprises" or "comprising" indicate the presence of the respective features, numbers, steps, operations, elements, components or combinations thereof disclosed in the specification, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components or combinations thereof, and are intended to cover non-exclusive inclusions. Furthermore, when describing embodiments of the present invention, "may" mean "one or more embodiments of the present invention. Also, the term "exemplary" is intended to refer to examples or illustrations.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

Referring to fig. 1, fig. 1 is a schematic side view of a display terminal 1 according to a first embodiment of the present invention. As shown in fig. 1, the display terminal 1 includes a display panel 10 and a backlight Module 20 (BM), wherein the BM 20 is used for providing light for display to the display panel 10.

The display terminal 1 further includes other components (not shown), which may be a power module, a signal processor module, a signal sensing module, and the like.

The display panel 10 includes an image display area 10a and a non-display area 10b. The display area 10a is used for displaying images, and the non-display area 10b is disposed around the display area 10a to provide other auxiliary components or modules. Specifically, the display panel 10 includes an Array Substrate (AS) 10c, a Color filter substrate (CF) 10d, and a liquid crystal layer 10e interposed between the Array substrate 10c and the Color filter substrate 10 d. The driving elements disposed on the array substrate 10c and the color filter substrate 10d generate corresponding electric fields according to the Data signals Data, so as to drive the liquid crystal molecules in the liquid crystal layer 10e to rotate at an angle to emit light rays with corresponding brightness, thereby performing image display.

Referring to fig. 2, fig. 2 is a schematic plan layout view of an array substrate 10c of the display panel 10 shown in fig. 1. As shown in fig. 2, the corresponding image display region 10a of the array substrate 10c includes a plurality of m × n Pixel cells (pixels) P arranged in a matrix, m Data lines (Data lines) S1 to Sm, and n scan lines (Gate lines) G1 to Gn, where m and n are natural numbers greater than 1.

The plurality of data lines S1 to Sm are insulated and arranged in parallel with each other at a first predetermined distance along the second direction F2, the plurality of scan lines G1 to Gn are insulated and arranged in parallel with each other at a second predetermined distance along the first direction F1, the plurality of scan lines G1 to Gn are insulated from the plurality of light emitting data lines S1 to Sm, and the first direction F1 is perpendicular to the second direction F2.

The display terminal 1 further includes a timing control circuit 11, a Data Driver circuit (Data Driver) 12 and a Scan Driver circuit (Scan Driver) 15 for driving the pixel units to display images, which are disposed on the array substrate 10c corresponding to the non-display region 10b of the display panel 10.

The Data driving circuit 12 is electrically connected to the Data lines S1 to Sm, and is configured to transmit image Data (Data) to be displayed to the pixel units P through the Data lines S1 to Sm in the form of Data voltages.

The scan driving circuit 15 is electrically connected to the plurality of scan lines G1 to Gn, and is configured to output a scan signal Gn through the plurality of scan lines G1 to Gn for controlling when the pixel unit P receives image data. The scan driving circuit 15 sequentially outputs scan signals G1, G2, 8230, gn from the plurality of scan lines G1 to Gn in a scan cycle in a positional arrangement order.

The timing control circuit 11 is electrically connected to the Data driving circuit 12 and the scan driving circuit 15, respectively, and is configured to control the working timings of the Data driving circuit 12 and the scan driving circuit 15, that is, output corresponding timing control signals to the Data driving circuit 12 and the scan driving circuit 15, so as to control when to output the corresponding scan signals Gn and the image Data.

In the present embodiment, the circuit elements in the scan driving circuit 15 and the pixel units P in the display panel 10 are manufactured in the display panel 10 in the same process, i.e. the GOA (Gate Driver on Array) technology.

It can be understood that the display terminal 1 further includes other auxiliary circuits for completing the display of the image together, for example, an image receiving Processing circuit (GPU), a power circuit, and so on, which are not described in detail in this embodiment.

Specifically, the timing control circuit 11 receives an image signal representing image information, a clock signal CLK for synchronization, a horizontal synchronization signal Hsyn, and a vertical synchronization signal Vsyn from an external signal source, and outputs a gate output control signal Cg and a clock signal CLK for controlling the scanning drive circuit 15, a source output control signal Cs for controlling the Data drive circuit 12, and a Data signal Data representing image information. In this embodiment, the timing control circuit 11 performs Data adjustment processing on the original Data signal to obtain a Data signal Data, and transmits the Data signal Data to the Data driving circuit 12.

The scan driving circuit 15 receives the gate output control signal Cg and the clock signal CLK output from the timing control circuit 11, and outputs scan signals to the scan lines G1 to Gn. The Data driving circuit 12 receives the source output control signal Cs output from the timing control circuit 11, and outputs Data signals Data for driving elements to perform image display in each pixel unit P in the display region 10a to the respective Data lines S1 to Sm. The Data signal Data supplied to the display panel 10 is a gray scale voltage in an analog form. The scan driving circuit 15 outputs scan signals to control the pixel unit P to receive the Data signals Data output by the Data driving circuit 12, so as to control the pixel unit P to display a corresponding image.

The display panel 10 further includes a level shift circuit 13 and a reset circuit 14, wherein the level shift circuit 13 is connected to the timing control circuit 11, and is configured to receive the clock signal CLK from the timing control circuit 11, perform circuit amplification on the clock signal CLK, transmit the clock signal CLK to the scan driving circuit 15 through the reset circuit 14, and output the scan signals G1 to Gn by the scan driving circuit 15. The reset circuit 14 is used for controlling the pixel units P to discharge the charges corresponding to the Data signals Data left therein for a preset period of time through the plurality of scanning lines G1 to Gn connected through the scanning drive circuit 15 when detecting that the display panel 10 stops the image display.

Referring to fig. 3, fig. 3 is an equivalent circuit diagram of the pixel unit in fig. 2.

As shown in fig. 3, the pixel unit P includes a TFT, a liquid crystal capacitor C1 and a storage capacitor C2, a gate of the TFT is connected to the scan line G, a source of the TFT is connected to the Data line S, and a drain of the TFT is connected to the liquid crystal capacitor C1 and the storage capacitor C2, when the gate of the TFT receives a scan signal from the scan line G, that is, when a voltage in the scan line G reaches a turn-on voltage VGH of the TFT, the TFT is turned on, the liquid crystal capacitor C1 and the storage capacitor C2 receive a Data signal Data from the Data line S for charging, and form an electric field with a common voltage terminal (not identified) to drive the liquid crystal to deflect, so that the pixel unit P emits light with a preset gray level.

When the image display of the pixel unit P is finished, the gate of the TFT receives the turn-off signal VGL transmitted in the data line, and the source and the drain of the TFT are in an off state, at this time, the charges in the liquid crystal capacitor C1 and the storage capacitor C2 used for image display are not released, so that the liquid crystal is always in a deflection state, and polarization is generated and the display panel has an afterimage.

Referring to fig. 4, fig. 4 is a circuit layout diagram of the display panel 10 in fig. 2. As shown in fig. 4, the display panel 10 includes a level conversion circuit 13, a reset circuit 14, and a scan drive circuit 15, and a plurality of scan lines G1 to Gn, a plurality of data lines S1 to Sm, and a plurality of pixel units P arranged in an array in the display region 10 a.

The level shift circuit 13 is connected to the reset circuit 14, and is configured to output a plurality of clock signals CLK with different phases to the reset circuit 14 when the display panel 10 performs image display, and transmit the clock signals CLK to the scan driving circuit 15 through the reset circuit 14, the scan driving circuit 15 outputs scan signals to the pixel units P according to the plurality of clock signals CLK1 to CLKn, and the level shift circuit 13 stops outputting the clock signals CLK to the scan driving circuit 15 when the display panel 10 stops image display.

The reset circuit 14 and the scan driving circuit 15 are used for simultaneously controlling all the pixel units P to release the charges corresponding to the Data signals Data stored in the pixel units P within a predetermined time period through the scan driving circuit 15 and the plurality of scan lines G1-Gn when the pixel units P of the display panel 10 stop displaying images, so as to control the liquid crystal in the pixel units P to return to the original position.

The reset circuit 14 includes a selection unit 142 and a detection control unit 141. The selection unit 142 is electrically connected to the detection control unit 141, the level conversion circuit 13 and the scan driving circuit 15, and is configured to receive the clock signal CLK from the level conversion circuit 13 and transmit the clock signal CLK to the scan driving circuit 15, and convert the clock signal CLK into a scan signal through the scan driving circuit 15 and output the scan signal to the plurality of scan lines G1-Gn to drive the pixel units P to perform image display, or when the display panel 10 stops image display, the self-test control unit 141 receives a control signal and transmits the control signal to the scan driving circuit 15, where the control signal is used to control all the pixel units P to release the remaining charges at the same time.

The detection control unit 141 is configured to detect an image display condition of the display panel 10, stop outputting the control signal to the selection unit 142 when detecting that the display panel 10 performs image display, and output the control signal to the selection unit 142 when detecting that the display panel 10 stops image display.

Specifically, the detection control unit 141 includes a detection module 1411, the detection module 1411 is configured to detect an output cycle number of a trigger signal TP, the trigger signal TP is configured to control output of a Data signal Data, when the display panel 10 stops displaying an image and after the trigger signal TP is in a preset cycle, the Data signal Data stops being output to the pixel unit P, the level conversion circuit 13 stops outputting the clock signal CLK, and after the detection module 1411 detects that the trigger signal TP is in the preset cycle, the detection module 1411 controls output of the control signal to the selection unit 142.

In one embodiment, the detecting module 1411 includes a clock counter S, the clock counter S is connected to a trigger start terminal (not identified) of the Data driving circuit 12, the Data driving circuit 12 is configured to output a Data signal Data to the pixel unit P after receiving a trigger signal TP received by the trigger start terminal, the clock counter S is configured to count a period of the trigger signal TP when the display panel 10 stops displaying an image, and output a counting signal after counting that the trigger signal is in a predetermined period, and the counting signal controls the detecting module to output a control signal.

In an exemplary embodiment, the detection module can also control the switch tube T to be turned on according to the power output condition by detecting the power output condition of the display panel 10, so as to output a control signal, and certainly can also detect other signals, without limitation.

The detection control unit further comprises a first resistor R1 and a switch tube T, wherein the clock counter S is connected to a grid electrode of the switch tube T, a source electrode of the switch tube T is connected to a first voltage end through the first resistor R1, a drain electrode of the switch tube T is connected to the selection unit 142, the switch tube is conducted after receiving the counting signal, and a first voltage V1 output by the first voltage end VT1 is output through the source electrode and the drain electrode of the switch tube T and is transmitted to the selection unit as a control signal. That is, one end of the first resistor R1 is connected to the source electrode of the switching tube T, and the other end thereof is connected to the first voltage terminal VT1, and is configured to receive the first voltage V1 and transmit the first voltage to the source electrode of the switching tube T, where the first voltage is the turn-on voltage VGH of the TFT in the pixel unit P. When the switch tube T is turned on, the turn-on voltage VGH is transmitted to the drain through the source of the switch tube T and is output through the drain of the switch tube T. The drain of the switch tube T is connected to the selection unit 142 for outputting a control signal to the selection unit 142.

The detection control unit 141 further includes a second resistor R2, where the second resistor R2 is connected between the drain of the switch tube T and the ground terminal, and is used for providing the ground potential for the selection unit when the switch tube T is turned off, and adjusting the length of the preset time period of the control signal when the switch tube T is turned on.

The selecting unit 142 includes a plurality of or gates Y1 to Yn arranged in sequence, first input terminals (not labeled) of the plurality of or gates Y1 to Yn are respectively connected to the drain of the switching transistor T for receiving the control signal, second input terminals (not labeled) of the plurality of or gates Y1 to Yn are connected to the level converting circuit 13 for receiving the clock signal CLK from the level converting circuit 13, output terminals (not labeled) of the plurality of or gates Y1 to Yn are connected to the scan driving circuit 15 for outputting the clock signal CLK from the output terminals to the scan driving circuit 15 to drive the scan driving circuit 15 to output the scan signal to the pixel unit P, and control the pixel unit P to display an image, or output the control signal to the scan driving circuit 15, and drive the scan driving circuit to simultaneously output the scan signal to all the pixel units within a predetermined time period, so as to control all the pixel units to simultaneously release the remaining charges.

When the switch tube T is turned off, the first input terminals of the plurality of or gates Y1 to Yn are connected to the ground terminal via the second resistor R2 for controlling the potential of the first input terminals to be maintained at the ground potential, and the second input terminals of the plurality of or gates Y1 to Yn receive the clock signal CLK from the level conversion circuit 13 and output the clock signal CLK to the scan driving circuit 15 for controlling the pixel unit P to display an image via the scan driving circuit 15.

For example, a first input terminal of the first or gate Y1 is connected to the detection control unit 141 for receiving the control signal output by the detection control unit, a second input terminal of the first or gate Y1 is connected to the level shift circuit 13, and an output terminal of the first or gate Y1 is connected to the scan driving circuit 15 and connected to the first scan line G1 through the scan driving circuit 15, and is used for outputting the clock signal or the control signal to the control scan driving circuit 15 to control the scan driving circuit 15 to output the first scan signal to the first scan line G1.

A first input terminal of the second or gate Y2 is connected to the detection control unit 141 for receiving the control signal output by the detection control unit, a second input/output terminal of the second or gate Y2 is connected to the level shifter circuit 13, and an output terminal of the second or gate Y2 is connected to the scan driving circuit 15 and connected to the second scan line G2 via the scan driving circuit 15, for outputting the clock signal or the control signal to the control scan driving circuit 15, so as to control the scan driving circuit 15 to output the second scan signal to the second scan line G2.

A first input terminal of the third or gate Y3 is connected to the detection control unit 141 for receiving the control signal output by the detection control unit, a second input/output terminal of the third or gate Y3 is connected to the level shifter circuit 13, and an output terminal of the third or gate Y3 is connected to the scan driving circuit 15 and is connected to the third scan line G3 through the scan driving circuit 15, for outputting the clock signal or the control signal to the control scan driving circuit 15, so as to control the scan driving circuit 15 to output the third scan signal to the third scan line G3.

Similarly, a first input terminal of the nth or gate Yn is connected to the detection control unit 141 for receiving the control signal output by the detection control unit, a second input/output terminal of the nth or gate Yn is connected to the level shift circuit 13, and an output terminal of the nth or gate Yn is connected to the scan driving circuit 15 and connected to the nth scan line Gn through the scan driving circuit 15 for outputting the clock signal or the control signal to the control scan driving circuit 15 to control the scan driving circuit 15 to output the nth scan signal to the nth scan line Gn.

Referring to fig. 5, fig. 5 is a timing diagram illustrating output of the trigger signal and the scan signal in fig. 4.

As shown in fig. 5, when the detecting module 1411 is a clock counter S and detects the trigger signal TP, the display condition of the display panel 10 is detected. In a period in which the trigger signal TP is continuously output, that is, in the first period T1 to the kth period Tk, the Data driving circuit 12 outputs the Data signal Data under the control of the trigger signal TP to drive the pixel unit P to perform image display, at this time, the clock counter S detects that the trigger signal TP is in a period of normal output, the detection module 1411 does not output a detection signal, that is, a count signal to the switching tube T, controls the switching tube T to be in an off state, first input terminals of the or gates Y1 to Yn are connected to the ground terminal E through the second resistor R2 to maintain a low voltage state, second input terminals of the or gates Y1 to Yn are connected to the level conversion circuit 13, and are configured to receive the clock signal CLK from the level conversion circuit 13 and output the clock signal CLK from the output terminals to the scan driving circuit 15, so as to control the scan driving circuit 15 to output the scan signals to the correspondingly connected scan lines G1 to Gn, and control the pixel unit P to receive the Data signal Data to perform image display.

In the (k + 1) th to nth periods Tk +1 to Tn, the display panel 10 stops displaying, the clock counter S captures the nth period Tn which is the last cycle of the trigger signal TP, the Data driving circuit 12 stops outputting the Data signal Data when the trigger signal TP is in the last cycle, the level conversion circuit 13 stops outputting the clock signal CLK, the detection control unit 141 outputs a control signal to the first input terminals of the plurality of or gates in the selection unit 142, and controls the scan driving circuit 15 to output instantaneous scan signals through the plurality of or gates Y1 to Yn to control the TFTs in the pixel units P to be turned on, thereby releasing the charges remaining in the pixel units P.

Specifically, in the nth time period Tn, the detection module 1411 recognizes that the trigger signal TP is in the last cycle, at this time, the clock signal counter 1521 outputs the detection signal to the gate of the switch tube T, so as to control the switch tube T to be turned on, the switch tube T receives the turn-on voltage VGH from the source and outputs the turn-on voltage VGH as the control signal to the first input terminals of the plurality of or gates Y1 to Yn in the selection unit 142 through the drain, at this time, the level conversion circuit 13 has stopped outputting the clock signal CLK, the TFTs in the pixel units P are in the off state, the turn-on voltage VGH is transmitted to the scan driving circuit 15 and the plurality of scan lines G1 to Gn through the output terminals of the or gates Y, so as to control the TFTs in all the pixel units P to be in the on state, and at this time, the charges remaining in the liquid crystal capacitor C1 and the storage capacitor C2 are released.

Through the setting of the reset circuit, when the display panel stops displaying images, the TFT in the pixel unit is controlled to be opened, so that charges reserved in the pixel unit are released, the liquid crystal returns to the original position, and the problem of shutdown ghost shadow is effectively solved.

It should be understood that the application of the present invention is not limited to the above examples, and that modifications or changes can be made by those skilled in the art based on the above description, and all such modifications and changes are intended to fall within the scope of the appended claims.

Claims (10)

1. A display panel comprises a scanning driving circuit, a plurality of scanning lines extending along a first direction and arranged along a second direction, and a plurality of pixel units arranged in an array, wherein the scanning driving circuit is used for outputting scanning signals to the pixel units so as to control the pixel units to receive data signals for image display to perform image display;

the display panel further comprises a reset circuit, wherein the reset circuit is electrically connected to the scan driving circuit and is used for simultaneously controlling all the pixel units to release the charges corresponding to the data signals within a preset time period through the scan driving circuit and the plurality of scan lines when the display panel is detected to stop displaying the image.

2. The display panel of claim 1,

the display panel further comprises a level conversion circuit, the level conversion circuit is connected with the reset circuit and is used for outputting a plurality of clock signals with different phases to the reset circuit when the display panel performs image display and transmitting the clock signals to the scanning driving circuit through the reset circuit, the scanning driving circuit outputs the scanning signals to the pixel units according to the clock signals, and the level conversion circuit stops outputting the clock signals to the scanning driving circuit when the display panel stops image display;

the reset circuit comprises a selection unit and a detection control unit, wherein the selection unit is electrically connected with the detection control unit, the level conversion circuit and the scanning drive circuit and used for receiving the clock signal from the level conversion circuit and transmitting the clock signal to the scanning drive circuit so as to drive the pixel unit to display an image, or receiving a control signal from the detection control unit and outputting the control signal to the scanning drive circuit, and the control signal is used for controlling all the pixel units to release the reserved charges at the same time.

3. The display panel according to claim 2, wherein the detection control unit is configured to detect an image display condition of the display panel, stop outputting the control signal to the selection unit when it is detected that the display panel performs image display, and output the control signal to the selection unit when it is detected that the display panel stops the image display.

4. The display panel according to claim 3, wherein the detection control unit includes a detection module for detecting an output cycle number of a trigger signal for controlling the output of the data signal, when the display panel stops displaying an image and after the trigger signal is a preset cycle, the data signal stops being output to the pixel unit, and the level conversion circuit stops outputting the clock signal;

after the detection module detects that the trigger signal is in the preset period, the detection module controls the control signal to be output to the selection unit.

5. The display panel according to claim 4, wherein the detection module comprises a clock counter, the clock counter is connected to a trigger start terminal of a data driving circuit, the data driving circuit is configured to output the data signal to the pixel unit after receiving a trigger signal received by the trigger start terminal, the clock counter is configured to count a period of the trigger signal when the display panel stops displaying an image, and the clock counter outputs a count signal when the trigger signal is counted to be in the preset period, the count signal controls the detection module to output the control signal.

6. The display panel according to claim 5, wherein the detection control unit further comprises a first resistor and a switching tube, the clock counter is connected to a gate of the switching tube, a source of the switching tube is connected to a first voltage terminal through the first resistor, and a drain of the switching tube is connected to the selection unit;

and the switch tube is conducted after receiving the counting signal, and a first voltage output by the first voltage end is output through a source electrode and a drain electrode of the switch tube and is transmitted to the selection unit as the control signal.

7. The display panel of claim 6, wherein the detection control unit further comprises a second resistor connected between a drain of the switch tube and a ground terminal for providing a ground potential to the selection unit when the switch tube is turned off and for adjusting the length of the preset time period of the control signal when the switch tube is turned on.

8. The display panel according to claim 7, wherein the selection unit includes a plurality of or gates arranged in sequence, first input terminals of the or gates are respectively connected to the drains of the switching transistors for receiving the control signal, second input terminals of the or gates are connected to the level conversion circuit for receiving the clock signal, and output terminals of the or gates are connected to the scan driving circuit for outputting the clock signal to the scan driving circuit to drive the scan driving circuit to output a scan signal to the pixel units, control the pixel units to display images, or output the control signal to the scan driving circuit to drive the scan driving circuit to simultaneously output a scan signal to all the pixel units within a preset time period, so as to control all the pixel units to release the remaining charges simultaneously.

9. The display panel according to claim 8, wherein when the switch is turned off, the first input terminals of the plurality of or gates are connected to the ground terminal through the second resistor for controlling the potential of the first input terminals to be maintained at the ground potential, and the second input terminals of the plurality of or gates receive the clock signal from the level shifter circuit and output the clock signal to the scan driver circuit for controlling the pixel units to display images through the scan driver circuit.

10. A display terminal, comprising a timing control circuit, a data driving circuit and the display panel of any one of claims 1 to 9, wherein the timing control circuit is configured to output a gate output control signal to the scan driving circuit and a source output control signal to the data driving circuit to control the scan driving circuit to output the scan signal to the pixel unit and control the data driving circuit to output a data signal to the pixel unit, and the pixel unit performs image display according to the scan signal and the data signal.

Images