CN218385186U

CN218385186U - Semiconductor packaging structure

Info

Publication number: CN218385186U
Application number: CN202222634768.7U
Authority: CN
Inventors: 马磊; 张帅
Original assignee: Chengdu Fujin Power Semiconductor Technology Development Co ltd
Current assignee: Chengdu Fujin Power Semiconductor Technology Development Co ltd
Priority date: 2022-10-08
Filing date: 2022-10-08
Publication date: 2023-01-24
Anticipated expiration: 2032-10-08

Abstract

The utility model discloses a semiconductor packaging structure, which belongs to the technical field of chip packaging and comprises a base, an insulating substrate and a semiconductor chip from bottom to top in sequence, wherein the semiconductor chip is plastically packaged by a plastic packaging layer; a groove is formed in one surface, away from the semiconductor chip, of the insulating substrate, metal blocks are manufactured in the groove and are in surface contact with the base, and gaps exist among the metal blocks and/or between the metal blocks and the side walls of the groove. The groove is formed in the back surface of the substrate, the metal block is manufactured, a combined structure of air and the metal block is formed, and the dielectric constant of the substrate is reduced through the air layer, so that the packaging structure is guaranteed to have lower parasitic capacitance; meanwhile, the thermal resistance from the semiconductor chip to the environment is reduced through the metal block, so that the whole packaging structure is compatible with low thermal resistance and low parasitic capacitance, and the working stability and reliability of the semiconductor chip are improved.

Description

Semiconductor packaging structure

Technical Field

The utility model relates to a chip package technical field especially relates to a semiconductor package structure.

Background

The package refers to a housing for mounting a semiconductor integrated circuit chip. The chip is arranged, adhered, fixed and connected on the frame by a series of technologies, the wiring terminal is led out and is encapsulated and fixed by a plastic insulating medium to form the integral three-dimensional structure, namely, a shell is added on the chip and fixed on the circuit board. The package has the functions of placing, fixing, sealing, protecting the chip and enhancing the electrothermal performance, and is also a bridge for communicating the internal world of the chip with an external circuit, wherein the connection points on the chip are connected to the pins of the package shell by leads, and the pins are connected with other devices by leads on the printed board. Therefore, packaging plays an important role for integrated circuits.

In the conventional package structure, a semiconductor chip is generally mounted on an insulating substrate, and the insulating substrate is mounted on a heat dissipation base plate, and the package structure has the following defects: (1) excessive device-to-ambient thermal resistance; and (2) the package parasitic capacitance is large.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to overcome prior art's problem, provide a semiconductor package structure.

The purpose of the utility model is realized through the following technical scheme: a semiconductor packaging structure comprises a base, an insulating substrate and a semiconductor chip from bottom to top in sequence, wherein the semiconductor chip is plastically packaged by a plastic packaging layer; a groove is formed in one surface, away from the semiconductor chip, of the insulating substrate, metal blocks are manufactured in the groove and are in surface contact with the base, and gaps exist among the metal blocks and/or between the metal blocks and the side walls of the groove.

In one example, a plurality of grooves are formed in a surface of the insulating substrate away from the semiconductor chip, and one metal block is arranged in each groove or a plurality of metal blocks are arranged at intervals.

In one example, the plurality of metal blocks are uniformly spaced in the groove.

In one example, the metal block is made of any one of Cu, ti, al, ni, and Au.

In one example, a circuit layer is disposed between the insulating substrate and the semiconductor chip.

In one example, when a plurality of semiconductor chips are packaged, the semiconductor chips are interconnected through a lead and a circuit layer.

In one example, the thickness of the plastic packaging layer is greater than or equal to the sum of the thickness of the semiconductor chip and the thickness of the circuit layer.

In one example, the molding layer is made of epoxy resin.

In one example, the insulating substrate is a substrate made of AlN or Al2O 3.

In one example, the substrate is a metal substrate made of any one of Cu, ti, al, ni, and Au.

It should be further noted that the technical features corresponding to the above examples can be combined with each other or replaced to form a new technical solution.

Compared with the prior art, the utility model discloses beneficial effect is:

the utility model forms a combined structure of air and metal blocks by slotting the back of the substrate and manufacturing the metal blocks, and replaces partial structure of the substrate by the air layer with low dielectric constant, thereby ensuring that the packaging structure has lower parasitic capacitance; meanwhile, the thermal resistance from the semiconductor chip to the environment is reduced through the metal block, so that the whole packaging structure is compatible with low thermal resistance and low parasitic capacitance, and the working stability and reliability of the semiconductor chip are improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention.

Fig. 1 is a schematic diagram of the packaging structure obtained in step S1 of the packaging structure preparation method of the present invention;

fig. 2 is a schematic view of the packaging structure obtained in step S2 of the packaging structure preparation method of the present invention;

FIG. 3 is a schematic view of the package structure obtained in step S3 of the package structure manufacturing method of the present invention;

fig. 4 is a schematic view of the final package structure obtained in step S4 of the package structure manufacturing method of the present invention.

In the figure: 1-base, 2-insulating base plate, 3-semiconductor chip, 4-plastic package layer, 5-groove, 6-metal block, 7-circuit layer and 8-lead.

Detailed Description

The technical solutions of the present invention will be described more clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts all belong to the protection scope of the present invention.

In the description of the present invention, it should be noted that the directions or positional relationships indicated by "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like are the directions or positional relationships indicated on the basis of the drawings, and are only for convenience of description and simplification of the description, but not for indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, ordinal words (e.g., "first and second," "first through fourth," etc.) are used to distinguish between objects, and are not limited to the order, but rather are to be construed to indicate or imply relative importance.

In the description of the present invention, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Furthermore, the technical features mentioned in the different embodiments of the invention described below can be combined with each other as long as they do not conflict with each other.

In one example, the semiconductor packaging structure sequentially comprises a base, an insulating substrate and a semiconductor chip from bottom to top, wherein the semiconductor chip is plastically packaged by a plastic packaging layer; specifically, one or more semiconductor chips are distributed on the front surface of the insulating substrate, at least one groove is formed in the back surface of the insulating substrate, the depth of the groove is smaller than or equal to the thickness of the insulating substrate, at least one metal block is manufactured in the groove, the metal block is in contact with the insulating substrate and the base, and gaps exist between the metal blocks and/or between the metal block and the side wall of the groove, so that a combined structure of air and the metal block is formed. Specifically, when only one metal block is manufactured in the groove on the back surface of the insulating substrate, gaps exist between two sides of the metal block and the side wall of the groove; when a plurality of metal blocks are manufactured in the groove on the back surface of the insulating substrate, gaps exist among the metal blocks, and gaps exist between the two metal blocks close to the side wall of the groove and the side wall of the groove.

The utility model forms a combined structure of air and metal blocks by slotting the back of the substrate and manufacturing the metal blocks, reduces the dielectric constant of the substrate through the air layer, and further ensures that the packaging structure has lower parasitic capacitance; meanwhile, heat generated by the semiconductor chip can be more quickly transferred to the heat dissipation base through the metal block, so that the thermal resistance of the semiconductor chip to the environment is reduced, the whole packaging structure is compatible with low thermal resistance and low parasitic capacitance, and the working stability and reliability of the semiconductor chip are improved.

In one example, the back surface of the insulating substrate is provided with a plurality of grooves, and one metal block is arranged in each groove or a plurality of metal blocks are arranged at intervals. Preferably, a plurality of metal blocks are arranged in each groove at intervals, so that the parasitic capacitance and the thermal resistance of the packaging framework are greatly reduced. Furthermore, a plurality of metal blocks in each groove are uniformly distributed at intervals, so that the supporting performance of the insulating substrate can be ensured while the parasitic capacitance and the thermal resistance of the packaging framework are reduced to the maximum extent.

In one example, the metal block is a metal block made of any one of Cu, ti, al, ni, and Au, or an alloy metal block made of a plurality of materials. When the metal block is an alloy metal block, the metal block is made of the existing alloy material, such as a Ni-Au alloy material, a Ti-Cu alloy material and the like, and has good heat-conducting property.

In one example, a circuit layer is disposed between the insulating substrate and the semiconductor chip for interconnecting the chips.

In one example, when a plurality of semiconductor chips are packaged in the package structure of the present invention, the semiconductor chips are interconnected through the leads and the circuit layer. Specifically, the back surface of each semiconductor chip is interconnected with the circuit layer, the front surface of the first semiconductor chip is connected to the circuit layer interconnected with the second chip through a lead, the front surface of the second chip is connected to the circuit layer interconnected with the third chip through a lead, and so on, so that the interconnection of the chips is realized, and the corresponding chip functions are realized.

In one example, the thickness of the plastic packaging layer is greater than or equal to the sum of the thickness of the semiconductor chip and the thickness of the circuit layer, so that the semiconductor chip is packaged in a small size for thinning the packaging structure, and the thickness of the plastic packaging layer is greater than the sum of the thickness of the semiconductor chip and the thickness of the circuit layer by 1-2 μm.

In one example, the plastic package layer is made of epoxy resin, has the characteristics of light weight, high strength, good corrosion resistance, excellent electrical property, shock absorption and the like, and can better meet the chip packaging requirements.

In one example, the insulating substrate is a substrate made of AlN or Al2O3, preferably AlN.

In one example, the substrate is a metal substrate made of any one of Cu, ti, al, ni, and Au, or an alloy metal substrate made of a plurality of materials, preferably a Cu substrate, and has excellent thermal conductivity and low cost.

The above examples are combined to obtain a preferred example of the present invention, as shown in fig. 4, the heat dissipation base 1 made of Cu, the insulating substrate 2 made of AlN, the circuit layer 7 and two semiconductor chips 3 are sequentially included from bottom to top, and the two semiconductor chips 3 are interconnected through the lead 8 and the circuit layer 7 and are plastically encapsulated by the plastic encapsulation layer 4; a plurality of grooves 5 are formed in the reverse side of the insulating substrate 2, a plurality of metal blocks 6 are manufactured in the grooves 5, the metal blocks 6 are in contact with the insulating substrate 2 and the heat dissipation base 1, and gaps exist between the metal blocks 6 and the side walls of the grooves 5.

To illustrate the technical concept of the present invention, a method for manufacturing a preferred exemplary semiconductor package structure will now be described, the method comprising the steps of:

s1: as shown in fig. 1, the semiconductor chip 3 is arranged on the surface of the insulating substrate 2 through the circuit layer 7, and then the interconnection between the chips is realized through the lead 8;

s2: as shown in fig. 2, the bottom of the insulating substrate 2 is grooved to form a groove 5, and the groove depth is less than or equal to the substrate thickness;

s3: manufacturing metal blocks 6 at the bottom of the insulating substrate 2, wherein gaps (air layers) exist between the metal blocks 6 and/or between the metal blocks 6 and the side walls of the groove 5; specifically, as shown in fig. 3, the metal block 6 fabrication includes the following sub-steps:

s31: sputtering a seed layer, preferably a seed layer made of Ti/Cu material, in the groove 5;

s32: performing mask processing on the seed layer corresponding to the air layer part by adopting the photoresist, namely exposing the seed layer corresponding to the position of the metal block 6 to be manufactured;

s33: carrying out sputtering electroplating treatment, preferably electroplating Cu, on the seed layer corresponding to the position of the metal block 6 to be manufactured;

s34: removing the electroplated metal on the photoresist, preferably removing by adopting a corrosion mode;

s35: removing the photoresist and the redundant seed layer outside the position of the metal block 6 to obtain the metal block 6 made of Ti/Cu material; wherein, the photoresist is preferably removed by wet etching.

S4: installing a heat dissipation bottom plate; specifically, as shown in fig. 4, the surface of the heat-dissipating base plate is in contact with the bottom surface of the metal block 6 for heat transfer.

The above detailed description is the detailed description of the present invention, and it can not be considered that the detailed description of the present invention is limited to these descriptions, and to the ordinary skilled person in the art to which the present invention belongs, without departing from the concept of the present invention, a plurality of simple deductions and replacements can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims

1. A semiconductor package structure, characterized in that: the semiconductor chip is plastically packaged by a plastic packaging layer; a groove is formed in one surface, away from the semiconductor chip, of the insulating substrate, metal blocks are manufactured in the groove and are in contact with the surface of the base, and gaps exist among the metal blocks and/or between the metal blocks and the side wall of the groove.

2. The semiconductor package structure of claim 1, wherein: a plurality of grooves are formed in one surface, far away from the semiconductor chip, of the insulating substrate, and a metal block is arranged in each groove or a plurality of metal blocks are arranged at intervals.

3. The semiconductor package structure of claim 2, wherein: a plurality of metal blocks in the groove are evenly distributed at intervals.

4. The semiconductor package structure of claim 1, wherein: the metal block is made of any one of Cu, ti, al, ni and Au.

5. The semiconductor package structure of claim 1, wherein: a circuit layer is arranged between the insulating substrate and the semiconductor chip.

6. The semiconductor package structure of claim 5, wherein: when a plurality of semiconductor chips are packaged, the semiconductor chips are interconnected through leads and circuit layers.

7. The semiconductor package structure of claim 5, wherein: the thickness of the plastic packaging layer is larger than or equal to the sum of the thickness of the semiconductor chip and the thickness of the circuit layer.

8. The semiconductor package structure of claim 1, wherein: the plastic packaging layer is made of epoxy resin.

9. The semiconductor package structure of claim 1, wherein: the insulating substrate is made of AlN or Al2O 3.

10. The semiconductor package structure of claim 1, wherein: the base is a metal bottom plate made of any one of Cu, ti, al, ni and Au.