CN218351440U - SMD encapsulation shell of multichannel signal protection type low-capacitance TVS array ceramic - Google Patents
SMD encapsulation shell of multichannel signal protection type low-capacitance TVS array ceramic Download PDFInfo
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- CN218351440U CN218351440U CN202222884861.3U CN202222884861U CN218351440U CN 218351440 U CN218351440 U CN 218351440U CN 202222884861 U CN202222884861 U CN 202222884861U CN 218351440 U CN218351440 U CN 218351440U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
Abstract
The utility model provides a multi-path signal protection type low-capacitance TVS array ceramic surface mount package shell; comprises a ceramic base, a sealing ring and a cover plate; the utility model reasonably arranges the positions of the chip bonding area and the bonding wire area by slotting or protruding in the ceramic base as the heat sink area and the bonding area, thereby reducing the packaging difficulty of the rear process; the chip and the bottom of the bonding area adopt the processes of whole metal gold plating and local nickel plating, and the processes of whole metal gold plating and local nickel plating.
Description
Technical Field
The utility model relates to a SMD encapsulation shell of multichannel signal protection type low capacitance TVS array ceramic and packaging method thereof.
Background
At present, high-power TVS pipe mostly is single tube package, and the knot electric capacity is great, can use a plurality of single tube devices to superpose in general design and use often, satisfying under the product electrical property index requirement, the product needs a plurality of single tube devices to superpose and uses, and this will lead to PCB face area increase, installation technology step is many, and the compatibility is low. In order to solve the problems, a multipath integrated array product is developed, a multipath signal protection type low-capacitance TVS array ceramic surface mount packaging structure and a packaging method are developed for solving the packaging problem of the product, and the packaging problem is solved directly through packaging. So as to meet the application requirement of high-reliability and high-performance array TVS tube package.
The utility model relates to a small-size ceramic package part of high power density, high reliability diode array. The series of ceramic parts are mainly used for the metal ceramic paster packaging shell parts of the high-reliability low-capacitance transient protection diode array. The ceramic packaging component is a typical representative of a miniaturized and integrated ceramic packaging part of an analog hybrid integrated circuit, and can meet the requirements of high reliability, high integration and technical requirements of electronic components on appearance packaging products in scientific research and production.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model provides a packaging structure of low knot electric capacity TVS array product of multichannel signal protection type. According to the performance of the electronic components and the conduction requirements of the products on heat and current, the designed array product capable of simultaneously protecting multiple signals has the characteristics of high power density, small parasitic capacitive reactance/inductive reactance/impedance, capability of simultaneously protecting 3 signal lines and the like (the single-path borne power can reach 3000W). Can well meet the high reliability requirement and the technical requirement on products with the same type of appearance in scientific research and production.
The utility model discloses a following technical scheme can realize.
The utility model provides a multi-path signal protection type low-capacitance TVS array ceramic surface mount package shell; comprises a ceramic base, a sealing ring and a cover plate;
the ceramic base is provided with at least one heat sink area and at least one bonding area on the upper end surface, at least two electrodes are arranged on the lower end surface, and through holes are formed among the heat sink area, the bonding area and the electrodes;
the sealing ring and the ceramic base have the same cross section shape;
a bulge is processed on one end surface of the cover plate, and the shape and the size of the bulge are the same as those of the inner ring of the sealing ring;
the bottoms of the heat sink area and the bonding area are covered by a metal layer, conductive columns are condensed in the through holes, and the conductive columns are used for respectively connecting the electrodes and the metal layer;
the heat sink area and the bonding area are grooves or bulges processed on the chip A.
The heat sink area comprises a first heat sink area, a second heat sink area, a third heat sink area, a fourth heat sink area and a fifth heat sink area, the fifth heat sink area is processed in the center of the chip A, and the first heat sink area, the second heat sink area, the third heat sink area and the fourth heat sink area evenly surround the fifth heat sink area.
And a first bonding area and a second bonding area are respectively processed beside the opposite two ends of the fifth heat sink area.
The electrode comprises a first electrode, a second electrode, a third electrode and a fourth electrode, the first electrode is respectively connected with metal layers on the first heat sink area and the second heat sink area through two conductive columns, the second electrode is respectively connected with the metal layers on the third heat sink area and the fourth heat sink area through two conductive columns, the third electrode is respectively connected with the metal layers on the first bonding area and the second bonding area through two conductive columns, and the fourth electrode is connected with the metal layer on the second bonding area through the conductive columns.
The metal layer comprises a metal block, a tungsten or molybdenum-manganese coating is processed on the metal block and the ceramic base, a gold coating is formed on the surface of the metal block, and a nickel or nickel-cobalt or nickel-phosphorus coating is further arranged between the gold coating and the metal block.
The shape and size of the cross section of the heat sink area are the same as the shape and size of the cross section of the chip.
The beneficial effects of the utility model reside in that: the positions of a chip bonding area and a bonding wire area are reasonably distributed by slotting or protruding in the ceramic base to serve as a heat sink area and a bonding area, so that the packaging difficulty of the rear process of the chip is reduced; the chip and the bottom of the bonding area adopt the processes of whole metal gold plating and local nickel plating, and the processes of whole metal gold plating and local nickel plating.
Drawings
FIG. 1 is a schematic structural view of a ceramic base according to the present invention;
figure 2 is a cross-sectional view taken along line a of figure 1 in accordance with the present invention;
figure 3 is a cross-sectional view taken along line b of figure 1 in accordance with the present invention;
FIG. 4 is a schematic view of the bottom structure of the ceramic base according to the present invention;
FIG. 5 is a schematic view of the tube core mounting structure of the present invention;
fig. 6 is a schematic view of the cover plate structure of the present invention;
FIG. 7 is a schematic view of the connection structure inside the tube core of the present invention;
fig. 8 is a schematic structural view of a ceramic base according to embodiment 2 of the present invention;
fig. 9 is a schematic cross-sectional view of fig. 8 according to the present invention;
fig. 10 is a schematic structural view of a ceramic base according to embodiment 2 of the present invention;
in the figure: 1-ceramic base, 2-through hole, 3-sealing ring, 4-heat sink area, 5-cover plate, 6-chip A, 7-soldering lug, 8-copper sheet, 9-chip B, 10-tungsten copper pressing block, 11-first heat sink area, 12-second heat sink area, 13-third heat sink area, 14-fourth heat sink area, 15-fifth heat sink area, 16-first bonding area, 17-second bonding area, 18-first electrode, 19-second electrode, 20-third electrode and 21-fourth electrode.
Detailed Description
The technical solution of the present invention is further described below, but the scope of the claimed invention is not limited to the described.
This patent is starting from CBCC encapsulation, has designed the flat cermet packaging structure of the novel multichannel of two types, and rationally distributed chip bonding region and bonding wire district position in the design to reduce its rear portion technology encapsulation degree of difficulty, improve the stability and the reliability of product.
According to the circuit installation requirement, the ceramic base except 4 electrode blocks and other parts are all ceramic, and meanwhile, a multilayer ceramic piece is welded with the frame 3, so that the requirement of insulativity and air tightness of the device is met.
The bottom of the heat sink area adopts the whole metal gold plating and local nickel plating process, and the bonding area is plated with nickel, so that the conduction problem of heat and transient large current of the ceramic part and the gold-aluminum bonding problem are solved, and the high power density and the integration level of the type of packaging are improved.
Example 1: as shown in fig. 8 to 10, the dimensions of the ceramic base are 9.1mm × 9.4mm × 4.4mm, and the dimensions of the closed cavity formed by the sealing ring and the cover plate are 7.2mm × 7.9mm;
as shown in fig. 10, the heat sink region and the bonding region are bosses on the ceramic base, the first bonding region and the second bonding region are respectively processed at two end edges of the ceramic base, the first heat sink region 11, the second heat sink region 12, the third heat sink region 13, the fourth heat sink region 14 are respectively processed at two side edges of the ceramic base, and the fifth heat sink region is processed at the center of the ceramic base;
a through hole is processed on the ceramic base to respectively communicate the bonding area and the heat sink area with the bottom of the ceramic base, the radius of the through hole is 0.5mm, the size of the through hole is 3.6mm multiplied by 0.8mm, and the filling materials of the through hole are all TU1 (oxygen-free copper); electroplating a layer of tungsten or molybdenum manganese with the thickness of 5um at the bottom of the heat sink area, placing the metal block on the coating, then electroplating nickel, nickel cobalt or nickel phosphorus with the thickness of 1.39um on the metal block, and electroplating gold with the thickness of 1.3um and the purity of more than or equal to 99.9 percent on the surface layer of the metal block. The coating material and structure of the bonding region are the same as those of the heat sink region, but the thickness of the surface layer material metal nickel, nickel cobalt or nickel phosphorus is 1.3um, and the thickness of the material metal tungsten or molybdenum manganese between the metal block and the ceramic is 5um.
Example 2: as shown in fig. 1 to 4, the dimensions of the ceramic base are 15.1mm × 1.5mm × 4.7mm, and the dimensions of the closed cavity formed by the sealing ring and the cover plate are 13.7mm × 10.9mm;
as shown in fig. 1, the heat sink area and the bonding area are recessed platforms on the ceramic base, the first heat sink area 11, the second heat sink area 12, the third heat sink area 13, and the fourth heat sink area 14 are respectively processed on four corners of the ceramic base, the fifth heat sink area is processed in the center of the ceramic base, and the first bonding area and the second bonding area are respectively processed on two side edges of the ceramic base;
a through hole is processed on the ceramic base to respectively communicate the bonding area and the heat sink area with the bottom of the ceramic base, the radius of the through hole is 0.5mm, the size of the through hole is 3.6mm multiplied by 0.8mm, and the filling materials of the through hole are all TU1 (oxygen-free copper); electroplating a layer of tungsten or molybdenum manganese with the thickness of 30um at the bottom of the heat sink area, placing the metal block on the plating layer, then electroplating nickel, nickel cobalt or nickel phosphorus with the thickness of 8.9um on the metal block, and electroplating gold with the thickness of 5.7um and the purity of more than or equal to 99.9 percent on the surface layer of the metal block. The coating material and structure of the bonding region are the same as those of the heat sink region, but the thickness of the surface layer material metal nickel, nickel cobalt or nickel phosphorus is 8.9um, and the thickness of the material metal tungsten or molybdenum manganese between the metal block and the ceramic is 30um.
Example 3: a packaging method of a multi-channel signal protection type low-capacitance TVS array ceramic surface mount type packaged ceramic base product takes a packaging scheme of a high-power low-capacitance TVS array device module as an example, and comprises the following specific steps:
(1) Cleaning the ceramic base:
(1) firstly, carrying out wet cleaning on the ceramic base, and baking by using vacuum or nitrogen: the packaging ceramic base is firstly soaked in acetone for 10 minutes, then is subjected to ultrasonic low-frequency cleaning for 3 minutes, is washed by conventional water for 5 minutes, is washed by ionized water for 10 minutes, and is finally dehydrated by alcohol. The baking was completed using a nitrogen oven at 60 ℃.
(2) Before use, the ceramic base is subjected to argon plasma cleaning; the specific scheme is as follows: the argon plasma cleaning power is preferably set to 100W, the argon flow rate is not more than 50SCCM, the cleaning time is preferably set to 180s, and the ceramic susceptor is used up within 24 hours after each cleaning.
(2) Preparing a power chip to be packaged and selecting a welding material as a high-temperature welding sheet;
(3) Mounting the chip according to the figure 5, firstly mounting a soldering lug 7 on each welding area line, secondly mounting a chip A6 and a chip B9 with the front side of the chip upward, placing the chip on the soldering lug of each welding area according to the position requirement, mounting an upper soldering lug 7 on the bottom chip A6 and the chip B9 in each independent area, mounting a copper sheet 8 on the soldering lug, then placing a tungsten-copper pressing block 10 on the copper sheet, and finally placing the assembled die in a vacuum sintering furnace for high-temperature sintering; heating to a preset temperature T1 at a set heating speed V1 under the condition of nitrogen, and keeping the temperature for T1 time; vacuumizing, vacuumizing for T1 time, then filling nitrogen again, setting a heating speed V2 to heat to a preset temperature T2, and keeping the temperature for T3 time; vacuumizing again, setting a heating speed V3 to a preset temperature T3 (highest temperature) after vacuumizing for T4 time, and keeping the temperature for T5 time; and (3) cooling, setting a cooling speed V4, filling nitrogen when the temperature is reduced to be below a melting point, cooling along with the furnace, and removing the pressing block to finish the sintering of the device. (temperature-rising rate relationship, V1 > V2 > V3 > V4).
(4) Placing the sintered module on a bonding machine, and performing wire bonding on electrodes and patterns on the upper chips and the inner surface of the ceramic base through interconnection materials to obtain an electrically interconnected module;
(5) And (3) putting the devices which are electrically interconnected in the step (5) into parallel seam welding equipment, mounting a cover plate (16) on the ceramic base, and sealing the ceramic base sealing ring (3) with the cover plate (5) to complete the module packaging of the multi-channel signal protection type low-capacitance TVS array module.
The chip is silicon-based, the back metallization layer can be Au, the maximum size of the chip is 4.0mm multiplied by 4.0mm, and the minimum size of the chip is 2.8mm multiplied by 2.8 mm. The packaging of the staggered structure is realized through the structural design, and an independent mounting chamber is formed for each chip, so that the assembly process becomes simple.
The bottom chip and the ceramic base are connected by using bottom solder, and the solder used for sintering the large chip is a preformed solid solder sheet with AuSn or PbSnAg components.
The welding flux used for connecting the bottom layer large chip and the ceramic base specifically comprises the following steps: the eutectic soldering temperature range of AuSn or PbSnAg solid soldering lug is 320-350 ℃, the soldering time is 30-150 s, and the soldering atmosphere is vacuum.
The welding sheet and the chip are positioned through the discrete structure of the part, and the chip and the welding sheet are installed by adopting a die bonder.
The ceramic base and the cover plate are connected through parallel seam welding to form the ceramic base, the cover plate is a metal cover plate (the component is 4J42 or 4J 29), the ceramic base and the cover plate are sealed in an airtight sealing mode, the content of water vapor in the sealed ceramic base and the sealed cover plate is less than or equal to 5000ppm, and the leakage rate after sealing is less than or equal to 1 x 10 < -3 > Pa cm < 3 >/s.
The power chip and the ceramic base are connected by metal wires, as shown in figure 7, A-A1-A2, B-B1-B2, C-C1-C2 and D-D1, the metal wires are made of silicon-aluminum wires, the wire diameter is larger than or equal to 380 mu m, and the number of the wires is 12.
Claims (6)
1. The utility model provides a SMD encapsulation shell of low electric capacity TVS array ceramic of multichannel signal protection type which characterized in that: comprises a ceramic base (1), a sealing ring (3) and a cover plate (5);
the device comprises a ceramic base (1), wherein at least one heat sink area and at least one bonding area are processed on the upper end surface of the ceramic base (1), at least two electrodes are arranged on the lower end surface of the ceramic base (1), and through holes (2) are processed between the heat sink area and the bonding area as well as between the heat sink area and the electrodes;
the sealing ring (3), the cross section shape of the sealing ring (3) is the same as that of the ceramic base (1);
a bulge is processed on one end face of the cover plate (5), and the shape and size of the bulge are the same as those of the inner ring of the sealing ring (3);
the bottoms of the heat sink area and the bonding area are covered by a metal layer, a conductive column is solidified in the through hole (2), and the conductive column respectively connects the electrode and the metal layer;
the heat sink area and the bonding area are grooves or bulges processed on the chip A (6).
2. The multi-channel signal protection type low-capacitance TVS array ceramic patch package housing of claim 1, wherein: the heat sink area comprises a first heat sink area (11), a second heat sink area (12), a third heat sink area (13), a fourth heat sink area (14) and a fifth heat sink area (15), wherein the fifth heat sink area (15) is processed in the center of the chip A (6), and the first heat sink area (11), the second heat sink area (12), the third heat sink area (13) and the fourth heat sink area (14) evenly surround the fifth heat sink area (15).
3. The multi-channel signal protection type low-capacitance TVS array ceramic patch package housing of claim 2, wherein: and a first bonding area (16) and a second bonding area (17) are respectively processed beside the opposite two ends of the fifth heat sink area (15).
4. The multi-channel signal protection type low-capacitance TVS array ceramic patch type package housing of claim 1, wherein: the electrode comprises a first electrode (18), a second electrode (19), a third electrode (20) and a fourth electrode (21), wherein the first electrode (18) is respectively connected with metal layers on a first heat sink area (11) and a second heat sink area (12) through two conductive columns, the second electrode (19) is respectively connected with metal layers on a third heat sink area (13) and a fourth heat sink area (14) through two conductive columns, the third electrode (20) is respectively connected with metal layers on a first bonding area (16) and a second bonding area (17) through two conductive columns, and the fourth electrode (21) is connected with the metal layer on the second bonding area (17) through the conductive columns.
5. The multi-channel signal protection type low-capacitance TVS array ceramic patch package housing of claim 1, wherein: the metal layer comprises a metal block, a tungsten or molybdenum-manganese coating is processed on the metal block and the ceramic base, a gold coating is formed on the surface of the metal block, and a nickel or nickel-cobalt or nickel-phosphorus coating is further arranged between the gold coating and the metal block.
6. The multi-channel signal protection type low-capacitance TVS array ceramic patch package housing of claim 1, wherein: the shape and size of the cross section of the heat sink area are the same as the shape and size of the cross section of the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222884861.3U CN218351440U (en) | 2022-10-31 | 2022-10-31 | SMD encapsulation shell of multichannel signal protection type low-capacitance TVS array ceramic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222884861.3U CN218351440U (en) | 2022-10-31 | 2022-10-31 | SMD encapsulation shell of multichannel signal protection type low-capacitance TVS array ceramic |
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| Publication Number | Publication Date |
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| CN218351440U true CN218351440U (en) | 2023-01-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222884861.3U Active CN218351440U (en) | 2022-10-31 | 2022-10-31 | SMD encapsulation shell of multichannel signal protection type low-capacitance TVS array ceramic |
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| CN (1) | CN218351440U (en) |
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2022
- 2022-10-31 CN CN202222884861.3U patent/CN218351440U/en active Active
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