CN218333783U

CN218333783U - Chip packaging structure

Info

Publication number: CN218333783U
Application number: CN202221530115.8U
Authority: CN
Inventors: 于鸿祺; 林俊荣; 古瑞庭
Original assignee: Walton Advanced Engineering Inc
Current assignee: Walton Advanced Engineering Inc
Priority date: 2022-06-17
Filing date: 2022-06-17
Publication date: 2023-01-17
Anticipated expiration: 2032-06-17

Abstract

The utility model discloses a chip packaging structure, this chip packaging structure contains a chip, an at least first dielectric layer, an at least second dielectric layer, an at least lead and connect circuit and an at least third dielectric layer, wherein each should lead and connect the circuit and utilize high dose silver cream or high dose copper cream to fill up and constitute in at least a first recess of each first dielectric layer and an at least second recess of each second dielectric layer, make at least one crystal pad of this chip can with each lead and connect circuit electric connection, in order to promote the electric conduction efficiency of each lead and connect the circuit, in addition, more accessible at least one crystal pad is formed in each first recess and correspond to be located each crystal pad on the surface with each crystal pad electric connection in order to protect each crystal pad and increase the product yield, in order to solve the problem that the credibility of current product descends, be favorable to increasing the market power competition of product.

Description

Chip packaging structure

Technical Field

The utility model relates to a chip packaging structure especially relates to a can increase chip packaging structure's electrically conductive efficiency and product yield's chip packaging structure.

Background

With the semiconductor process technology changing day by day, the conductive efficiency and the product yield of the existing chip package structure product can not meet the requirements of the manufacturing end or the consuming end, so that the quality of the existing chip package structure product in the market is low and the reliability is reduced.

Therefore, a chip package structure product capable of increasing the conductive efficiency and the product yield of the chip package structure to make the product have higher quality in the market and increase the reliability is a great expectation of the related industries at present.

SUMMERY OF THE UTILITY MODEL

The main objective of the present invention is to provide a chip package structure, which comprises a chip, at least one first dielectric layer, at least one second dielectric layer, at least one conductive trace and at least one third dielectric layer, wherein each conductive trace is formed by filling at least one first groove of each first dielectric layer and at least one second groove of each second dielectric layer with high-dose silver paste or high-dose copper paste, so that at least one die pad of the chip can be electrically connected to each conductive trace to improve the conductive efficiency of each conductive trace, and further, at least one bump for the die pad is formed in each first groove and correspondingly located on the surface of each die pad and electrically connected to each die pad to protect each die pad and increase the yield of the product, thereby effectively solving the problem of the existing chip package structure product that the quality is low in the market and the reliability is lowered.

To achieve the above objects, the present invention provides a chip package structure, which comprises a chip, at least one first dielectric layer, at least one second dielectric layer, at least one conductive trace and at least one third dielectric layer; wherein the chip has a surface on which at least one Die Pad (Die Pad) and at least one chip protection layer are disposed, wherein the chip is formed by dividing a wafer; wherein each first dielectric layer covers the surface of each chip protection layer of the chip, and at least one first groove is formed on each first dielectric layer, so that each die pad can be exposed from each first groove; wherein each second dielectric layer is covered on the surface of each first dielectric layer, and each second dielectric layer is provided with at least one second groove, and each second groove is communicated with each first groove of each first dielectric layer; wherein each conductive circuit is formed by filling each first groove and each second groove with high-dose silver paste or high-dose copper paste, so that each die pad can be electrically connected with each conductive circuit; wherein each third dielectric layer covers the surface of each second dielectric layer and the surface of each connecting circuit, and each third dielectric layer is formed with at least one opening to expose each connecting circuit from each opening, wherein each connecting circuit forms at least one bonding Pad (Pad) at each opening for external electrical connection.

In a preferred embodiment of the present invention, at least one conductive bump is further disposed on the surface of each conductive circuit, and each conductive bump is electrically connected to each conductive circuit.

In a preferred embodiment of the present invention, each of the conductive bumps is further a bump body composed of a nickel (Ni) layer and a gold (Au) layer, or a bump body composed of a nickel (Ni) layer, a palladium (P) layer and a gold (Au) layer, or a bump body composed of a palladium (P) layer and a gold (Au) layer.

In a preferred embodiment of the present invention, each of the conductive bumps further has at least one first passivation layer, wherein each of the first passivation layers is electrically connected to each of the conductive bumps.

In a preferred embodiment of the present invention, each of the first passivation layers further has at least one second passivation layer, wherein each of the second passivation layers is electrically connected to each of the first passivation layers.

In a preferred embodiment of the present invention, the total thickness of the stacked first dielectric layers, the stacked second dielectric layers, the stacked conductive traces, and the stacked third dielectric layers is 25 μm.

In a preferred embodiment of the present invention, the high-dose silver paste or the high-dose copper paste forming each of the conductive lines is further a nano silver paste or a nano copper paste.

In a preferred embodiment of the present invention, each of the openings of each of the third dielectric layers is further provided with at least one solder ball, so that each of the conductive traces can be electrically connected to the outside through each of the solder balls.

In a preferred embodiment of the present invention, the chip package structure is further electrically connected to the electronic device through a bonding Wire, so as to form a first bonding pad and a second bonding pad on an electronic device through the bonding Wire in each of the conductive traces in each of the openings during Wire bonding.

To achieve the above objective, the present invention further provides a chip package structure, which includes a chip, at least one first dielectric layer, at least one bump for a die pad, at least one second dielectric layer, at least one conductive trace and at least one third dielectric layer; wherein the chip has a surface, the surface is provided with at least one Die Pad (Die Pad) and at least one chip protection layer, wherein the chip is formed by cutting off a wafer; wherein each first dielectric layer covers the surface of each chip protection layer of the chip, and at least one first groove is formed on each first dielectric layer, so that each die pad can be exposed from each first groove; wherein each bump for die pad is formed in each first groove and correspondingly located on the surface of each die pad to be electrically connected with each die pad; wherein each second dielectric layer is arranged on the surface of each first dielectric layer in a covering manner, at least one second groove is formed on each second dielectric layer, and each second groove is communicated with each first groove of each first dielectric layer; wherein each conductive circuit is formed by filling each second groove with high-dose silver paste or high-dose copper paste, so that each bump for the die pad can be electrically connected with each conductive circuit; wherein each third dielectric layer covers the surface of each second dielectric layer and the surface of each conducting circuit, and each third dielectric layer is formed with at least one opening so that each conducting circuit can pass through each opening to be exposed to the outside, wherein each conducting circuit forms at least one bonding Pad (Pad) at each opening for external electrical connection.

In another preferred embodiment of the present invention, each of the conductive traces further has at least one conductive bump on the surface thereof, and each of the conductive bumps is electrically connected to each of the conductive traces.

In another preferred embodiment of the present invention, each of the conductive bumps is further a bump body composed of a nickel (Ni) layer and a gold (Au) layer, or a bump body composed of a nickel (Ni) layer, a palladium (P) layer and a gold (Au) layer, or a bump body composed of a palladium (P) layer and a gold (Au) layer.

In another preferred embodiment of the present invention, each of the conductive bumps further has at least one first passivation layer, wherein each of the first passivation layers is electrically connected to each of the conductive bumps.

In another preferred embodiment of the present invention, each of the first passivation layers further has at least one second passivation layer, wherein each of the second passivation layers is electrically connected to each of the first passivation layers.

In another preferred embodiment of the present invention, each bump for die pad is further a bump body composed of a nickel (Ni) layer and a gold (Au) layer, or a bump body composed of a nickel (Ni) layer, a palladium (P) layer and a gold (Au) layer, or a bump body composed of a palladium (P) layer and a gold (Au) layer.

In another preferred embodiment of the present invention, the total thickness of the stacked first dielectric layers, the stacked second dielectric layers, the stacked conductive traces, and the stacked third dielectric layers is 25 μm.

In another preferred embodiment of the present invention, the high-dose silver paste or the high-dose copper paste constituting each of the conductive traces is further a nano silver paste or a nano copper paste.

In another preferred embodiment of the present invention, at least one solder ball is further disposed on each opening of each third dielectric layer, so that each conductive circuit can be electrically connected to the outside through each solder ball.

In another preferred embodiment of the present invention, the chip package structure is further electrically connected to the electronic device through a bonding Wire, so as to form a first bonding pad and a second bonding pad on an electronic device through the bonding Wire on each of the conductive traces in each of the openings during Wire bonding.

Drawings

Fig. 1 is a schematic side sectional plan view of a first embodiment of the present invention.

Fig. 2 is a schematic side view of the chip of the present invention.

Fig. 3 is a cross-sectional side plan view of a first dielectric layer disposed on the chip of fig. 2.

Fig. 4 is a cross-sectional side plan view of a second dielectric layer disposed on the first dielectric layer of fig. 3.

Fig. 5 is a schematic sectional side plan view illustrating filling of a high-dose silver paste or a high-dose copper paste into the first and second grooves of fig. 4.

FIG. 6 is a schematic sectional side plan view of the high-dose silver or copper paste of FIG. 5 above the surface of the second dielectric layer being polished to expose the surface of the second dielectric layer.

Fig. 7 is a schematic sectional side plan view of a third dielectric layer disposed on the conductive trace of fig. 6.

Fig. 8 is a schematic side sectional plan view illustrating a plurality of chip package structures on a wafer according to a first embodiment of the present invention.

Fig. 9 is a schematic side sectional plan view illustrating the chip package structure and the electronic device electrically connected together through Wire bonding (Wire bonding).

Fig. 10 is a schematic side sectional plan view of a second embodiment of the present invention.

Fig. 11 is a schematic sectional side plan view of a conductive bump disposed on the conductive trace of fig. 6.

Fig. 12 is a schematic sectional side plan view illustrating the first protective layer disposed on the conductive bump of fig. 11.

Fig. 13 is a side cross-sectional plan view of a second protective layer disposed on the first protective layer of fig. 12.

FIG. 14 is a cross-sectional side plan view of a third dielectric layer disposed on the second passivation layer of FIG. 13.

Fig. 15 is a schematic side sectional plan view illustrating a plurality of chip package structures on a wafer according to a second embodiment of the present invention.

Fig. 16 is a schematic side sectional plan view of a third embodiment of the present invention.

Fig. 17 is a schematic side cross-sectional plan view illustrating a bump for a die pad disposed on the die pad of fig. 2.

Fig. 18 is a side cross-sectional plan view of a second dielectric layer disposed on the first dielectric layer of fig. 17.

Fig. 19 is a cross-sectional side plan view illustrating the first and second grooves of fig. 18 filled with a high-dose silver paste or a high-dose copper paste.

FIG. 20 is a cross-sectional side plan view of the high-dose silver or copper paste of FIG. 19 that is above the surface of the second dielectric layer being polished to expose the surface of the second dielectric layer.

Fig. 21 is a cross-sectional side plan view of a third dielectric layer disposed over the conductive line of fig. 20.

Fig. 22 is a schematic side sectional plan view illustrating a plurality of chip package structures on a wafer according to a third embodiment of the present invention.

Fig. 23 is a schematic side sectional plan view of a fourth embodiment of the present invention.

Fig. 24 is a cross-sectional side plan view of the conductive trace of fig. 23 with a conductive bump formed thereon.

Fig. 25 is a schematic sectional side plan view illustrating the first protective layer disposed on the conductive bump in fig. 24.

Fig. 26 is a side cross-sectional plan view of a second protective layer disposed on the first protective layer of fig. 25.

Fig. 27 is a side cross-sectional plan view of a third dielectric layer disposed on the second protective layer of fig. 26.

Fig. 28 is a schematic side sectional plan view illustrating a plurality of chip package structures on a wafer according to a fourth embodiment of the present invention.

Description of the reference numerals: 1-chip packaging structure; 1 a-a chip package structure; 1 b-a chip package structure; 1 c-a chip package structure; 1 d-a chip package structure; 10-a chip; 11-surface; 12-a die pad; 13-chip protection layer; 20-a first dielectric layer; 21-a first groove; 30-a second dielectric layer; 31-a second groove; 40-a conducting line; 40 a-a metal paste layer; 41-a pad; 50-a third dielectric layer; 51-an opening; 60-bumps for conductive connection; 70-solder ball; 80-bumps for die pad; 90-a first protective layer; 100-a second protective layer; 2-a wafer; 3-welding wires; 3 a-a first solder joint; 3 b-a second solder joint; 4-electronic components.

Detailed Description

The structure and the technical features of the present invention are described in detail below with reference to the drawings, wherein each drawing is only used to illustrate the structure relationship and related functions of the present invention, and therefore the sizes of the elements in each drawing are not drawn according to the actual scale and are not used to limit the present invention.

Referring to fig. 1, 10, 16 and 23, the present invention provides a chip package structure 1, in which the chip package structure 1 includes a chip 10, at least one first dielectric layer 20, at least one second dielectric layer 30, at least one conductive trace 40 and at least one third dielectric layer 50.

The chip 10 has a surface 11, and at least one Die Pad (Die Pad) 12 and at least one chip passivation layer 13 are disposed on the surface 11 as shown in fig. 1 and 2; the chips 10 are formed by being separated from a wafer 2 as shown in fig. 8, 15, 22 and 28.

Each first dielectric layer 20 covers the surface of each chip protection layer 13 of the chip 10, and at least one first groove 21 is formed on each first dielectric layer 20, so that each die pad 12 can be exposed from each first groove 21 as shown in fig. 1 and 3.

Each second dielectric layer 30 is disposed on the surface of each first dielectric layer 20, and at least one second recess 31 is formed on each second dielectric layer 30, and each second recess 31 is communicated with each first recess 21 of each first dielectric layer 20 as shown in fig. 1 and 4.

Each conductive trace 40 is formed by filling the first grooves 21 and the second grooves 31 with high-dose silver paste or high-dose copper paste, so that each die pad 12 can be electrically connected to each conductive trace 40 as shown in fig. 1; wherein the high-dosage silver paste is composed of a resin material and a silver material, but not limited thereto, wherein the ratio of the silver material in the high-dosage silver paste is larger than that of the resin material; the high-dosage copper paste is composed of a resin material and a copper material, but is not limited to the above, wherein the ratio of the copper material in the high-dosage copper paste is larger than that of the resin material.

The high-dose silver paste or the high-dose copper paste forming each conductive connection line 40 is further a nano silver paste or a nano copper paste, but not limited to, so as to increase the conductive efficiency.

Each of the third dielectric layers 50 is disposed on the surface of each of the second dielectric layers 30 and the surface of each of the conductive traces 40, and each of the third dielectric layers 50 has at least one opening 51 formed thereon, so that each of the conductive traces 40 can be exposed from each of the openings 51 to the outside as shown in fig. 1 and 7, wherein each of the conductive traces 40 has at least one Pad (Pad) 41 formed at each of the openings 51 for electrically connecting to the outside as shown in fig. 1, 7, 14, 21 and 27.

In this case, the total thickness of the stacked first dielectric layers 20, the stacked second dielectric layers 30, the stacked conductive traces 40, and the stacked third dielectric layers 50 is 25 micrometers (μm), but not limited to, as shown in fig. 9, so as to form a stacked structure having a thickness to enhance the overall structural strength.

The chip package structure 1 of the present invention further can select the solder ball welding or Wire Bonding operation to electrically connect with the external electronic component without limitation; when the solder ball bonding operation is selected, at least one solder ball 70 is further disposed on each opening 51 of each third dielectric layer 50 of the chip package structure 1, but not limited to the embodiment shown in fig. 1, 10, 16 and 23, so that each conductive trace 40 can be electrically connected to the outside through each solder ball 70; when Wire Bonding is selected, the chip package structure 1 further forms a first Bonding pad 3a on each conductive trace 40 in each opening 51 and a second Bonding pad 3b on an electronic element 4 through a Wire Bonding 3, as shown in fig. 9, so that the chip package structure 1 and the electronic element 4 are electrically connected together, thereby increasing the diversified applications of the product and facilitating the increase of the market competitiveness of the product.

Referring to fig. 1 to 8, 15, 22 and 28, the method for manufacturing the chip package structure 1 includes the following steps:

step S1: providing a wafer 2, disposing a plurality of chips 10 arranged in an array on the wafer 2 as shown in fig. 8, 15, 22 and 28, each of the chips 10 having a surface 11, and disposing at least one Die Pad (Die Pad) 12 and at least one chip protection layer 13 on the surface 11 as shown in fig. 2.

Step S2: at least one first dielectric layer 20 is correspondingly disposed on the surface of each chip protection layer 13 of the chip 10, and at least one first groove 21 is formed on each first dielectric layer 20, so that each die pad 12 can be exposed from each first groove 21 as shown in fig. 3.

And step S3: at least one second dielectric layer 30 is correspondingly disposed on the surface of each first dielectric layer 20, at least one second recess 31 is formed on each second dielectric layer 30, and each second recess 31 is communicated with each first recess 21 of each first dielectric layer 20 as shown in fig. 4.

And step S4: a metal paste layer 40a is formed by filling a high-dose silver paste or a high-dose copper paste into each of the first grooves 21 and each of the second grooves 31, and the thickness of the metal paste layer 40a formed by the high-dose silver paste or the high-dose copper paste is greater than the surface of each of the second dielectric layers 30 as shown in fig. 5.

Step S5: polishing the metal paste layer 40a (as shown in fig. 5) formed by the high-dose silver paste or the high-dose copper paste higher than the surface of each second dielectric layer 30 to expose the surface of each second dielectric layer 30, so that the surface of the high-dose silver paste or the high-dose copper paste is flush with the surface of each second dielectric layer 30 to form at least one conductive trace 40 as shown in fig. 6; wherein each die pad 12 can be electrically connected to each conductive trace 40 as shown in fig. 1.

Step S6: at least one third dielectric layer 50 is correspondingly disposed on the surface of each second dielectric layer 30 and the surface of each conductive trace 40, at least one opening 51 is formed on each third dielectric layer 50, so that each conductive trace 40 can be exposed from each opening 51 as shown in fig. 1 and 7, wherein at least one Pad (Pad) 41 is formed on each opening 51 of each conductive trace 40 for external electrical connection as shown in fig. 7.

In addition, the chip package structure 1 according to the present invention can be further divided into a first embodiment (the chip package structure 1 a), a second embodiment (the chip package structure 1 b), a third embodiment (the chip package structure 1 c) and a fourth embodiment (the chip package structure 1 d) without limitation as shown in fig. 1, 10, 16 and 23, according to whether the chip package structure 1 has at least one connecting bump 60 (as shown in fig. 10) or at least one die pad bump 80 (as shown in fig. 16), or each connecting bump 60 and each die pad bump 80 have (as shown in fig. 23), or each connecting bump 60 and each die pad bump 80 do not have (as shown in fig. 1); the chip 10, the first dielectric layers 20, the second dielectric layers 30, the connecting lines 40 and the third dielectric layers 50 are substantially the same in structure or technical features in the first embodiment (the chip package structure 1 a), the second embodiment (the chip package structure 1 b), the third embodiment (the chip package structure 1 c) and the fourth embodiment (the chip package structure 1 d), as shown in fig. 1, 10, 16 and 23.

Each of the conductive bumps 60 is further a bump body composed of a nickel (Ni) layer and a gold (Au) layer, or a bump body composed of a nickel (Ni) layer, a palladium (P) layer and a gold (Au) layer, or a bump body composed of a palladium (P) layer and a gold (Au) layer, but not limited thereto, so as to reduce the use of gold (Au) material and save cost; each bump 80 for die pad is further a bump body composed of a nickel (Ni) layer and a gold (Au) layer, or a bump body composed of a nickel (Ni) layer, a palladium (P) layer and a gold (Au) layer, or a bump body composed of a palladium (P) layer and a gold (Au) layer, but not limited thereto, so as to reduce the use of gold (Au) material and save cost.

The embodiment shown in fig. 1 and 8 is the first embodiment (the chip package structure 1 a) of the present invention, and in the first embodiment (the chip package structure 1 a), the chip package structure 1a does not have the conductive bumps 60 and the die pads 80, so that each die pad 12 of the chip 10 can be directly electrically connected to the outside through the conductive traces 40, which is favorable for improving the conductive efficiency of the product.

In addition, since the chip package structure 1a (the first embodiment) does not need to provide the conductive bumps 60 and the die pads 80, the manufacturing process is simplified and the cost is saved.

The second embodiment (the chip package structure 1 b) of the present invention is shown in fig. 10 and fig. 15, in the second embodiment (the chip package structure 1 b), the chip package structure 1b further has at least one conductive bump 60, each conductive bump 60 is disposed on the surface of each conductive trace 40, and each conductive bump 60 is electrically connected to each conductive trace 40 as shown in fig. 10, fig. 11 and fig. 14, so as to protect each conductive trace 40 and improve the yield of the product.

Wherein each of the conductive bumps 60 is further provided with at least one first protection layer 90 without limitation as shown in fig. 12, wherein each of the first protection layers 90 is electrically connected to each of the conductive bumps 60 to protect each of the conductive bumps 60 and improve the yield of the product; at least one second passivation layer 100 is further disposed on each first passivation layer 90, but not limited to fig. 13 and 14, wherein each second passivation layer 100 is electrically connected to each first passivation layer 90 to protect each conductive bump 60 and thus to improve the yield of the product.

The embodiment shown in fig. 16 and 22 is a third embodiment (the chip package structure 1 c) of the present invention, and in the third embodiment (the chip package structure 1 c), the chip package structure 1b further has at least one bump 80 for die pad, each bump 80 for die pad is formed in each first groove 21 and correspondingly located on the surface of each die pad 12 to electrically connect with each die pad 12 as shown in fig. 16 to 18; referring to fig. 19 and 20, each of the conductive traces 40 is formed in each of the second recesses 31 and polished to expose the surface of each of the second dielectric layers 30, so that each of the bumps 80 for a die pad can be electrically connected to each of the conductive traces 40.

The embodiment shown in fig. 23 and 28 is a fourth embodiment (the chip package structure 1 d) of the present invention, and in the fourth embodiment (the chip package structure 1 d), the chip package structure 1d further has at least one conductive bump 60 and at least one die pad bump 80; wherein each of the bumps 60 is disposed on the surface of each of the conductive traces 40, and each of the bumps 60 is electrically connected to each of the conductive traces 40 as shown in fig. 24 and 27, so as to protect each of the conductive traces 40 and improve the yield of the product; wherein each bump 80 for die pad is formed in each first groove 21 and correspondingly located on the surface of each die pad 12 to electrically connect each die pad 12 as shown in fig. 26; wherein each conductive trace 40 is formed in each second groove 31 and polished to expose the surface of each second dielectric layer 30, so that each bump 80 for die pad can be electrically connected to each conductive trace 40 as shown in FIG. 23.

Wherein each of the conductive bumps 60 is further provided with at least one first protection layer 90 without limitation as shown in fig. 25, wherein each of the first protection layers 90 is electrically connected to each of the conductive bumps 60 to protect each of the conductive bumps 60 and thus to stably improve the yield of the product; at least one second passivation layer 100 is further disposed on each first passivation layer 90, but not limited to the embodiment shown in fig. 26, wherein each second passivation layer 100 is electrically connected to each first passivation layer 90 to protect each conductive bump 60 and thus to improve the yield of the product.

The utility model discloses a this chip package structure 1 compares with current chip package structure, has following advantage:

the utility model discloses an each leads and connects circuit 40 utilizes high dose silver cream or high dose copper cream to fill up and constitutes in each first recess 21 of each first dielectric layer 20 and each second recess 31 of each second dielectric layer 30, make each brilliant pad 12 of this chip 10 can with each lead and connect circuit 40 electric connection, in order to promote each conductive efficiency who leads and connect circuit 40, furthermore, more accessible each brilliant pad forms in each first recess 21 and corresponds on being located each brilliant pad 12 with each brilliant pad 12 electric connection with each brilliant pad 80, in order to protect each brilliant pad 12 and increase the product yield, solve effectively that current chip packaging structure product quality is lower on the market and make the problem that the dependability descends, be favorable to increasing the market competition of product.

The foregoing is only a preferred embodiment of the present invention, which is intended to be illustrative, not limiting; those skilled in the art will understand that many variations, modifications, and even equivalent variations can be made within the spirit and scope of the invention as defined in the claims, but all will fall within the scope of the invention.

Claims

1. A chip package structure, comprising:

a chip having a surface, at least one die pad and at least one chip passivation layer disposed on the surface; wherein the chip is formed by dividing a wafer;

at least one first dielectric layer, each first dielectric layer is covered on the surface of each chip protective layer of the chip, and at least one first groove is formed on each first dielectric layer, so that each crystal pad can be exposed from each first groove;

at least one second dielectric layer, each second dielectric layer is covered on the surface of each first dielectric layer, at least one second groove is formed on each second dielectric layer, and each second groove is communicated with each first groove of each first dielectric layer;

at least one conductive circuit, each conductive circuit is formed by filling each first groove and each second groove with high-dosage silver paste or high-dosage copper paste, so that each die pad can be electrically connected with each conductive circuit; and

at least one third dielectric layer, each third dielectric layer covering the surface of each second dielectric layer and the surface of each conducting circuit, and each third dielectric layer having at least one opening to expose each conducting circuit from each opening, wherein each conducting circuit has at least one pad formed at each opening for electrical connection.

2. The chip package structure as claimed in claim 1, wherein at least one conductive bump is further disposed on the surface of each conductive trace, and each conductive bump is electrically connected to each conductive trace.

3. The chip package structure of claim 2, wherein each of the conductive bumps is further a bump body composed of a Ni layer and a Au layer, or a bump body composed of a Ni layer, a Pd layer and a Au layer, or a bump body composed of a Pd layer and a Au layer.

4. The chip package structure according to claim 2, wherein at least a first passivation layer is further disposed on each of the conductive bumps, wherein each of the first passivation layers is electrically connected to each of the conductive bumps.

5. The chip package structure according to claim 4, wherein each of the first passivation layers further has at least one second passivation layer thereon, wherein each of the second passivation layers is electrically connected to each of the first passivation layers.

6. The chip package structure of claim 1, wherein a total thickness of the stacked first dielectric layers, the stacked second dielectric layers, the stacked conductive traces and the stacked third dielectric layers is 25 μm.

7. The chip package structure of claim 1, wherein the high-dose silver paste or high-dose copper paste forming each of the bonding wires is further a nano-silver paste or a nano-copper paste.

8. The chip package structure of claim 1, wherein each opening of each third dielectric layer is further formed with at least one solder ball, such that each conductive trace can be electrically connected to the outside through each solder ball.

9. The chip package structure of claim 1, wherein the chip package structure is further electrically connected to the electronic device by a bonding wire, so that a first bonding pad and a second bonding pad are formed on each of the conductive traces in each of the openings by the bonding wire during a wire bonding operation.

10. A chip package structure, comprising:

at least one bump for die pad, each bump for die pad formed in each first groove and correspondingly located on the surface of each die pad and electrically connected to each die pad;

at least one second dielectric layer, each second dielectric layer covering the surface of each first dielectric layer, and each second dielectric layer having at least one second groove formed thereon, each second groove being communicated with each first groove of each first dielectric layer;

at least one conductive circuit, each conductive circuit is formed by filling each second groove with high-dose silver paste or high-dose copper paste, so that each bump for the die pad can be electrically connected with each conductive circuit; and

at least one third dielectric layer, each third dielectric layer covering the surface of each second dielectric layer and the surface of each conducting circuit, and each third dielectric layer having at least one opening, so that each conducting circuit can be exposed through each opening, wherein each conducting circuit forms at least one pad at each opening for electrical connection.

11. The chip package structure as claimed in claim 10, wherein at least one conductive bump is further disposed on the surface of each conductive trace, and each conductive bump is electrically connected to each conductive trace.

12. The chip package structure of claim 11, wherein each of the conductive bumps is further a bump body composed of a nickel layer and a gold layer, or a bump body composed of a nickel layer, a palladium layer and a gold layer, or a bump body composed of a palladium layer and a gold layer.

13. The chip package structure as claimed in claim 11, wherein at least a first passivation layer is further disposed on each of the conductive bumps, wherein each of the first passivation layers is electrically connected to each of the conductive bumps.

14. The chip package structure according to claim 13, wherein each of the first passivation layers further has at least one second passivation layer thereon, wherein each of the second passivation layers is electrically connected to each of the first passivation layers.

15. The chip package structure of claim 10, wherein each bump for the die pad is further a bump body composed of a nickel layer and a gold layer, or a bump body composed of a nickel layer, a palladium layer and a gold layer, or a bump body composed of a palladium layer and a gold layer.

16. The chip package structure of claim 10, wherein a total thickness of stacked first dielectric layers, second dielectric layers, conductive traces and third dielectric layers is 25 μm.

17. The chip package structure of claim 10, wherein the high-dose silver paste or high-dose copper paste forming each of the bonding wires is further a nano-silver paste or a nano-copper paste.

18. The chip package according to claim 10, wherein each of the openings of the third dielectric layer is further provided with at least one solder ball, such that each of the conductive traces can be electrically connected to the outside through each of the solder balls.

19. The chip package structure according to claim 10, wherein the chip package structure is further electrically connected to the electronic device through a bonding wire for forming a first bonding point on each of the conductive traces in each of the openings and a second bonding point on an electronic device through the bonding wire during a wire bonding operation.