CN218333784U

CN218333784U - Chip packaging lug structure for improving wire bonding bearing capacity

Info

Publication number: CN218333784U
Application number: CN202221536960.6U
Authority: CN
Inventors: 于鸿祺; 林俊荣; 古瑞庭
Original assignee: Walton Advanced Engineering Inc
Current assignee: Walton Advanced Engineering Inc
Priority date: 2022-06-17
Filing date: 2022-06-17
Publication date: 2023-01-17
Anticipated expiration: 2032-06-17

Abstract

The utility model discloses an improve bump structure of chip package of routing Bonding bearing capacity, wherein at least a lug of this chip package is a metal stack structure that has certain thickness, and the whole thickness of each this lug sets for 4.5 ~ 20 microns (mu m), with this increase the structural strength of each this lug in order to bear the normal pressure that produces when coming from routing Bonding (Wire Bonding) operation or forming a first solder joint, make at least an inner line of this chip can not receive destruction because of this normal pressure, and make each this inner line can allow to pass through or arrange in the below of at least a wafer Pad (Die Pad) of this chip, solve the design that the inner line of chip need rearrangement of manufacture end effectively and lead to the problem of manufacture end cost increase, be favorable to reducing the cost of manufacture end.

Description

Chip packaging lug structure for improving wire bonding bearing capacity

Technical Field

The present invention relates to a bump structure for chip packaging, and more particularly to a bump structure for chip packaging which improves the wire bonding endurance.

Background

In the field of chip packaging, the electrical connection between the chip package and the electronic device can be achieved by Wire Bonding, i.e., a Bonding Wire is used to form a solder joint on the chip package structure and another solder joint on the electronic device, so that the chip package structure and the electronic device are electrically connected together. However, when performing the wire bonding operation, the conventional chip package structure is subjected to a positive pressure generated from the wire bonding operation or the formation of the solder joints, so that the internal circuits of the chip are damaged by the positive pressure, and the internal circuits are not easy to pass or cannot pass through or are arranged under the die pads in the chip.

Therefore, a bump structure of a chip package for improving wire bonding endurance, which effectively solves the problem of increasing the manufacturing cost due to the need of rearranging the internal circuit of the chip at the manufacturing end, is a great expectation of the related industries at present.

SUMMERY OF THE UTILITY MODEL

The main objective of the present invention is to provide a bump structure of chip package for improving Wire Bonding endurance, wherein at least one bump of the chip package is a metal stacked structure with a certain thickness, and the overall thickness of each bump is set to be 4.5-20 micrometers (μm), so as to improve the structural strength of each bump to bear the positive pressure generated during Wire Bonding operation or forming a first solder joint, so that at least one internal circuit of the chip is not damaged by the positive pressure, and each internal circuit can be allowed to pass through or be arranged under at least one Die Pad (Die Pad) of the chip, thereby effectively solving the problem of increasing the cost of the manufacturing end due to the requirement of rearranging the internal circuit of the chip at the manufacturing end.

To achieve the above objects, the present invention provides a bump structure of a chip package for improving the wire bonding endurance, the chip package comprising a chip, at least one dielectric layer and at least one bump; wherein the chip has a first surface and at least one internal circuit, the first surface is provided with at least one Die Pad (Die Pad) and at least one protective layer, wherein the chip is formed by dividing a wafer; wherein each dielectric layer is correspondingly covered on the first surface of the chip, each dielectric layer is provided with at least one opening, and each opening corresponds to each crystal pad of the chip; each bump is arranged in each opening of each dielectric layer and is exposed upwards, and each bump is a laminated stacking structure body and is electrically connected to the top surface of each crystal pad of the chip; the chip package and the electronic element are electrically connected together through a Bonding Wire during Wire Bonding operation so as to form a first welding point on each bump and a second welding point on the electronic element; in the chip package: each bump is a metal stacked structure body which is composed of a nickel (Ni) layer and a gold (Au) layer which are sequentially arranged on the top surface of each die pad and has a certain thickness, wherein the overall thickness of each bump is set to be 4.5-20 micrometers (mum), so that the structural strength of each bump is improved to bear positive pressure generated in wire bonding operation or formation of the first welding point, each internal circuit of the chip is not damaged due to the positive pressure, each internal circuit can pass through or be arranged below each die pad, and the manufacturing cost of the terminal is reduced.

In a preferred embodiment of the present invention, the gold (Au) layer occupies 0.005-0.2 μm of thickness in each bump, and the rest of the thickness of each bump is the thickness of the nickel (Ni) layer.

To achieve the above objects, the present invention further provides a bump structure of a chip package for improving the wire bonding endurance, the chip package comprising a chip, at least one dielectric layer and at least one bump; wherein the chip has a first surface and at least one internal circuit, the first surface is provided with at least one Die Pad (Die Pad) and at least one protective layer, wherein the chip is formed by dividing a wafer; wherein each dielectric layer is correspondingly covered on the first surface of the chip, each dielectric layer is provided with at least one opening, and each opening corresponds to each crystal pad of the chip; each bump is arranged in each opening of each dielectric layer and is exposed upwards, and each bump is a laminated stacking structure body and is electrically connected to the top surface of each crystal pad of the chip; the chip package and the electronic element are electrically connected together through a Bonding Wire during Wire Bonding operation so as to form a first welding point on each bump and a second welding point on the electronic element; wherein: each bump is a metal stacked structure composed of a nickel (Ni) layer, a palladium (Pd) layer and a gold (Au) layer sequentially formed on the top surface of each die pad, and having a certain thickness, wherein the entire thickness of each bump is set to be 4.5 to 20 micrometers (μm), so as to enhance the structural strength of each bump to withstand a positive pressure generated from a wire bonding operation or the formation of the first solder joint, so that each internal circuit of the chip is not damaged by the positive pressure, and each internal circuit is allowed to pass through or be arranged under each die pad, thereby facilitating the reduction of the manufacturing cost of the terminals.

In a preferred embodiment of the present invention, the thickness of the gold (Au) layer in each bump is 0.005-0.2 micrometers (μm), the thickness of the palladium (Pd) layer in each bump is 0.005-0.3 micrometers (μm), and the remaining thickness of each bump is the thickness of the nickel (Ni) layer.

Drawings

Fig. 1 is a schematic side sectional plan view of a first embodiment of the present invention.

Fig. 2 is a side cross-sectional plan view of a first embodiment of a die cut from a wafer.

Fig. 3 is a schematic side sectional plan view of a second embodiment of the present invention.

FIG. 4 is a side cross-sectional plan view of a second embodiment of a die cut from a wafer.

Fig. 5 is a side cross-sectional plan view of the chip package of the first embodiment.

Fig. 6 is a side cross-sectional plan view of the chip package of the second embodiment.

Fig. 7 is a partially enlarged schematic view of fig. 5.

Fig. 8 is a partially enlarged view of fig. 6.

Fig. 9 is a schematic top plan view of the internal circuit of the present invention.

Fig. 10 is a schematic top plan view of the chip package according to the present invention.

Description of reference numerals: 1-packaging a chip; 1 a-packaging a chip; 10-a chip; 10 a-a first surface; 11-a die pad; 12-a protective layer; 13-internal wiring; 13 a-an array region; 13 b-circuit area; 20-a dielectric layer; 21-opening; 30-a bump; 31-a first solder joint; a 32-nickel layer; 33-gold layer; 34-palladium layer; 2-a wafer; 3-welding wires; 4-an electronic component; 4 a-second solder joint.

Detailed Description

The structure and the technical features of the present invention are described in detail below with reference to the drawings, wherein each drawing is only used to illustrate the structure relationship and related functions of the present invention, and therefore the sizes of the elements in each drawing are not drawn according to the actual scale and are not used to limit the present invention.

Referring to fig. 1, fig. 3, fig. 5 and fig. 6, the present invention provides a bump structure of chip package for enhancing wire bonding endurance, the chip package 1, 1a includes a chip 10, at least one dielectric layer 20 and at least one bump 30; wherein the chip 10 has a first surface 10a and at least one internal circuit 13, the first surface 10a is provided with at least one Die Pad (Die Pad) 11 and at least one passivation layer 12, and the chip 10 is formed by being separated from a wafer 2 (as shown in fig. 2 and 4); wherein each dielectric layer 20 is correspondingly covered on the first surface 10a of the chip 10, each dielectric layer 20 has at least one opening 21, and each opening 21 corresponds to each die pad 11 of the chip 10; wherein each bump 30 is disposed in each opening 21 of each dielectric layer 20 and exposed upward, and each bump 30 is a layered stacked structure and is electrically connected to the top surface of each die pad 11 of the chip 10; when Wire Bonding (Wire Bonding) is performed, as shown in fig. 1 and 3, a first Bonding pad 31 is formed on each bump 30 and a second Bonding pad 4a is formed on an electronic component 4 by a Bonding Wire 3, so that the chip packages 1 and 1a and the electronic component 4 are electrically connected together, as shown in fig. 1 and 3.

Each of the internal circuits 13 includes, but is not limited to, a 13a Array region (Array), a 13b circuit region (circuit area) or a Cell (Cell) (not shown) as shown in fig. 9 and 10.

According to the present invention, the difference between the materials or components of each bump 30 constituting the stacked structure can be further divided into a first embodiment (the chip package 1) and a second embodiment (the chip package 1 a) as shown in fig. 1 and 3; wherein the chip 10 and each of the dielectric layers 20 are identical in structural configuration or technical features in the first embodiment (the chip package 1) or the second embodiment (the chip package 1 a).

The embodiment shown in fig. 1, 2, 5 and 7 is a first embodiment (the chip package 1) of the present invention, in which each bump 30 is a metal stacked structure having a certain thickness and sequentially including a nickel (Ni) layer 32 and a gold (Au) layer 33 on the top surface of each die pad 11 as shown in fig. 1 and 5, wherein the overall thickness of each bump 30 is set to be 4.5-20 micrometers (μm) as shown in fig. 7, so as to enhance the structural strength of each bump 30 to withstand the positive pressure N generated from the wire bonding operation or the formation of the first solder joints 31 as shown in fig. 1, so that each internal circuit 13 of the chip 10 is not damaged by the positive pressure N (shown in fig. 1), and each internal circuit 13 is allowed to pass through or be arranged under each die pad 11 as shown in fig. 1 and 10.

The thickness of the gold (Au) layer 33 in each bump 30 is 0.005-0.2 micrometers (μm) but not limited to the thickness shown in fig. 7, and the remaining thickness of each bump 30 is the thickness of the nickel (Ni) layer 32, so that the ratio distribution can reduce the usage amount of the gold (Au) layer 33 with higher cost, and each bump 30 can not lose a certain structural strength, which is beneficial to reducing the manufacturing end cost.

The second embodiment (the chip package 1 a) of the present invention is shown in fig. 3, 4, 6 and 8, in which each bump 30 is a metal stacked structure having a certain thickness and comprising a nickel (Ni) layer 32, a palladium (Pd) layer 34 and a gold (Au) layer 33 sequentially formed on the top surface of each die pad 11 as shown in fig. 3 and 6, wherein the overall thickness of each bump 30 is set to 4.5 to 20 micrometers (μm) as shown in fig. 8, so as to enhance the structural strength of each bump 30 to withstand the positive pressure N generated from the wire bonding operation or the formation of the first pads 31 as shown in fig. 3, so that each internal circuit 13 of the chip 10 is not damaged by the positive pressure N (as shown in fig. 3), and each internal circuit 13 is allowed to pass through or be arranged below each die pad 11 as shown in fig. 3 and 10.

The thickness of the gold (Au) layer 33 in each bump 30 is 0.005-0.2 micrometers (μm) but not limited to fig. 8, the thickness of the palladium (Pd) layer 34 in each bump 30 is 0.005-0.3 micrometers (μm) but not limited to fig. 8, and the remaining thickness of each bump 30 is the thickness of the nickel (Ni) layer 32, so that the ratio distribution can reduce the usage amount of the gold (Au) layer 33 at a high cost, and each bump 30 can not lose a certain structural strength, which is beneficial to reducing the manufacturing end cost.

The utility model discloses compare with current chip package structure, have following advantage:

each bump 30 of the chip packages 1 and 1a (i.e., the first and second embodiments) of the present invention is a metal stacked structure having a certain thickness, which is composed of the nickel (Ni) layer 32 and the gold (Au) layer 33 as disclosed in the first embodiment (as shown in fig. 1, 2, 5 and 7) or composed of the nickel (Ni) layer 32, the palladium (Pd) layer 34 and the gold (Au) layer 33 as disclosed in the second embodiment (as shown in fig. 3, 4, 6 and 8), and the overall thickness of each bump 30 is set to 4.5 to 20 micrometers (μm) as shown in fig. 7 and 8, so as to increase the structural strength of each bump 30 to withstand the positive pressure N generated from the wire bonding operation or the formation of the first pad 31 as shown in fig. 1 and 3, so that each internal circuit 13 of the chip 10 is not damaged by the positive pressure N (as shown in fig. 1 and 3), and the internal circuit layout cost of each internal circuit 13 can be effectively reduced by the problem that the internal circuit layout of the chip 10 needs to be solved by the manufacturing cost of the chip 10 or the chip.

The foregoing is only a preferred embodiment of the present invention, which is intended to be illustrative, not limiting; those skilled in the art will appreciate that many variations, modifications, and even equivalent variations are possible within the spirit and scope of the invention as defined in the appended claims.

Claims

1. A chip package bump structure for improving the wire bonding bearing capacity comprises a chip, at least one dielectric layer and at least one bump; the chip is provided with a first surface and at least one internal circuit, the first surface is provided with at least one crystal pad and at least one protective layer, and the chip is formed by being divided from a wafer; wherein each dielectric layer is correspondingly covered on the first surface of the chip, each dielectric layer is provided with at least one opening, and each opening corresponds to each crystal pad position of the chip; each bump is arranged in each opening of each dielectric layer and is exposed upwards, and each bump is a laminated stacking structure body and is electrically connected to the top surface of each crystal pad of the chip; the chip package and the electronic element are electrically connected together through a bonding wire during the wire bonding operation, so that a first welding point is formed on each bump and a second welding point is formed on the electronic element; the method is characterized in that:

each bump is a metal stacked structure which is composed of a nickel layer and a gold layer which are sequentially arranged on the top surface of each die pad upwards and has a certain thickness, wherein the overall thickness of each bump is set to be 4.5-20 micrometers, so that the structural strength of each bump is improved to bear positive pressure generated in wire bonding operation or formation of the first welding point, each internal circuit of the chip is not damaged due to the positive pressure, and each internal circuit can pass through or be arranged below each die pad.

2. The bump structure of chip package according to claim 1, wherein the gold layer occupies 0.005-0.2 μm of thickness in each bump, and the remaining thickness of each bump is the thickness of the nickel layer.

3. A chip package bump structure for improving the wire bonding bearing capacity comprises a chip, at least one dielectric layer and at least one bump; the chip is provided with a first surface and at least one internal circuit, the first surface is provided with at least one crystal pad and at least one protective layer, and the chip is formed by being divided from a wafer; wherein each dielectric layer is correspondingly covered on the first surface of the chip, each dielectric layer is provided with at least one opening, and each opening corresponds to each crystal pad of the chip; each bump is arranged in each opening of each dielectric layer and is exposed upwards, and each bump is a laminated stacking structure body and is electrically connected to the top surface of each crystal pad of the chip; the chip package and the electronic element are electrically connected together through a welding wire during the routing joint operation, so that a first welding point is formed on each bump and a second welding point is formed on the electronic element; the method is characterized in that:

each bump is a metal stacked structure which is composed of a nickel layer, a palladium layer and a gold layer which are sequentially arranged on the top surface of each die pad upwards and has a certain thickness, wherein the overall thickness of each bump is set to be 4.5-20 micrometers, so that the structural strength of each bump is improved to bear positive pressure generated in wire bonding operation or forming of the first welding point, each internal circuit of the chip is not damaged due to the positive pressure, and each internal circuit can be allowed to pass through or be arranged below each die pad.

4. The bump structure of chip package according to claim 3, wherein the gold layer occupies 0.005-0.2 μm of thickness in each bump, the palladium layer occupies 0.005-0.3 μm of thickness in each bump, and the remaining thickness of each bump is the thickness of the nickel layer.