CN218217309U - Biasing circuit, amplifier and radio frequency front end module - Google Patents
Biasing circuit, amplifier and radio frequency front end module Download PDFInfo
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- CN218217309U CN218217309U CN202222377844.0U CN202222377844U CN218217309U CN 218217309 U CN218217309 U CN 218217309U CN 202222377844 U CN202222377844 U CN 202222377844U CN 218217309 U CN218217309 U CN 218217309U
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Abstract
The utility model provides a bias circuit, include: n biasing units, wherein N is an integer and is more than or equal to 2; the N bias units correspond to the N amplifying transistors one to one, each bias unit is used for being connected with the corresponding amplifying transistor and providing working voltage for the amplifying transistor, each bias unit comprises a first transistor, the type of the first transistor is the same as that of the amplifying transistor corresponding to the bias unit, and the first transistor and the amplifying transistor form a current mirror structure. Correspondingly the utility model also provides an amplifier and radio frequency front end module. Implement the utility model discloses can reduce the influence of technology angle to amplifier quiescent current.
Description
Technical Field
The utility model relates to the field of semiconductor technology, especially, relate to a biasing circuit, amplifier and radio frequency front end module.
Background
The power amplifier is the most common amplifier in the market at present, and is widely applied to various fields such as radio frequency communication, audio amplification and the like.
A power amplifier (hereinafter simply referred to as an amplifier) mainly includes an amplifying transistor (e.g., a field effect transistor or a transistor), a bias circuit, an input matching circuit, and an output matching circuit. The amplifier comprises an amplifying transistor, a bias circuit, an input matching circuit and an output matching circuit, wherein the amplifying transistor is used as a core element of the amplifier and used for amplifying signals, the bias circuit is used for providing working voltage for the amplifying transistor so as to ensure that the amplifying transistor can work in an amplifying state, the input matching circuit is used for achieving impedance matching of an input end of the amplifier, and the output matching circuit is used for achieving impedance matching of an output end of the amplifier. There are many implementations for the bias circuit, the most typical of which is a voltage-dividing bias circuit, i.e. a circuit that supplies an operating voltage to the amplifying transistor by dividing the voltage with a resistor.
As shown in fig. 1, in the present embodiment, the amplifier includes two amplifying transistors, a bias circuit 1, an input matching circuit 2, and an output matching circuit 3. The two amplifying transistors being field effect transistors M 1 And a field effect transistor M 2 Wherein the field effect transistor M 1 Is connected to a voltage source VDD 1 Field effect transistor M 1 Is connected to the field effect transistor M 2 Drain electrode of (1), field effect transistor M 2 Is grounded. The bias circuit 1 comprises a field effect transistor M 1 Bias unit 1a for providing operating voltage, and field effect transistor M 2 A bias unit 1b for supplying an operating voltage. The bias unit 1a includes a resistor R 4 Resistance R 5 Resistance R 6 Resistance R 7 Resistance R 8 Resistance R 9 And a triode Q 1 . Wherein, the resistance R 4 As an input terminal of the bias unit 1a, is connected to a voltage source VDD 0 The other end of the resistor is connected with a resistor R 5 Is connected to a resistor R 6 One terminal of (1), resistance R 6 Is connected to the triode Q at the other end 1 A base electrode of (1); triode Q 1 Through the collector of (2) 7 Is connected to a resistor R 8 One terminal of (1), resistance R 8 The other end of which passes through a resistor R 9 Grounding; triode Q 1 The emitter of the transistor is grounded and the triode Q 1 The base and collector are shorted. Resistance R 9 And a resistance R 8 The node between them is used as the output terminal of the bias unit 1a, through which the bias unit 1a is connected to the field effect transistor M 1 To be implemented as a field effect transistor M 1 Providing an operating voltage. The bias unit 1b includes a resistor R 1 And a resistor R 2 And a resistance R 3 . Wherein, the resistance R 1 As an input terminal of the bias unit 1b, to a voltage source VDD 0 The other end passes through a resistor R 2 Is connected to a resistor R 3 One terminal of (1), resistance R 3 And the other end of the same is grounded. Resistance R 1 And a resistance R 2 The node between them is used as the output terminal of the bias unit 1b, through which the bias unit 1b is connected to the field effect transistor M 2 To be implemented as a field effect transistor M 2 An operating voltage is provided. An input matching circuit 2 and an output matching circuit 3 are respectively arranged at the input RF of the amplifier in And an output terminal RF out And the impedance matching circuit is used for realizing the impedance matching of the input end and the output end of the amplifier. Wherein the input of the input matching circuit 2 is connected to the input RF in The output end is connected to the field effect transistor M 2 The input of the input matching circuit 3 is connected to the field effect transistor M 1 Is connected to the output RF of the amplifier out 。
For the existing amplifier, the amplifier needs to be simulated under various Process angles (Process Corner) in the design stage of the amplifier, so as to ensure that the amplifier can normally work under various Process angles, and thus, the high yield of the amplifier in the mass production stage is ensured. Among them, it is found from the simulation result that the quiescent current of the amplifier (i.e., the operating current of the amplifier when no signal is input) is greatly affected by the process corner. In particular, the process corner is directed to the threshold voltage (V) of the amplifying transistor in the amplifier T ) There is a great influence that different process corners may cause a large fluctuation in the threshold voltage of the amplifying transistor, which may further cause a large quiescent current of the amplifierAnd (4) floating. The description will be made by taking the amplifier shown in fig. 1 as an example. The results obtained from simulations of the amplifier of fig. 1 at different process angles show that the quiescent current of the amplifier of fig. 1 has a target value of 20.8mA, whereas the quiescent current of the amplifier at the Slow process angle and at the Fast process angle has values of 2.21mA and 48mA, respectively. That is, the quiescent current values and target values of the amplifier shown in FIG. 1 deviate significantly between the Slow process corner and the Fast process corner. This effect of process corner on the quiescent current of the amplifier is clearly detrimental to the stability of the amplifier.
SUMMERY OF THE UTILITY MODEL
In order to overcome the above-mentioned defect among the prior art, the utility model provides a bias circuit, this bias circuit includes:
n biasing units, wherein N is an integer and is more than or equal to 2;
the N bias units correspond to the N amplifying transistors one to one, each bias unit is used for being connected with the corresponding amplifying transistor and providing working voltage for the amplifying transistor, each bias unit comprises a first transistor, the type of the first transistor is the same as that of the amplifying transistor corresponding to the bias unit, and the first transistor and the amplifying transistor form a current mirror structure.
According to an aspect of the present invention, in the bias circuit, each of the bias units further includes a first resistor, a second resistor, a third resistor, and a voltage divider module, wherein one end of the first resistor serves as a first input end of the bias unit, and the other end of the first resistor is connected to a terminal of the first transistor serving as a drain or a collector, a terminal of the first transistor serving as a source or an emitter serves as a first output end of the bias unit, a terminal of the first transistor serving as a drain or a collector and a terminal serving as a gate or a base are shorted, one end of the second resistor is connected to a terminal of the first transistor serving as a gate or a base, and the other end of the second resistor is connected to one end of the third resistor, and the other end of the third resistor serves as a second output end of the bias unit, and one end of the voltage divider module serves as a second input end of the bias unit, and the other end of the voltage divider module is connected to a node between the second resistor and the third resistor; the first input end of the 1 st bias unit and the second input ends of all the bias units are used for connecting a voltage source; the first output end of the ith bias unit is connected to the first input end of the (i + 1) th bias unit, the first output end of the Nth bias unit is used for grounding, wherein i is more than or equal to 1 and less than or equal to N-1; the second output end of each bias unit is used for being connected with the terminal of the corresponding amplifying transistor serving as a grid electrode or a base electrode.
According to another aspect of the present invention, in the bias circuit, the voltage dividing module includes a second transistor or a fourth resistor; for the case that the voltage dividing module includes the second transistor, the second transistor is of the same type as the first transistor in the bias unit in which the second transistor is located, wherein a terminal of the second transistor serving as a drain or a collector is used as the second input terminal, a terminal of the second transistor serving as a source or an emitter is connected to the node, and a terminal of the second transistor serving as a source or an emitter is shorted with a terminal serving as a gate or a base; in a case where the voltage dividing module is the fourth resistor, one end of the fourth resistor serves as the second input terminal, and the other end is connected to the node.
According to still another aspect of the present invention, in the bias circuit, the first transistor, the second transistor, and the amplifying transistor are all N-channel MOS field effect transistors, or all P-channel MOS field effect transistors, or all PNP type transistors, or all NPN type transistors.
According to still another aspect of the present invention, in the bias circuit, N is equal to 2.
The utility model also provides an amplifier, this amplifier includes:
the bias circuit comprises two or more amplifying transistors and the bias circuit, wherein the number of bias units in the bias circuit is the same as that of the amplifying transistors and corresponds to that of the amplifying transistors one to one, the first transistor in each bias unit is the same as that of the amplifying transistor corresponding to the first transistor, and the second output end of each bias unit is connected to a terminal, serving as a grid or a base, of the amplifying transistor corresponding to the second transistor and used for providing working voltage for the amplifying transistor;
an input matching circuit provided at an input of the amplifier for impedance matching of the input of the amplifier and/or an output matching circuit provided at an output of the amplifier for impedance matching of the output of the amplifier.
According to another aspect of the present invention, in the amplifier, a terminal of the amplifying transistor corresponding to the 1 st bias unit as a drain or a collector is connected to a voltage source, a terminal of the amplifying transistor corresponding to the i-th bias unit as a source or an emitter is connected to a terminal of the amplifying transistor corresponding to the i +1 th bias unit as a drain or a collector, and a terminal of the amplifying transistor corresponding to the N-th bias unit as a source or an emitter is grounded, wherein i is greater than or equal to 1 and less than or equal to N-1.
According to yet another aspect of the invention, in the amplifier, the amplifier is a power amplifier or a low noise amplifier.
The utility model also provides a radio frequency front end module, this radio frequency front end module includes at least one aforementioned amplifier.
The utility model provides a biasing circuit includes N (N is greater than or equal to 2) biasing units, and each biasing unit is used for being connected and providing operating voltage for it with corresponding amplifier transistor. For each bias unit, the bias unit comprises a first transistor which has the same type as the amplifying transistor corresponding to the bias unit, and after the bias unit is connected with the amplifying transistor corresponding to the bias unit, the first transistor and the amplifying transistor in the bias unit form a current mirror structure. In this case, when the process corner affects the amplifying transistor to cause the threshold voltage of the amplifying transistor to float, the threshold voltage of the first transistor also floats under the influence of the process corner, and the floating of the threshold voltage of the first transistor can compensate the floating of the threshold voltage of the amplifying transistor, so that the influence of the floating of the threshold voltage of the amplifying transistor on the quiescent current of the amplifier can be effectively reduced. That is to say, compare in present partial pressure formula biasing circuit, will the utility model provides a when biasing circuit is applied to the amplifier, not only can provide operating voltage for the amplifier transistor in the amplifier, can also effectively reduce the influence of technology angle to amplifier quiescent current, make the stability of amplifier promote. Based on the utility model provides an amplifier that biasing circuit realized is because its quiescent current receives the influence of technology angle little, consequently has the good characteristics of stability. Based on the utility model provides a corresponding good characteristics of stability that also have of radio frequency front end module that amplifier realized.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:
FIG. 1 is a circuit diagram of a prior art amplifier;
fig. 2 is a circuit diagram of an amplifier according to an embodiment of the present invention, wherein the amplifying transistor and the first transistor are both field effect transistors;
fig. 3 is a circuit diagram of an amplifier according to another embodiment of the present invention, wherein the amplifying transistor and the first transistor are both transistors;
fig. 4 to 8 are circuit diagrams of amplifiers according to five preferred embodiments of the present invention.
The same or similar reference numbers in the drawings identify the same or similar elements.
Detailed Description
For a better understanding and explanation of the present invention, reference will now be made in detail to the present invention, which is illustrated in the accompanying drawings.
The utility model provides a biasing circuit, this biasing circuit includes:
n biasing units, wherein N is an integer and is more than or equal to 2;
the N bias units correspond to the N amplifying transistors one to one, each bias unit is used for being connected with the corresponding amplifying transistor and providing working voltage for the amplifying transistor, each bias unit comprises a first transistor, the type of the first transistor is the same as that of the amplifying transistor corresponding to the bias unit, and the first transistor and the amplifying transistor form a current mirror structure.
The bias circuit provided by the present invention will be described with reference to the accompanying drawings.
Specifically, the present invention provides a bias circuit including N bias cells, where N is an integer greater than or equal to 2. When utilizing the utility model provides a biasing circuit constructs the amplifier, a N biasing unit and a N amplifier transistor one-to-one, each biasing unit is used for being connected and providing operating voltage for it with its amplifier transistor that corresponds. The present invention does not limit the number of the bias units in the bias circuit, considering that the number of the bias units in the bias circuit depends on the number of the amplifying transistors in the amplifier, i.e. the number of N is related to the actual design requirement of the amplifier.
In this embodiment, each bias unit includes a first transistor, which is a field effect transistor or a triode. It will be understood by those skilled in the art that the present invention is not limited to any particular type of fet or transistor. The field effect transistor may be a junction field effect transistor, an N-channel metal oxide semiconductor field effect transistor, or a P-channel metal oxide semiconductor field effect transistor. For the triode, the triode can be a PNP type transistor or an NPN type transistor. It should be noted that the specific type of the first transistor in the bias unit is related to the amplifying transistor of the working voltage provided by the bias unit. Specifically, the type of the first transistor in each bias unit needs to be the same as the type of the amplifying transistor corresponding to the bias unit. The amplifying transistor is for example an N-channel metal oxide semiconductor field effect transistor and correspondingly the first transistor in the biasing unit providing the operating voltage for the amplifying transistor is also an N-channel metal oxide semiconductor field effect transistor. Also for example, the amplifying transistor is a PNP type transistor, and accordingly, the first transistor in the bias unit that supplies the operating voltage to the amplifying transistor is also a PNP type transistor. In terms of device types, the first transistor in each bias unit is the same as the amplifying transistor corresponding to the bias unit. In the circuit structure, the first transistor in each bias unit and the amplifying transistor corresponding to the bias unit form a current mirror structure. It should be noted that, the present invention does not limit the specific structure of each bias unit, and besides the first transistor, other components such as a resistor can be correspondingly arranged according to the actual design requirement, and the present invention does not limit this. In view of the many possibilities for practical design requirements, and correspondingly, the structure of the bias circuit, there are many possibilities, and for the sake of brevity, all of the possible structures of each bias circuit are not listed here.
The utility model provides a biasing circuit includes N (N is greater than or equal to 2) biasing units, and each biasing unit is used for being connected and providing operating voltage for it with corresponding amplifier transistor. The first transistor in each bias unit and the amplifying transistor corresponding to the bias unit are of the same type and form a current mirror structure. Therefore, when the threshold voltage of the amplifying transistor is influenced by the process corner and floats, the first transistor also floats under the influence of the process corner, and the floating of the threshold voltage of the amplifying transistor can be compensated by the floating of the threshold voltage of the first transistor, so that the influence of the floating of the threshold voltage of the amplifying transistor on the quiescent current of the amplifier can be effectively reduced. That is to say, compare in present partial pressure formula biasing circuit, will the utility model provides a when biasing circuit is applied to the amplifier, not only can provide operating voltage for the amplifier transistor in the amplifier, can also effectively reduce the influence of technology angle to amplifier quiescent current, make the stability of amplifier promote.
The bias circuit provided by the present invention will be described with reference to specific embodiments. It is to be noted that, in the following description, the three terminals of a transistor (including an amplifying transistor, a first transistor, and other transistors described later) are denoted by a first terminal, a second terminal, and a third terminal. Wherein, for the case where the transistor is a field effect transistor, the first terminal is a drain, the second terminal is a source, and the third terminal is a gate; for the case where the transistor is a triode, the first terminal is the collector, the second terminal is the emitter, and the third terminal is the base.
In one embodiment, as shown in FIG. 2, the bias circuit 10 includes N (N ≧ 2) bias units, which are in one-to-one correspondence with N amplifying transistors, i.e., each bias unit provides an operating voltage for its corresponding amplifying transistor. In fig. 2, the ith bias unit is denoted by reference numeral 10' u i, and the amplifier transistor corresponding to the ith bias unit is denoted by reference numeral M i0 Wherein i =1,2, \ 8230, N. In the present embodiment, the ith bias unit includes a first transistor M i1 A first resistor R i1 A second resistor R i2 A third resistor R i3 And a voltage division module A i I =1,2, \8230N. First transistor M in the ith bias unit i1 And an amplifying transistor M corresponding to the ith bias unit i0 The field effect transistors are of the same type, and the two form a current mirror structure. As shown in the figure, in the ith bias unit, a first resistor R i1 One terminal of the first transistor M is used as the first input terminal of the bias unit, the other terminal of the first transistor M is used as the first transistor M i1 Is connected to the first terminal (drain); first transistor M i1 As a first output terminal of the bias unit; first transistor M i1 Is connected to the second resistor R i2 While the first transistor M is turned on i1 A third terminal (gate) and a first terminal (drain) are shorted; a second resistor R i2 Is connected to a third resistor R at the other end i3 One terminal of (1), a third resistor R i3 The other end of the first output terminal is used as a second output terminal of the bias unit; voltage dividing module A i One end of the first resistor is used as the second input end of the bias unit, and the other end of the first resistor is connected to the second resistor R i2 And a third resistor R i3 On the node in between. Wherein, the first input terminal of the 1 st bias unit is connected to the voltage source VDD 10 (ii) a The first output end of the ith bias unit is connected to the first input end of the (i + 1) th bias unit, wherein i =1,2, \8230, N-1; the Nth bias unitAn output terminal is grounded. Voltage Source VDD 10 After being stepped down, the voltage is respectively provided for the first terminal of the first transistor in each bias unit. In addition, the second input terminal of the ith bias unit is connected to the voltage source VDD i1 A second output terminal connected to the amplifying transistor M corresponding to the ith bias unit i0 A third terminal (gate) of the voltage source VDD i1 Through a partial pressure module A i And a third resistor R i3 An amplifying transistor M corresponding to the ith bias unit after voltage reduction i0 Wherein i =1,2, \8230n, N.
In another embodiment, as shown in FIG. 3, the bias circuit 10 also includes N (N ≧ 2) bias units, which correspond one-to-one to the N amplifying transistors. The only difference from the bias circuit of fig. 2 is that the first transistor Q in the ith bias cell in the bias circuit of fig. 3 i1 And an amplifying transistor Q corresponding to the ith bias unit i0 Is the same type of triode.
Note that (1) the voltage source VDD in FIG. 2 and FIG. 3 10 And a voltage source VDD i1 (i =1,2, \ 8230; (N)) can be designed as the same voltage source or different independent voltage sources according to the actual design requirements, and the present invention does not limit the same; (2) In fig. 2 and 3, the amplifying transistor corresponding to the 1 st bias cell has its first terminal (drain) connected to the voltage source VDD 20 (ii) a The second terminal (source) of the amplifying transistor corresponding to the ith bias cell is connected to the first terminal (drain) of the amplifying transistor corresponding to the (i + 1) th bias cell, wherein i =1,2, \8230; N-1; the second terminal (source) of the amplifying transistor corresponding to the nth bias unit is grounded. It should be noted that, when the bias circuit provided by the present invention provides the operating voltage for the N amplifying transistors, there is no limitation on the layout of the N amplifying transistors. That is to say, the layout of the N amplifying transistors is merely an illustrative example, in other embodiments, the N amplifying transistors may adopt a corresponding layout according to actual design requirements, and for the sake of simplicity, the layout of the N amplifying transistors is not repeated herePossible layout modes are listed one by one; (3) In a preferred embodiment, as shown in fig. 8, N is equal to 2, i.e. the biasing circuit comprises two biasing units providing the operating voltages for the two amplifying transistors. For the case where N is equal to 2, the bias circuit and the two amplifying transistors form a cascode current mirror structure.
The utility model discloses do not specifically prescribe a limit to the structure of partial pressure module, all can realize that the structure of partial pressure function all is applicable to the utility model discloses a partial pressure module. In a preferred embodiment, the voltage dividing module in each bias unit is implemented by using a second transistor or a fourth resistor. For the case that the voltage division module is implemented by using the second transistor, the second transistor needs to be of the same type as the first transistor in the bias unit where the second transistor is located. That is, if the first transistor in the bias unit is a field effect transistor, the second transistor used by the voltage divider module in the bias unit should be the same type of field effect transistor. If the first transistor in the bias unit is a triode, the second transistor used by the voltage dividing module in the bias unit should be a triode of the same type. In this embodiment, the first terminal of the second transistor is used as the second input terminal of the bias unit, and the second terminal is connected to a node between the second resistor and the third resistor. Further, the second terminal and the third terminal of the second transistor are both shorted. For the case that the voltage division module is implemented by adopting a fourth resistor, one end of the fourth resistor is used as a second output end of the bias unit, and the other end of the fourth resistor is connected to a node between the second resistor and the third resistor. It can be understood by those skilled in the art that, for the case that the bias circuit includes two or more bias units, the voltage dividing modules in all bias units may all be implemented by using the second transistor, the voltage dividing modules in all bias units may also be implemented by using the fourth resistor, the voltage dividing modules in some bias units may also be implemented by using the second transistor, and the voltage dividing modules in the other bias units may also be implemented by using the fourth resistor, which is not limited by the present invention.
The following description will be made with reference to specific examples. As shown in FIG. 4, the bias circuit 10 includes N bias units (N ≧ 2), the ith biasThe first transistor in the cell is a field effect transistor M i1 Realization, voltage dividing module A i Using field effect transistors M i1 Field effect transistor M of the same type i2 The method is realized, wherein i =1,2, \ 8230, N. As shown in FIG. 5, the bias circuit 10 includes N bias units (N ≧ 2), and the first transistor in the ith bias unit is a field effect transistor M i1 Realization, voltage dividing module A i Using a fourth resistor R i4 The method is realized, wherein i =1,2, \ 8230, N. As shown in fig. 6, the bias circuit 10 includes N bias units (N is greater than or equal to 2), the first transistors in all bias units are implemented by field effect transistors, the voltage dividing modules in some bias units are implemented by fourth resistors, and the voltage dividing modules in the other bias units are implemented by second transistors. As shown in FIG. 7, the bias circuit 10 includes N bias units (N ≧ 2), and the first transistor in the ith bias unit is a transistor Q i1 Realization, voltage dividing module A i By means of an and-transistor Q i1 Triode Q of the same type i2 The method is realized, wherein i =1,2, \8230N.
Correspondingly, the utility model also provides an amplifier, this amplifier includes:
the bias circuit comprises two or more than two amplifying transistors and the bias circuit, wherein the number of bias units in the bias circuit is the same as that of the amplifying transistors and corresponds to the amplifying transistors one by one, the type of the first transistor in each bias unit is the same as that of the amplifying transistor corresponding to the first transistor, and the second output end of each bias unit is connected to a terminal, serving as a grid or a base, of the amplifying transistor corresponding to the second output end of the bias unit and used for providing working voltage for the amplifying transistors;
an input matching circuit provided at an input of the amplifier for impedance matching of the input of the amplifier and/or an output matching circuit provided at an output of the amplifier for impedance matching of the output of the amplifier.
The components of the amplifier provided by the present invention will be described with reference to fig. 2 to 7.
In particular, as shown in the figureAs shown, the amplifier provided by the present invention comprises N (N is not less than 2) amplifying transistors (the ith amplifying transistor is marked with the reference number M) i0 Or Q i0 Where i =1,2, \ 8230n), and a bias circuit 10 for providing an operating voltage to the N amplifying transistors, where the bias circuit 10 is implemented by the aforementioned bias circuit of the present invention, and the structure of the bias circuit will not be described again here for the sake of brevity.
In this embodiment, the number of the bias units and the number of the amplifying transistors in the bias circuit are the same, and the bias units and the amplifying transistors in the bias circuit are in one-to-one correspondence, that is, each bias unit provides the operating voltage for the corresponding amplifying transistor. As shown, the bias circuit 10 includes N bias units (an ith bias unit is denoted by reference numeral 10_i), wherein the second output terminal of the ith bias unit 10_iand the ith amplifying transistor M i0 Or Q i0 Is connected to realize that it is supplied with an operating voltage, wherein i =1,2, \ 8230n. In addition, the first transistor in each bias unit is the same as the corresponding amplifying transistor in type and forms a current mirror structure.
In this embodiment, the N amplification transistors are connected in sequence as shown in the figure. Specifically, the first terminal (drain or collector) of the 1 st amplifying transistor is connected to the voltage source VDD 20 (ii) a The second terminal (source or emitter) of the ith amplification transistor is connected to the first terminal (drain or collector) of the (i + 1) th amplification transistor, wherein 1 ≦ i ≦ N-1; the second terminal (source or emitter) of the nth amplifying transistor is grounded. As will be understood by those skilled in the art, the present invention (1) is not limited to the layout connection manner of the N amplifying transistors in the amplifier, the layout connection manner of the N amplifying transistors in fig. 2 to 7 is only an illustrative example, in other embodiments, the N amplifying transistors may be correspondingly arranged and connected according to the actual design requirement, and for the sake of simplicity, all possible layout connection manners of the N amplifying transistors are not listed. (2) In this embodiment, all amplifying transistors in the amplifier are of the same type, but this should not be assumed for the present inventionThe limitations of the utility model, the specific choice of the type of each amplifying transistor in the amplifier depends on the actual design requirements.
The utility model provides an amplifier is still including input matching circuit and output matching circuit, should input matching circuit setting at the input of amplifier, be used for realizing the impedance match of amplifier input, should output matching circuit setting at the output of amplifier for realize the impedance match of amplifier output. In this embodiment, one end of the input matching circuit 20 is connected to the input RF of the amplifier as shown in the figure in The other end is connected to the Nth (N ≧ 2) amplifying transistor (denoted by reference numeral M in the figure) N0 Or Q N0 A third terminal (gate or base); one end of the output matching circuit 30 is connected to the 1 st amplifying transistor (denoted by reference numeral M in the figure) 10 Or Q 10 Shown), the other end is connected to the output RF of the amplifier out . Those skilled in the art will appreciate that (1) in other embodiments, the amplifier may also include only input matching circuitry or only output matching circuitry, depending on the actual design requirements. (2) The utility model discloses do not do any restriction to the concrete structure of input matching circuit and output matching circuit, all be applicable to in amplifier input and output circuit structure that is used for realizing impedance matching the utility model discloses an input matching circuit and output matching circuit, for the sake of conciseness, no longer carry out the list one by one here to all possible structures of input matching circuit and output matching circuit.
It should be noted that (1) the present invention is not limited to any specific type of amplifier, and may be a Power Amplifier (PA) or a Low Noise Amplifier (LNA), or may be any other amplifier that needs to provide an operating voltage for an amplifying transistor through a bias circuit, and for the sake of simplicity, all possible types of amplifiers are not listed here. (2) The amplifier in the utility model can be a single-stage amplifier or a multi-stage amplifier. For multistage amplifier, N amplifier transistor distributes in each grade of amplifier, to the quantity and the overall arrangement connected mode of amplifier transistor in each grade amplifier the utility model discloses do not do any restriction.
The utility model provides an amplifier includes two and above amplifier transistor and bias circuit, and wherein bias circuit includes the same and the one-to-one biasing unit of one-to-one with amplifier transistor quantity, and each biasing unit is used for providing operating voltage for the amplifier transistor rather than corresponding. Each bias unit comprises a first transistor, the type of the first transistor is the same as that of the corresponding amplifying transistor, and the first transistor and the amplifying transistor in the bias unit form a current mirror structure. In this case, when the process corner affects the amplifying transistor to cause the threshold voltage of the amplifying transistor to float, the threshold voltage of the first transistor also floats under the influence of the process corner, and the floating of the threshold voltage of the first transistor can compensate the floating of the threshold voltage of the amplifying transistor, so that the influence of the floating of the threshold voltage of the amplifying transistor on the quiescent current of the amplifier can be effectively reduced. That is to say, compare in the present amplifier that adopts the partial pressure formula biasing circuit, the utility model provides an its quiescent current of amplifier receives the influence of technology angle little, consequently has the good characteristics of stability.
The effect of the bias circuit provided by the present invention is explained by the simulation result. Referring to fig. 8, the amplifier shown in fig. 8 and the amplifier shown in fig. 1 have two amplifying transistors, and the difference is only that the amplifier shown in fig. 8 uses the bias circuit provided by the present invention, and the amplifier shown in fig. 1 uses the existing voltage-dividing bias circuit. The results obtained in the background art referring to simulations of the amplifier of fig. 1 at different process angles show that the amplifier of fig. 1 has a quiescent current target value of 20.8mA, while the quiescent current values of the amplifier at the Slow process angle and at the Fast process angle are 2.21mA and 48mA, respectively. The results from the same simulation performed on the amplifier shown in FIG. 8 show that the target value for the quiescent current of the amplifier shown in FIG. 8 is 20.7mA, and the values for the quiescent current of the amplifier at the Slow process angle and at the Fast process angle are 16.8mA and 19.4mA, respectively. Can obviously see out through the simulation result, the value and the target value deviation of its quiescent current of amplifier that fig. 8 shows are less under Slow technology angle and Fast technology angle, promptly the utility model provides a bias circuit can effectively reduce the influence of technology angle to amplifier quiescent current, and then effectively promote amplifier's stability.
The utility model also provides a radio frequency front end module, this radio frequency front end module include at least one amplifier, wherein, this amplifier adopts the utility model discloses aforementioned amplifier realizes, for the sake of conciseness, no longer describes the structure of amplifier again here. It should be noted that, in general, the rf front-end module includes an antenna, an rf switch, a duplexer group, and the like in addition to the amplifier. It can be understood by those skilled in the art that all rf front-end modules formed by using the amplifier provided by the present invention fall within the scope protected by the present invention, and for the sake of brevity, all the possibilities of the rf front-end modules provided by the present invention are not listed one by one. Because the utility model provides an amplifier stability is good, so the radio frequency front end module based on this amplifier formation also correspondingly has the good characteristics of stability.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it will be obvious that the term "comprising" does not exclude other elements, components or steps, and the singular does not exclude the plural. A plurality of components, units or means recited in the system claims may also be implemented by one component, unit or means in software or hardware.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the scope of the invention, which is defined by the appended claims.
Claims (9)
1. A bias circuit, comprising:
n biasing units, wherein N is an integer and is more than or equal to 2;
the N bias units correspond to the N amplifying transistors one to one, each bias unit is used for being connected with the corresponding amplifying transistor and providing working voltage for the amplifying transistor, each bias unit comprises a first transistor, the type of the first transistor is the same as that of the amplifying transistor corresponding to the bias unit, and the first transistor and the amplifying transistor form a current mirror structure.
2. The bias circuit of claim 1, wherein:
each bias unit further comprises a first resistor, a second resistor, a third resistor and a voltage dividing module, wherein one end of the first resistor is used as a first input end of the bias unit, the other end of the first resistor is connected to a terminal of the first transistor as a drain or a collector, a terminal of the first transistor as a source or an emitter is used as a first output end of the bias unit, a terminal of the first transistor as a drain or a collector and a terminal as a gate or a base are shorted, one end of the second resistor is connected to a terminal of the first transistor as a gate or a base, the other end of the second resistor is connected to one end of the third resistor, the other end of the third resistor is used as a second output end of the bias unit, and one end of the voltage dividing module is used as a second input end of the bias unit, and the other end of the voltage dividing module is connected to a node between the second resistor and the third resistor;
the first input end of the 1 st bias unit and the second input ends of all the bias units are used for being connected with a voltage source; the first output end of the ith bias unit is connected to the first input end of the (i + 1) th bias unit, the first output end of the Nth bias unit is used for grounding, wherein i is more than or equal to 1 and less than or equal to N-1; the second output end of each bias unit is used for being connected with the terminal of the corresponding amplifying transistor serving as a grid electrode or a base electrode.
3. The bias circuit of claim 2, wherein:
the voltage division module comprises a second transistor or a fourth resistor;
for the case that the voltage dividing module comprises the second transistor, the second transistor is of the same type as the first transistor in the bias unit where the second transistor is located, wherein a terminal of the second transistor serving as a drain or a collector is used as the second input terminal, a terminal of the second transistor serving as a source or an emitter is connected to the node, and the terminal of the second transistor serving as the source or the emitter is shorted with a terminal serving as a gate or a base;
in a case where the voltage dividing module is the fourth resistor, one end of the fourth resistor serves as the second input terminal, and the other end is connected to the node.
4. The bias circuit of claim 3, wherein:
the first transistor, the second transistor and the amplifying transistor are all N-channel MOS field effect transistors, or all P-channel MOS field effect transistors, or all PNP type transistors, or all NPN type transistors.
5. The bias circuit of claim 1, wherein N is equal to 2.
6. An amplifier, the amplifier comprising:
two or more amplifying transistors and a bias circuit according to any one of claims 1 to 5, wherein the number of the bias units is the same as the number of the amplifying transistors and corresponds to one, and the first transistor in each bias unit is the same as the type of the amplifying transistor corresponding to the first transistor, wherein the second output end of each bias unit is connected to a terminal of the amplifying transistor corresponding to the second output end of the bias unit, which is used for providing a working voltage for the amplifying transistor;
an input matching circuit provided at an input of the amplifier for impedance matching of the input of the amplifier and/or an output matching circuit provided at an output of the amplifier for impedance matching of the output of the amplifier.
7. The amplifier of claim 6, wherein:
the terminal of the drain or collector of the amplifying transistor corresponding to the 1 st bias unit is connected to a voltage source, the terminal of the source or emitter of the amplifying transistor corresponding to the i-th bias unit is connected to the terminal of the drain or collector of the amplifying transistor corresponding to the i +1 th bias unit, and the terminal of the source or emitter of the amplifying transistor corresponding to the N-th bias unit is grounded, wherein i is greater than or equal to 1 and less than or equal to N-1.
8. An amplifier according to claim 6 or 7, wherein the amplifier is a power amplifier or a low noise amplifier.
9. A RF front-end module, comprising at least one amplifier as claimed in any one of claims 6 to 8.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222377844.0U CN218217309U (en) | 2022-09-07 | 2022-09-07 | Biasing circuit, amplifier and radio frequency front end module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222377844.0U CN218217309U (en) | 2022-09-07 | 2022-09-07 | Biasing circuit, amplifier and radio frequency front end module |
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| Publication Number | Publication Date |
|---|---|
| CN218217309U true CN218217309U (en) | 2023-01-03 |
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|---|---|---|---|
| CN202222377844.0U Active CN218217309U (en) | 2022-09-07 | 2022-09-07 | Biasing circuit, amplifier and radio frequency front end module |
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| Country | Link |
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| CN (1) | CN218217309U (en) |
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2022
- 2022-09-07 CN CN202222377844.0U patent/CN218217309U/en active Active
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