CN218039192U - Semiconductor device with a plurality of semiconductor chips - Google Patents

Semiconductor device with a plurality of semiconductor chips Download PDF

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Publication number
CN218039192U
CN218039192U CN202221610423.1U CN202221610423U CN218039192U CN 218039192 U CN218039192 U CN 218039192U CN 202221610423 U CN202221610423 U CN 202221610423U CN 218039192 U CN218039192 U CN 218039192U
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China
Prior art keywords
buffer
chip
buffer layer
positioning
semiconductor device
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CN202221610423.1U
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Chinese (zh)
Inventor
潘奇雯
吴彦
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Yangzhou Byd Semiconductor Co ltd
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BYD Semiconductor Co Ltd
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Priority to CN202221610423.1U priority Critical patent/CN218039192U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48491—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being an additional member attached to the bonding area through an adhesive or solder, e.g. buffer pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

Abstract

The utility model discloses a semiconductor device, including base plate, chip and buffer layer, the base plate is located to the chip, and the chip middle part is equipped with gate level circuit, and gate level circuit has the lead wire that extends along the first direction, and the chip has at least one chip side edge that extends along the second direction. The buffer layer is arranged on the chip and electrically connected with the chip and the substrate, and is provided with at least two first positioning points arranged along a first direction at intervals and at least two second positioning points arranged along a second direction at intervals. The connecting line of the two first positioning points is parallel to the lead wire so as to position the buffer layer in the second direction, and the connecting line of the two second positioning points is parallel to the side edge so as to position the buffer layer in the first direction. According to the utility model discloses a semiconductor device can realize improving the position accuracy between buffer layer and the chip to the whole location of buffer layer, avoids taking place the skew between buffer layer and the chip, and then improves the yields of semiconductor device production.

Description

Semiconductor device with a plurality of semiconductor chips
Technical Field
The utility model relates to the field of semiconductor technology, more specifically relates to a semiconductor device.
Background
The third generation of semiconductor high power electronic devices represented by SiC is one of the fastest developing power semiconductor devices in the power electronic field at present. The semiconductor has the advantages of high efficiency, high speed, high temperature resistance and high reliability, and is very suitable for being used in new energy automobiles.
The traditional chip upper layer interconnection technology needs to use Al wire bonding to realize the connection between the chip and the chip substrate. The area of the upper metal layer of the SiC chip is reduced by 3-5 times compared with that of the traditional chip, so that the traditional Al wire bonding can not meet the requirement. For SiC chips, cu wire bonding is usually chosen to achieve the connection between the chip and the chip substrate. The problem of thermoelectric transmission is solved by adopting Cu wire bonding, but the upper layer of the chip is easy to damage.
In the prior art, a buffer layer, which may be a Cu buffer layer, is sintered on the surface of a SiC chip, and then a Cu wire is bonded to the Cu buffer layer, thereby implementing a chip and a chip substrate. However, since the size of the buffer layer is too small, it is difficult to position the buffer layer in the process of connecting the buffer layer and the chip, which easily causes an offset between the buffer layer and the chip.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a semiconductor device's new technical scheme can solve among the prior art at least and be difficult to the problem of buffer layer location.
The utility model provides a semiconductor device, include: a substrate; the chip is arranged on the substrate, a gate-level circuit is arranged in the middle of the chip and provided with a lead extending along a first direction, and the chip is provided with at least one chip side edge extending along a second direction; the buffer layer is arranged on the chip and electrically connected with the chip and the substrate, the buffer layer is provided with at least two first positioning points which are arranged along the first direction at intervals and at least two second positioning points which are arranged along the second direction at intervals, wherein the connecting line of the two first positioning points is parallel to the lead so as to position the buffer layer in the second direction, and the connecting line of the two second positioning points is parallel to the side edge so as to position the buffer layer in the first direction.
Optionally, the buffer layer has two buffer side edges extending along the second direction, and each of the buffer side edges is provided with one first positioning point and two second positioning points, respectively.
Optionally, each of the buffer side edges is respectively provided with a positioning groove recessed toward the middle of the buffer layer, and the first positioning point and the second positioning point are respectively located in the positioning groove.
Optionally, the positioning groove is a triangular groove, the two second positioning points are respectively a vertex of the positioning groove located on the edge of the buffer side, and the first positioning point is another vertex of the positioning groove.
Optionally, the positioning groove is a rectangular groove, a trapezoidal groove, a tapered groove or a profiled groove.
Optionally, the buffer layer comprises: the first buffer part and the second buffer part are respectively positioned above the chip and are respectively connected with the chip, and the first buffer part and the second buffer part are positioned on two sides of the lead; the buffer connecting part is arranged between the first buffer part and the second buffer part to connect the first buffer part and the second buffer part.
Optionally, the buffer connecting portion is connected to a side surface of the first buffer portion and the second buffer portion, which is far away from the substrate, and a horizontal height of the buffer connecting portion is higher than a horizontal height of the first buffer portion and the second buffer portion.
Optionally, the semiconductor device further comprises: and one end of the bonding connecting part is connected with the buffer layer, and the other end of the bonding connecting part is connected with the substrate.
Optionally, the bonding connection is a metal bonding wire.
Optionally, the bonding connection part is integrally formed with the buffer layer.
According to the utility model discloses a semiconductor device, through two at least first locating points and two at least second locating points of locating the buffer layer, the line that makes two first locating points is parallel with the lead wire that extends along the first direction, the line of two second locating points is parallel along the chip side that extends along the second direction on with the chip, can fix a position the buffer layer in second direction and first direction respectively, thereby realize the whole location to the buffer layer, improve the position accuracy between buffer layer and the chip, avoid taking place the skew between buffer layer and the chip, and then improve the yields of semiconductor device production.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a perspective view of a semiconductor device according to a first embodiment provided by the present invention;
fig. 2 is a top view of a semiconductor device according to a first embodiment of the present invention;
fig. 3 is a perspective view of a semiconductor device according to a second embodiment of the present invention;
fig. 4 is a perspective view of a semiconductor device according to a third embodiment of the present invention.
Reference numerals
A semiconductor device 100;
a substrate 10; a first metal layer 11; a non-metal layer 12; a second metal layer 13;
a chip 20; a device body 22; an upper-layer metal plate 23; chip side edges 24;
a buffer layer 30; a triangular groove 31; a first anchor point 311; a second anchor point 312; a buffer side edge 313; a first buffer 32; a second buffer 33; a buffer connection portion 34; a bonding connection portion 35; the first connecting portion 351; the second connection portion 352; a third connecting portion 353;
a first tie layer 40;
a second connection layer 50.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: unless specifically stated otherwise, the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present invention.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as exemplary only and not as limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
The semiconductor device 100 according to an embodiment of the present invention is described in detail below with reference to the drawings.
As shown in fig. 1 to 4, a semiconductor device 100 according to an embodiment of the present invention includes: substrate 10, chip 20 and buffer layer 30.
Specifically, the chip 20 is disposed on the substrate 10, a gate-level circuit is disposed in the middle of the chip 20, the gate-level circuit has a lead 21 extending along a first direction, the chip 20 has at least one chip side edge 24 extending along a second direction, the buffer layer 30 is disposed on the chip 20, the buffer layer 30 electrically connects the chip 20 and the substrate 10, the buffer layer 30 is provided with at least two first positioning points 311 spaced apart along the first direction and at least two second positioning points 312 spaced apart along the second direction, a connection line of the two first positioning points 311 is parallel to the lead 21 to position the buffer layer 30 in the second direction, and a connection line of the two second positioning points 312 is parallel to the chip side edge 24 to position the buffer layer 30 in the first direction.
In other words, the semiconductor device 100 according to the embodiment of the present invention is mainly composed of the substrate 10, the chip 20 provided on the substrate 10, and the buffer layer 30 provided on the chip 20, and for convenience of description, the substrate 10, the chip 20, and the buffer layer 30 may be arranged in this order from the bottom.
The substrate 10 is used for carrying a chip 20, a gate level circuit in the chip 20 is located in the middle of the chip 20, a lead 21 of the gate level circuit extends along a first direction, and the chip 20 has at least one chip side edge 24 extending along a second direction. Specifically, the chip 20 may be a rectangular chip, the second direction may be an extending direction of one side of the chip 20, and the first direction may be an extending direction of another adjacent side, that is, the first direction and the second direction may be perpendicular to each other, for example, the first direction may be an up-down direction as shown in fig. 2, and the second direction may be a left-right direction as shown in fig. 2.
It should be noted that the chip 20 may have other shapes, and it is only necessary to ensure that the first direction and the second direction are both parallel to the upper surface of the substrate 10, and the chip 20 has at least one chip side edge 24 extending along the second direction.
The buffer layer 30 is connected to the upper surface of the chip 20, the buffer layer 30 may be a sheet structure made of a metal material, and optionally, the buffer layer 30 is made of metal Cu to provide good electrical conductivity.
Optionally, a first connection layer 40 may be further disposed between the buffer layer 30 and the chip 20, the buffer layer 30 and the chip 20 are connected through the first connection layer 40, the first connection layer 40 may be made of a first material, and the first connection material may be a connection material with good conductivity.
The buffer layer 30 has at least two first positioning points 311 and at least two second positioning points 312, each of the first positioning points 311 being arranged at intervals in a first direction, and each of the second positioning points 312 being arranged at intervals in a second direction. The relative position between the buffer layer 30 and the chip 20 may be located in the second direction by a connection line between the two first positioning points 311 being parallel to the lead 21, and the relative position between the buffer layer 30 and the chip 20 may be located in the first direction by a connection line between the two second positioning points 312 being parallel to the chip side edge 24 of the chip 20 extending in the second direction.
Specifically, the connection between the buffer layer 30 and the chip 20 will be described in detail by taking the chip 20 as a rectangular chip as an example.
In the process of connecting the buffer layer 30 and the chip 20, the chip 20 and the substrate 10 bearing the chip 20 are fixed on a tool, by moving the metal sheet as the buffer layer 30, the connecting line between the two first positioning points 311 on the buffer layer 30 is made parallel to the lead 21, and the connecting line between the two second positioning points 312 is made parallel to the side edge, and then the buffer layer 30 can be positioned in the second direction by setting the distance from the connecting line between the two first positioning points 311 to the lead 21, and similarly, the buffer layer 30 can be positioned in the first direction by setting the distance from the connecting line between the two second positioning points 312 to the side edge.
Alternatively, an orthogonal projection of a connecting line between the two first positioning points 311 on the chip 20 may be set to coincide with the lead 21, so as to position the buffer layer 30 in the second direction. At this time, the first positioning points 311 may be all located on a central line of the buffer layer 30, and the buffer layer 30 is positioned by a connection line of the two first positioning points 311 on the central line, so that the positioning is more accurate.
From this, according to the utility model discloses a semiconductor device 100, through two at least first locating point 311 and two at least second locating point 312 of locating buffer layer 30, make the line of two first locating point 311 parallel with the lead wire 21 that extends along the first direction, the line of two second locating point 312 is parallel along 24 with the chip side edge that extends along the second direction on the chip 20, can fix a position buffer layer 30 in second direction and first direction respectively, thereby realize the overall positioning to buffer layer 30, improve the position precision between buffer layer 30 and the chip 20, avoid taking place the skew between buffer layer 30 and the chip 20, and then improve the yields of semiconductor device production.
According to an embodiment of the present invention, the buffer layer 30 has two buffer side edges 313 extending along the second direction, and each buffer side edge 313 is provided with a first positioning point 311 and two second positioning points 312.
Specifically, the buffer layer 30 is a sheet structure and has two buffer side edges 313 extending along the second direction, the two buffer side edges 313 are distributed at intervals along the first direction, the two buffer side edges 313 are respectively provided with one first positioning point 311, and the connection line of the two first positioning points 311 is parallel to the lead 21, so that the buffer layer 30 can be positioned in the second direction. The two buffer side edges 313 are respectively provided with two second positioning points 312, and the connecting line of the two second positioning points 312 arranged on the same buffer side edge 313 is parallel to the chip side edge 24, so that the buffer layer 30 can be positioned in the first direction.
By providing the first positioning point 311 and the second positioning point 312 at the buffer-side edge 313, the structure is simple, the manufacturing is easy, and the performance of the buffer layer 30 is not affected.
In some embodiments of the present invention, each buffer side edge 313 is respectively provided with a positioning groove recessed toward the middle of the buffer layer 30, and the first positioning point 311 and the second positioning point 312 are respectively located at the positioning grooves.
Specifically, each buffer side edge 313 is provided with a positioning groove, the positioning groove is recessed from the side edge of the buffer layer 30 to the middle of the buffer layer 30, and each positioning groove has a first positioning point 311 and two second positioning points 312. The first positioning point 311 and the second positioning point 312 may be vertexes of a positioning groove, and the two second positioning points 312 are spaced apart on the positioning groove in the second direction.
The positioning groove is formed in the buffer layer 30, so that the production and the processing are easy, and the positioning accuracy of the buffer layer 30 can be improved in the connection process of the buffer layer 30 and the chip 20 only by reprocessing the existing buffer layer 30.
According to an embodiment of the present invention, the positioning groove is a triangular groove 31, the two second positioning points 312 are respectively the top points of the positioning groove located on the edge 313 of the buffering side, and the first positioning point 311 is another top point of the positioning groove.
Specifically, the positioning groove may be a triangular groove 31, and in the top view shown in fig. 2, the positioning groove has a triangular shape, and the triangular groove 31 has three vertexes, two vertexes are located at the side of the cushioning layer 30, and the other vertex is located in the cushioning layer 30, in other words, the cushioning side edge 313 is provided with a V-shaped notch, and the opening direction of the V-shaped notch faces outward.
The two second positioning points 312 are respectively the vertexes located at the sides of the buffer layer 30, and the first positioning point 311 is the vertex located in the buffer layer 30. The positioning of the buffer layer 30 in the first direction can be realized by arranging the triangular grooves 31 to be parallel to the chip side edges 24 at the connection lines of the vertexes of the same side of the buffer layer 30, and the positioning of the buffer layer 30 in the second direction can be realized by arranging the connection lines between the vertexes of the two triangular grooves 31 located in the buffer layer 30 to be parallel to the lead 21, so that the mounting accuracy of the buffer layer 30 is improved.
The buffer layer 30 is a rectangular buffer layer, and the chip 20 is a rectangular chip.
The first direction is the up-down direction as shown in fig. 2, and the second direction is the left-right direction as shown in fig. 2. Chip side edge 24 is a lower edge of chip 20, and buffer side edge 313 is an upper and lower edge of buffer layer 30. Triangular grooves 31 are respectively formed in the upper edge and the lower edge of the cushioning layer 30, the triangular grooves 31 are recessed into the cushioning layer 30, two of three vertexes of the triangular grooves 31 are located on the corresponding cushioning side edges 313, and the other vertex is located at the bottom of the groove. The line between the two vertices of the bottom of the trench may be the center line of the buffer layer 30, and the leads 21 of the gate level circuit coincide with the center line of the chip 20.
When the buffer layer 30 is connected, a connecting line between two vertexes of the lower edge of the buffer layer 30 may be parallel to the lower edge of the chip 20, and the position of the buffer layer 30 in the first direction may be positioned by setting a distance therebetween. A line between two apexes of the groove bottom is parallel to the lead 21, and the position of the buffer layer 30 in the second direction is positioned by setting the distance therebetween.
Preferably, the buffer layer 30 can be positioned by coinciding the orthogonal projection of the line between the two vertices of the groove bottom on the chip 20 with the lead 21. The buffer layer 30 is positioned through a connecting line of the two first positioning points 311 in the middle, and the positioning is more accurate.
According to an embodiment of the present invention, the positioning groove is a rectangular groove, a trapezoidal groove, a tapered groove, or a special-shaped groove.
Specifically, the positioning groove may be a positioning groove with various shapes, and the positioning of the buffer layer 30 may be achieved as long as two positioning grooves respectively have at least one first positioning point 311, two first positioning points 311 are arranged at intervals in the first direction, and each positioning groove has two second positioning points 312 arranged at intervals in the second direction.
For example, when the positioning groove is a rectangular groove, the rectangular groove has four vertices, wherein the vertex on the buffer side edge 313 may be set as the second positioning point 312, and any one of two vertices in the buffer layer 30 may be set as the first positioning point 311. The positioning groove may have other shapes such as a trapezoid shape, a taper shape, or a special shape, and the description thereof is omitted here for brevity.
According to an embodiment of the present invention, the buffer layer 30 includes a first buffer portion 32, a second buffer portion 33, and a buffer connection portion 34.
Specifically, the first buffer portion 32 and the second buffer portion 33 are respectively located above the chip 20 and respectively connected to the chip 20, the first buffer portion 32 and the second buffer portion 33 are located at both sides of the lead 21, and the buffer connection portion 34 is provided between the first buffer portion 32 and the second buffer portion 33 to connect the first buffer portion 32 and the second buffer portion 33.
In other words, the cushion layer 30 is mainly composed of the first cushion part 32, the cushion connection part 34, and the second cushion part 33 connected in this order. The buffer connection portion 34 is located at a position corresponding to the position of the lead 21, the first buffer portion 32 is located at one side of the lead 21 and connected above the chip 20, and the second buffer portion 33 is located at the other side of the lead 21 and connected above the chip 20.
It should be noted that the chip 20 may include a device main body 22, a gate level circuit, and two upper metal plates 23 in sequence from bottom to top. The device body 22 is disposed on the substrate 10, two upper metal plates 23 may be spaced apart along the second direction, the leads 21 of the gate-level circuit are located between the two upper metal plates 23, and the buffer layer 30 is connected to the chip 20 by the upper metal plates 23 of the chip 20.
Specifically, the first buffer portion 32 and the second buffer portion 33 may be connected to the corresponding upper metal plates 23, respectively, for example, as shown in fig. 3, the first buffer portion 32 is located on the left side of the lead 21, the second buffer portion 33 is located on the right side of the lead 21, the first buffer portion 32 is connected to the upper metal plate 23 on the left side of the lead 21, and the second buffer portion 30 is connected to the upper metal plate 23 on the right side of the lead 21. The buffer connection 34 is located directly above the lead 21, and the buffer connection 34 extends in a first direction, and two first positioning points 311 may be disposed at both ends of the buffer connection 34 at intervals in the first direction.
Preferably, the edges of the first and second buffer parts 32 and 33 are arc-shaped edges, which may easily cause degradation of the connection portion during operation of the chip 20, compared to right-angled edges, and may improve the reliability of the connection between the first and second buffer parts 32 and 33 and the chip 20.
According to an embodiment of the present invention, the buffer connecting portion 34 is connected to a side surface of the first buffer portion 32 and the second buffer portion 33, which is far away from the substrate 10, and a level of the buffer connecting portion 34 is higher than a level of the first buffer portion 32 and the second buffer portion 33.
In other words, the distance between the buffer connection part 34 and the substrate 10 is greater than the distance between the first buffer part 32 and the second buffer part 33 and the substrate 10. The first buffer portion 32 and the second buffer portion 33 are both flat plate-shaped structures, and the buffer connecting portion 34 protrudes from the first buffer portion 32 and the second buffer portion 33.
For example, as shown in fig. 3, the first connection parts 351 and the second connection parts 352 are symmetrically distributed along the lead 21, the first connection parts 351 and the second connection parts 352 are respectively connected with the corresponding upper-layer metal plates 23 by the first connection material, and the first connection parts 351 and the second connection parts 352 cover the corresponding upper-layer metal plates 23. The buffer-connecting portion 34 includes a flat plate portion parallel to the first connecting portion 351 and an extending portion extending perpendicularly from the flat plate portion to the first connecting portion 351 and the second connecting portion 352, and the extending portion connects the flat plate portion and the corresponding first connecting portion 351 or the second connecting portion 352.
The first positioning points 311 and the second positioning points 312 may be disposed at both ends of the buffer connecting portion 34, the two first positioning points 311 may be disposed at intervals in the first direction at both ends of the buffer connecting portion 34, and the two second positioning points 312 at the same buffer side edge 313 may be disposed at intervals at the same end of the buffer connecting portion 34.
By disposing the buffer connection portion 34 higher than the first buffer portion 32 and the second buffer portion 33, the exposed gate-level circuit can be protected from being damaged by the pressure applied to the buffer layer 30 during the process of connecting the buffer layer 30 and the chip 20.
According to an embodiment of the present invention, the semiconductor device 100 further includes a bonding connection portion 35, one end of the bonding connection portion 35 is connected to the buffer layer 30, and the other end of the bonding connection portion 35 is connected to the substrate 10.
Specifically, the substrate 10 may include a first metal layer 11, a nonmetal layer 12, and a second nonmetal layer 12 in this order from top to bottom. The nonmetal layer 12 may be made of ceramic, and the first and second metal layers 11 and 13 may be metal Cu layers provided at both sides of the nonmetal layer 12, that is, the first metal layer 11 may be overlying Cu overlying an upper side of the nonmetal layer 12, and the second metal layer 13 may be underlying Cu overlying a lower side of the nonmetal layer 12.
The first metal layer 11 may include two metal sheets arranged at intervals in the second direction, and both of the two metal sheets may be rectangular metal sheets. The chip 20 may be connected to one of the metal sheets through the second connection layer 50, and the second connection layer 50 may be made of a second connection material. One end of the bonding connection portion 35 is connected to the buffer layer 30, and the other end of the bonding connection portion 35 is connected to another metal piece.
Alternatively, the bonding connection portion 35 is made of a material with good conductivity, and the buffer layer 30 and the other metal sheet are connected to each other, so that the buffer layer 30 and the other metal sheet are electrically connected.
In an optional embodiment of the present invention, the bonding connection 35 is a metal bonding wire.
The bonding connection 35 may be a metal bonding wire, and the number of the metal bonding wires may be plural, for example, as shown in fig. 1 to 3, the bonding connection 35 is four metal bonding wires. One end of the metal bonding wire is connected to the upper surface of the buffer layer 30, and the other end is connected to the surface of the first metal layer 11 of the substrate 10, so as to achieve electrical connection between the buffer layer 30 and the first metal layer 11.
Alternatively, the metal bonding wire may be a bonding wire made of metal Cu to improve the conductivity of the bonding connection 35.
According to an embodiment of the present invention, the bonding connection portion 35 is integrally formed with the buffer layer 30.
Specifically, the buffer layer 30 may have a laminated structure connected to the upper side of the chip 20, the bonding connection portion 35 is integrally formed with the buffer layer 30, and the bonding connection portion 35 may also have a laminated structure. For example, as shown in fig. 4, taking the left side of the lead 21 as the first buffer portion 32 and the right side of the lead 21 as the second buffer portion 33, the bonding connection portion 35 extends from one end of the second buffer portion away from the buffer connection portion 34 in a direction away from the buffer connection portion 34, and is connected to the first metal layer 11 of the substrate 10.
Alternatively, as shown in fig. 4, the bonding connection part 35 may include a first connection part 351, a second connection part 352, and a third connection part 353 connected in sequence, wherein the first connection part 351 is connected to the buffer layer 30, and a level of the first connection part 351 is equal to a level of the buffer layer 30, the second connection part 352 is connected to the first connection part 351, and a level of the second connection part 352 is higher than a level of the buffer layer 30, and the third connection part 353 is connected to the second connection part 352 and the first metal layer 11, and a level of the third connection part 353 is lower than a level of the buffer layer 30. Thereby avoiding the bond connections 35 from hitting the first metal layer 11 to which the bottom of the chip 20 is connected during the connection of the buffer layer 30.
Alternatively, the third connection portion 353 may be connected to the first metal layer 11 by sintering, diffusion welding, or ultrasonic welding.
Optionally, the two metal sheets of the first metal layer 11 have the same horizontal height, the second connection portion 352 is located above the first metal layer 11 of the connection chip 20, and the distance between the second connection portion 352 and the first metal layer 11 is greater than 0.5mm or 1mm. That is, the distance between the portion of the bonding connection part 35 located above the first metal layer 11 connecting the chip 20 and the first metal layer 11 is greater than 0.5mm or 1mm to prevent the bonding connection part 35 integrally formed with the buffer layer 30 from colliding against the first metal layer 11 connected to the bottom of the chip 20 in the process of connecting the buffer layer 30.
Taking the semiconductor device 100 shown in fig. 4 as an example, the bonding connection portion 35 is integrally formed on the buffer layer 30, and the specific process of assembling the semiconductor device 100 is as follows:
predrying a layer of sintered material on the first buffer portion 32 and the second buffer portion 33 of the buffer layer 30 on the side for connection with the upper metal plate 23 of the chip 20, the sintered material forming a first connection layer 40;
the buffer layer 30 is sucked from the side of the buffer layer 30, which is not provided with the sintering material, by using the picking and placing device, the buffer layer 30 is moved, two first positioning points 311 of two triangular grooves 31 on the buffer layer 30 are aligned with the leads 21 of the gate-level circuit, so that the positioning of the buffer layer 30 in the second direction can be realized, the connecting line between the two second positioning points 312 on one triangular groove 31 of the buffer layer 30 is parallel to the chip side edge 24, and the positioning of the buffer layer 30 in the first direction can be realized by setting the distance between the connecting line and the chip side edge 24;
the positioned chip 20 and the buffer layer 30 are sent into a high-temperature furnace to finish the pressure sintering process, and then the positioning and the assembly of the buffer layer 30 can be finished;
relatively fixing the chip 20 connected with the buffer layer 30, a second connecting material for manufacturing a second connecting layer 50 and the substrate 10 by a tool from top to bottom, and realizing the connection between the bottom of the chip 20 and the substrate 10 under high-temperature equipment;
the assembly of the semiconductor device 100 is completed by electrically connecting the bonding connection 35 to the overlying Cu as the first metal layer 11 using an ultrasonic bonding process.
If the bonding connection 35 is a metal bonding wire, the metal bonding wire may be electrically connected to the upper surfaces of the overlying Cu and the buffer layer, respectively, using an ultrasonic bonding process.
Although certain specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims (10)

1. A semiconductor device, comprising:
a substrate;
the chip is arranged on the substrate, a gate-level circuit is arranged in the middle of the chip and provided with a lead extending along a first direction, and the chip is provided with at least one chip side edge extending along a second direction;
a buffer layer provided on the chip, the buffer layer electrically connecting the chip and the substrate, the buffer layer being provided with at least two first positioning points arranged at intervals along the first direction and at least two second positioning points arranged at intervals along the second direction,
the connecting line of the two first positioning points is parallel to the lead so as to position the buffer layer in the second direction, and the connecting line of the two second positioning points is parallel to the side edge so as to position the buffer layer in the first direction.
2. The semiconductor device according to claim 1, wherein the buffer layer has two buffer side edges extending along the second direction, and each of the buffer side edges has one first positioning point and two second positioning points.
3. The semiconductor device as claimed in claim 2, wherein each of the buffer side edges is provided with a positioning groove recessed toward a middle portion of the buffer layer, and the first positioning point and the second positioning point are respectively located at the positioning grooves.
4. The semiconductor device according to claim 3, wherein the positioning groove is a triangular groove, the two second positioning points are respectively a vertex of the positioning groove located on the buffer side edge, and the first positioning point is the other vertex of the positioning groove.
5. The semiconductor device according to claim 3, wherein the positioning groove is a rectangular groove, a trapezoidal groove, a tapered groove, or a profiled groove.
6. The semiconductor device according to claim 3, wherein the buffer layer comprises:
the first buffer part and the second buffer part are respectively positioned above the chip and are respectively connected with the chip, and the first buffer part and the second buffer part are positioned on two sides of the lead;
the buffer connecting part is arranged between the first buffer part and the second buffer part to connect the first buffer part and the second buffer part.
7. The semiconductor device according to claim 6, wherein the buffer connection portion is connected to a surface of one side of the first buffer portion and the second buffer portion which is away from the substrate, and a level of the buffer connection portion is higher than a level of the first buffer portion and the second buffer portion.
8. The semiconductor device according to claim 1, further comprising:
and one end of the bonding connecting part is connected with the buffer layer, and the other end of the bonding connecting part is connected with the substrate.
9. The semiconductor device according to claim 8, wherein the bonding connection is a metal bonding wire.
10. The semiconductor device according to claim 8, wherein the bonding connection portion is integrally molded with the buffer layer.
CN202221610423.1U 2022-06-23 2022-06-23 Semiconductor device with a plurality of semiconductor chips Active CN218039192U (en)

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Application Number Priority Date Filing Date Title
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