CN218006202U - RC oscillator without comparator - Google Patents

Abstract

The utility model discloses a RC oscillator without a comparator, which comprises a starting circuit, a CTAT current source, a cascode current mirror, an RC oscillating circuit, a competition risk eliminating circuit and a trimming circuit; the RC oscillating circuit is respectively connected with the starting circuit, the cascode current mirror, the trimming circuit and the competition risk elimination circuit, the starting circuit is respectively connected with the CTAT current source and the competition risk elimination circuit, and the CTAT current source is connected with the cascode current mirror; when the starting circuit receives the enabling signal en, the enabling signal enb is generated through the competition hazard eliminating circuit; when the starting circuit receives the enable signal enb, the CTAT current source is driven to work; the cascode current mirror copies the current of the CTAT current source and injects the current into the RC oscillating circuit; the trimming circuit trims the output of the RC oscillating circuit; the utility model has the advantages of voltage stability and temperature stability.

Description

RC oscillator without comparator

Technical Field

The utility model relates to a RC oscillator of no comparator belongs to oscillator technical field.

Background

The oscillator is a circuit for providing a reference clock for a sequential circuit, and along with the improvement of chip complexity and integration, high precision and low power consumption become the development direction of the oscillator, so that a novel design method is required to overcome the non-ideality of an on-chip device and keep the frequency stable under various working conditions. Compared with other types of oscillators, the RC oscillator has the characteristics of simple structure, low power consumption, low cost, low temperature coefficient and high integration level, and becomes the first choice of the on-chip integrated oscillator. However, the RC oscillator also has certain disadvantages, such as unstable frequency, influence from process deviation, and comparator delay interference and comparator misadjustment.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to overcome not enough among the prior art, provide a RC oscillator of no comparator, can solve the unsatisfactory technical problem of supply voltage stability and temperature stability of current RC oscillator.

In order to achieve the purpose, the utility model is realized by adopting the following technical scheme:

the utility model provides a comparator-free RC oscillator, which comprises a starting circuit, a CTAT current source, a cascode current mirror, an RC oscillating circuit, a competition risk eliminating circuit and a trimming circuit; the RC oscillation circuit is respectively connected with a starting circuit, a cascode current mirror, a trimming circuit and a competition hazard elimination circuit, the starting circuit is respectively connected with a CTAT current source and the competition hazard elimination circuit, and the CTAT current source is connected with the cascode current mirror;

when the starting circuit receives the enabling signal en, the enabling signal enb is generated through a competition hazard eliminating circuit; when the starting circuit receives an enabling signal enb, the starting circuit drives a CTAT current source to work; the cascode current mirror copies the current of the CTAT current source and injects the current into the RC oscillating circuit; and the trimming circuit trims the output of the RC oscillating circuit.

Optionally, the RC oscillation circuit includes a capacitor C2, a capacitor C3, an N-type MOS transistor N7, an N-type MOS transistor N8, an N-type MOS transistor N9, an N-type MOS transistor N10, a three-input nand gate nand1, a three-input nand gate nand2, an inverter inv1, an inverter inv2, an inverter inv3, an inverter inv4, an inverter inv5, an inverter inv6, an inverter inv7, and an inverter inv8;

the first, second and third input ends of the three-input NAND gate nand1 are marked as a terminal A1, a terminal B1 and a terminal C1, and the output end is marked as a terminal o1; the first, second and third input ends of the three-input nand gate nand2 are marked as a terminal A2, a terminal B2 and a terminal C2, and the output end is marked as a terminal o2;

the terminal o1 is connected to the terminal C2 and the input end of the inverter inv1 respectively, the output end of the inverter inv1 is connected to the input end of the inverter inv3, the output end of the inverter inv3 is connected to the input end of the inverter inv5, the output end of the inverter inv5 is connected to the gate of the N-type MOS transistor N8, and the drain of the N-type MOS transistor N8, one end of the capacitor C2 and the gate of the N-type MOS transistor N7 are connected and serve as the terminal CAP2; the source electrodes of the N-type MOS tube N7 and the N-type MOS tube N8 and the other end of the capacitor C2 are grounded; the drain electrode of the N-type MOS tube N7 is connected to the terminal A1;

the terminal o2 is connected to the terminal C1 and the input end of the inverter inv2 respectively, the output end of the inverter inv2 is connected to the input end of the inverter inv4, the output end of the inverter inv4 is connected to the input end of the inverter inv6, the output end of the inverter inv6 is connected to the gate of the N-type MOS transistor N9, and the drain of the N-type MOS transistor N9, one end of the capacitor C3 and the gate of the N-type MOS transistor N10 are connected and serve as the terminal CAP3; the source electrodes of the N-type MOS tube N9 and the N-type MOS tube N10 and the other end of the capacitor C3 are grounded; the drain electrode of the N-type MOS tube N10 is connected to a terminal A2;

the grid electrode of the N-type MOS tube N9 is connected to the input end of the inverter inv7, the output end of the inverter inv7 is connected to the input end of the inverter inv7, and the output end of the inverter inv7 serves as the output end of the RC oscillating circuit and is marked as CLK.

Optionally, the three-input nand gate nand1 and the three-input nand gate nand2 have the same structure and respectively include a P-type MOS transistor P23, a P-type MOS transistor P24, a P-type MOS transistor P25, an N-type MOS transistor N29, an N-type MOS transistor N30, and an N-type MOS transistor N31;

the source electrodes of the P-type MOS tube P23, the P-type MOS tube P24 and the P-type MOS tube P25 are connected to a power supply VDD; the source electrode of the N-type MOS tube N29 is connected to the drain electrode of the N-type MOS tube N30, the source electrode of the N-type MOS tube N30 is connected to the drain electrode of the N-type MOS tube N31, and the source electrode of the N-type MOS tube N31 is grounded;

the drains of the P-type MOS tube P23, the P-type MOS tube P24, the P-type MOS tube P25 and the N-type MOS tube N29 are connected and used as an output end; the grids of the P-type MOS tube P23 and the N-type MOS tube N29 are connected and used as a first input end; the grids of the P-type MOS tube P24 and the N-type MOS tube N31 are connected and used as a third input end; and the grids of the P-type MOS tube P25 and the N-type MOS tube N30 are connected and used as a second input end.

Optionally, the inverter inv1, the inverter inv2, the inverter inv3, the inverter inv4, the inverter inv5, the inverter inv6, the inverter inv7 and the inverter inv8 have the same structure, and each of the inverters includes a P-type MOS transistor P29 and an N-type MOS transistor N35;

the source electrode of the P type MOS tube P29 is connected to a power supply VDD, the grid electrodes of the P type MOS tube P29 and the N type MOS tube N35 are connected, the drain electrodes of the P type MOS tube P29 and the N type MOS tube N35 are connected, and the source electrode of the N type MOS tube N35 is grounded.

Optionally, the starting circuit includes an N-type MOS transistor N1, an N-type MOS transistor N2, an N-type MOS transistor N3, an N-type MOS transistor N4, a P-type MOS transistor P10, and a capacitor C1;

the grids of the N-type MOS tube N1, the N-type MOS tube N4 and the P-type MOS tube P10 are connected and input with an enable signal enb; the source electrodes of the N-type MOS tube N1, the N-type MOS tube N2 and the N-type MOS tube N4 are grounded; the drains of the N-type MOS tube N1, the N-type MOS tube N2 and the P-type MOS tube P10 are connected with the grid of the N-type MOS tube N3; a voltage signal VGN2 is input to the grid electrode of the N-type MOS tube N2; the drain electrode of the N-type MOS tube N3 and the source electrode of the P-type MOS tube P10 are connected to a power supply VDD; the source electrode of the N-type MOS tube N3, the drain electrode of the N-type MOS tube N4 and one end of the capacitor C1 are connected and output a voltage signal VC1, and the other end of the capacitor C1 is grounded.

Optionally, the CTAT current source includes a P-type MOS transistor P1, a P-type MOS transistor P2, a P-type MOS transistor P11, a P-type MOS transistor P12, an N-type MOS transistor N5, an N-type MOS transistor N6, a positive temperature coefficient resistor PTC1, a positive temperature coefficient resistor PTC2, a negative temperature coefficient resistor NTC1, and a negative temperature coefficient resistor NTC2;

the source electrodes of the P-type MOS tube P1 and the P-type MOS tube P2 are connected to a power supply VDD; the grid electrodes of the P-type MOS tube P1 and the P-type MOS tube P2, the drain electrode of the P-type MOS tube P12 and one end of the positive temperature coefficient resistor PTC1 are connected and output a voltage signal VPB1; the other end of the positive temperature coefficient resistor PTC1 is connected to the drain electrode of the N-type MOS tube N6 through a negative temperature coefficient resistor NTC 1; the drains of the P-type MOS tube P1 and the P-type MOS tube P2 are respectively connected to the sources of the P-type MOS tube P11 and the P-type MOS tube P12; the grids of the P-type MOS tube P11 and the P-type MOS tube P12 and the drain of the N-type MOS tube N6 are connected and output a voltage signal VPB2; the drain electrodes of the P-type MOS tube P11 and the N-type MOS tube N5 and the grid electrode of the N-type MOS tube N6 are connected and input with a voltage signal VC1; the grid electrode of the N-type MOS tube N5, the source electrode of the N-type MOS tube N6 and one end of the positive temperature coefficient resistor PTC2 are connected and output a voltage signal VGN2; the other end of the positive temperature coefficient resistor PTC2 is grounded through a negative temperature coefficient resistor NTC2, and the source electrode of the N-type MOS tube N5 is grounded.

Optionally, the cascode current mirror includes a P-type MOS transistor P3, a P-type MOS transistor P4, a P-type MOS transistor P5, a P-type MOS transistor P6, a P-type MOS transistor P7, a P-type MOS transistor P8, a P-type MOS transistor P9, a P-type MOS transistor P13, a P-type MOS transistor P14, a P-type MOS transistor P15, and a P-type MOS transistor P16;

the source electrodes of the P-type MOS tube P3, the P-type MOS tube P4, the P-type MOS tube P5, the P-type MOS tube P6, the P-type MOS tube P7, the P-type MOS tube P8 and the P-type MOS tube P9 are connected to a power supply VDD; the gates of the P-type MOS tube P3, the P-type MOS tube P6 and the P-type MOS tube P7 are connected and input with an enable signal en; the drain electrode of the P-type MOS tube P3 and the grid electrodes of the P-type MOS tube P13, the P-type MOS tube P14, the P-type MOS tube P15 and the P-type MOS tube P16 are connected and input with a voltage signal VPB2; the grids of the P-type MOS tube P4, the P-type MOS tube P5, the P-type MOS tube P8 and the P-type MOS tube P9 are connected with and input a voltage signal VPB1; the drain electrode of the P-type MOS tube P4 is connected with the source electrode of the P-type MOS tube P13; the drain electrode of the P-type MOS tube P5 is connected with the source electrode of the P-type MOS tube P14; the drain electrode of the P-type MOS tube P8 is connected with the source electrode of the P-type MOS tube P15; the drain electrode of the P-type MOS tube P9 is connected with the source electrode of the P-type MOS tube P16; the drain electrodes of the P-type MOS tube P6 and the P-type MOS tube P13 are connected with the terminal A1; the drain electrodes of the P-type MOS tube P7 and the P-type MOS tube P16 are connected with the terminal A2; the drains of the P-type MOS transistors P14 and P-type MOS transistor P15 are respectively connected to the terminal CAP2 and the terminal CAP3.

Optionally, the competition risk elimination circuit includes a P-type MOS transistor P17, a P-type MOS transistor P18, a P-type MOS transistor P19, a P-type MOS transistor P20, a P-type MOS transistor P21, a P-type MOS transistor P22, an N-type MOS transistor N23, an N-type MOS transistor N24, an N-type MOS transistor N25, an N-type MOS transistor N26, an N-type MOS transistor N27, and an N-type MOS transistor N28;

the source electrodes of the P-type MOS tube P17, the P-type MOS tube P18, the P-type MOS tube P19, the P-type MOS tube P20, the P-type MOS tube P21 and the P-type MOS tube P22 are connected to a power supply VDD; the source electrodes of the N-type MOS tube N23, the N-type MOS tube N24, the N-type MOS tube N25, the N-type MOS tube N26, the N-type MOS tube N27 and the N-type MOS tube N28 are grounded; the gates of the P-type MOS tube P17 and the N-type MOS tube N23 and the terminal B1 are connected and input with an enable signal en; the drains of the P-type MOS tube P17 and the N-type MOS tube N23 and the gates of the P-type MOS tube P18 and the N-type MOS tube N24 are connected and output an enable signal enb; the drains of the P-type MOS tube P18 and the N-type MOS tube N24 are connected with the gates of the P-type MOS tube P19 and the N-type MOS tube N25; the drains of the P-type MOS tube P19 and the N-type MOS tube N25 are connected with the gates of the P-type MOS tube P20 and the N-type MOS tube N26; the drains of the P-type MOS tube P20 and the N-type MOS tube N26 are connected with the gates of the P-type MOS tube P21 and the N-type MOS tube N27; the drains of the P-type MOS tube P21 and the N-type MOS tube N27 are connected with the gates of the P-type MOS tube P22 and the N-type MOS tube N28; the drains of the P-type MOS transistor P22 and the N-type MOS transistor N28 are connected with the terminal B2.

Optionally, the trimming circuit includes an N-type MOS transistor N11, an N-type MOS transistor N12, an N-type MOS transistor N13, an N-type MOS transistor N14, an N-type MOS transistor N15, an N-type MOS transistor N16, an N-type MOS transistor N17, an N-type MOS transistor N18, an N-type MOS transistor N19, an N-type MOS transistor N20, an N-type MOS transistor N21, an N-type MOS transistor N22, an N-type MOS transistor M32, an N-type MOS transistor M16, an N-type MOS transistor M8, an N-type MOS transistor M4, an N-type MOS transistor M2, an N-type MOS transistor M1, an N-type MOS transistor M32, an N-type MOS transistor M16, an N-type MOS transistor M8, an N-type MOS transistor M4, an N-type MOS transistor M2, and an N-type MOS transistor M1;

the drains of the N-type MOS tube N11, the N-type MOS tube N12, the N-type MOS tube N13, the N-type MOS tube N14, the N-type MOS tube N15 and the N-type MOS tube N16 are connected to a terminal CAP2; the drains of the N-type MOS transistor N17, the N-type MOS transistor N18, the N-type MOS transistor N19, the N-type MOS transistor N20, the N-type MOS transistor N21 and the N-type MOS transistor N22 are connected to a terminal CAP3;

the source electrode and the drain electrode of the N-type MOS tube M32, the N-type MOS tube M16, the N-type MOS tube M8, the N-type MOS tube M4, the N-type MOS tube M2, the N-type MOS tube M1, the N-type MOS tube M32, the N-type MOS tube M16, the N-type MOS tube M8, the N-type MOS tube M4, the N-type MOS tube M2 and the N-type MOS tube M1 are all grounded;

the source of N-type MOS transistor N11 is connected to the gate of N-type MOS transistor M32, the source of N-type MOS transistor N12 is connected to the gate of N-type MOS transistor M16, the source of N-type MOS transistor N13 is connected to the gate of N-type MOS transistor M8, the source of N-type MOS transistor N14 is connected to the gate of N-type MOS transistor M4, the source of N-type MOS transistor N15 is connected to the gate of N-type MOS transistor M2, the source of N-type MOS transistor N16 is connected to the gate of N-type MOS transistor M1, the source of N-type MOS transistor N17 is connected to the gate of N-type MOS transistor M1, the source of N-type MOS transistor N18 is connected to the gate of N-type MOS transistor M2, the source of N-type MOS transistor N19 is connected to the gate of N-type MOS transistor M4, the source of N-type MOS transistor N20 is connected to the gate of N-type MOS transistor M8, the source of N-type MOS transistor N21 is connected to the gate of N-type MOS transistor M16, and the source of N22 is connected to the gate of N32;

the external digital interface t32 of adjusting of grid of N type MOS pipe N11, N type MOS pipe N22, the external digital interface t16 of adjusting of grid of N type MOS pipe N12, N type MOS pipe N21, the external digital interface t8 of adjusting of grid of N type MOS pipe N13, N type MOS pipe N20, the external digital interface t4 of adjusting of grid of N type MOS pipe N14, N type MOS pipe N19, the external digital interface t2 of adjusting of grid of N type MOS pipe N15, N type MOS pipe N18, the external digital interface t1 of adjusting of grid of N type MOS pipe N16, N type MOS pipe N17.

Compared with the prior art, the utility model discloses the beneficial effect who reaches:

the utility model provides a RC oscillator of no comparator through improving current RC oscillator, adopts self-bias CTAT current source, and the RC oscillating circuit of Cascaded current mirror and no comparator type resists because the MOSFET threshold voltage that the temperature arouses changes through rationally adjusting CTAT electric current, has also improved temperature stability when improving mains voltage stability. Meanwhile, the comparator is eliminated, so that the size is greatly reduced.

Drawings

Fig. 1 is a schematic diagram of an RC oscillator without a comparator according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a starting circuit provided by an embodiment of the present invention;

fig. 3 is a schematic diagram of a CTAT current source provided by an embodiment of the present invention;

fig. 4 is a schematic diagram of a cascode current mirror according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a race hazard elimination circuit according to an embodiment of the present invention;

fig. 6 is a schematic diagram of an RC oscillating circuit provided by an embodiment of the present invention;

fig. 7 is a schematic diagram of a trimming circuit according to an embodiment of the present invention;

fig. 8 is a schematic diagram of a three-input nand gate according to an embodiment of the present invention;

fig. 9 is a schematic diagram of an inverter according to an embodiment of the present invention.

Detailed Description

The present invention will be further described with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.

The first embodiment is as follows:

as shown in fig. 1, the present embodiment provides a comparator-less RC oscillator, which includes a start circuit, a CTAT current source, a cascode current mirror, an RC oscillation circuit, a race hazard elimination circuit, and a trimming circuit; the RC oscillating circuit is respectively connected with the starting circuit, the cascode current mirror, the trimming circuit and the competition risk elimination circuit, the starting circuit is respectively connected with the CTAT current source and the competition risk elimination circuit, and the CTAT current source is connected with the cascode current mirror;

when the starting circuit receives the enabling signal en, the enabling signal enb is generated through the competition hazard elimination circuit; when the starting circuit receives the enable signal enb, the CTAT current source is driven to work; the cascode current mirror copies the current of the CTAT current source and injects the current into the RC oscillating circuit; the trimming circuit trims the output of the RC oscillating circuit.

As shown in fig. 2, the start-up circuit includes an N-type MOS transistor N1, an N-type MOS transistor N2, an N-type MOS transistor N3, an N-type MOS transistor N4, a P-type MOS transistor P10, and a capacitor C1;

the grid electrodes of the N-type MOS tube N1, the N-type MOS tube N4 and the P-type MOS tube P10 are connected and input with an enable signal enb; the source electrodes of the N-type MOS tube N1, the N-type MOS tube N2 and the N-type MOS tube N4 are grounded; the drains of the N-type MOS tube N1, the N-type MOS tube N2 and the P-type MOS tube P10 are connected with the grid of the N-type MOS tube N3; a voltage signal VGN2 is input to a grid electrode of the N-type MOS tube N2; the drain electrode of the N-type MOS tube N3 and the source electrode of the P-type MOS tube P10 are connected to a power supply VDD; the source electrode of the N-type MOS tube N3, the drain electrode of the N-type MOS tube N4 and one end of the capacitor C1 are connected and output a voltage signal VC1, and the other end of the capacitor C1 is grounded.

When the en signal is high, the enb signal is low, N1, N4, the grid of P10 is the low potential, make N1, N4 close, P10 conducts this moment, the power charges to the grid of N3 through P10, lead to N3 to conduct, power VDD charges to C1 through N3 this moment, produce voltage VC1 on electric capacity C1, make N6 in the CTAT current source circuit conduct, CTAT current source circuit realizes the soft start, the voltage on PTC2 in the CTAT current source circuit rises this moment, output signal is VGN2, lead to N2 to turn on, thereby make N2 drain potential reduce, N3 shuts off this moment, the starting circuit closes. At which point the entire oscillating system starts.

When the en signal is low, the enb signal is high, and P10 is off, the gate potentials of P3, P6 and P7 in the CTAT current source circuit are low, and the gates of all the tubes as cascode current mirrors are biased at high potential, thereby turning off the cascode current mirrors. At which time the entire oscillating system is shut down.

As shown in fig. 3, the CTAT current source includes a P-type MOS transistor P1, a P-type MOS transistor P2, a P-type MOS transistor P11, a P-type MOS transistor P12, an N-type MOS transistor N5, an N-type MOS transistor N6, a positive temperature coefficient resistor PTC1, a positive temperature coefficient resistor PTC2, a negative temperature coefficient resistor NTC1, and a negative temperature coefficient resistor NTC2;

the source electrodes of the P-type MOS tube P1 and the P-type MOS tube P2 are connected to a power supply VDD; the grid electrodes of the P-type MOS tube P1 and the P-type MOS tube P2, the drain electrode of the P-type MOS tube P12 and one end of the positive temperature coefficient resistor PTC1 are connected and output a voltage signal VPB1; the other end of the positive temperature coefficient resistor PTC1 is connected to the drain electrode of the N-type MOS tube N6 through a negative temperature coefficient resistor NTC 1; the drains of the P-type MOS tube P1 and the P-type MOS tube P2 are respectively connected to the sources of the P-type MOS tube P11 and the P-type MOS tube P12; the grid electrodes of the P-type MOS tube P11 and the P-type MOS tube P12 and the drain electrode of the N-type MOS tube N6 are connected and output a voltage signal VPB2; the drains of the P type MOS tube P11 and the N type MOS tube N5 and the grid of the N type MOS tube N6 are connected and input with a voltage signal VC1; the grid electrode of the N-type MOS tube N5, the source electrode of the N-type MOS tube N6 and one end of the positive temperature coefficient resistor PTC2 are connected and output a voltage signal VGN2; the other end of the positive temperature coefficient resistor PTC2 is grounded through a negative temperature coefficient resistor NTC2, and the source electrode of the N-type MOS tube N5 is grounded.

The PTC1, the NTC1, the P2 and the P12 form a self-bias structure for providing bias voltages VPB1 and VPB2 for all cascode structures, and the PTC1+ NTC1 has a zero temperature coefficient by reasonably adjusting the resistance ratio of the PTC1 and the NTC1, so that the variation of the VPB1 and the VPB2 in the whole temperature range is reduced to the greatest extent. The current of the CTAT current source is the gate-source voltage Vgs passing through N5 _N5 And is formed by superposition on the resistors PTC2 and PTC 2. Since the threshold voltage of the MOSFET has a negative temperature coefficient, a current with a negative temperature needs to be generated to offset its change, and the PTC2+ NTC2 has an adjustable positive temperature coefficient by adjusting the proportional relationship between PTC2 and PTC 2. The current I of the CTAT current source is:

as shown in fig. 4, the cascode current mirror includes a P-type MOS transistor P3, a P-type MOS transistor P4, a P-type MOS transistor P5, a P-type MOS transistor P6, a P-type MOS transistor P7, a P-type MOS transistor P8, a P-type MOS transistor P9, a P-type MOS transistor P13, a P-type MOS transistor P14, a P-type MOS transistor P15, and a P-type MOS transistor P16; the P-type MOS transistor P3, the P-type MOS transistor P6 and the P-type MOS transistor P7 are used as switches;

the source electrodes of the P-type MOS tube P3, the P-type MOS tube P4, the P-type MOS tube P5, the P-type MOS tube P6, the P-type MOS tube P7, the P-type MOS tube P8 and the P-type MOS tube P9 are connected to a power supply VDD; the grids of the P-type MOS tube P3, the P-type MOS tube P6 and the P-type MOS tube P7 are connected and input with an enable signal en; the drain electrode of the P-type MOS tube P3 and the grid electrodes of the P-type MOS tube P13, the P-type MOS tube P14, the P-type MOS tube P15 and the P-type MOS tube P16 are connected and input with a voltage signal VPB2; the grid electrodes of the P-type MOS tube P4, the P-type MOS tube P5, the P-type MOS tube P8 and the P-type MOS tube P9 are connected with and input a voltage signal VPB1; the drain electrode of the P-type MOS tube P4 is connected with the source electrode of the P-type MOS tube P13; the drain electrode of the P-type MOS tube P5 is connected with the source electrode of the P-type MOS tube P14; the drain electrode of the P type MOS tube P8 is connected with the source electrode of the P type MOS tube P15; the drain electrode of the P-type MOS tube P9 is connected with the source electrode of the P-type MOS tube P16; the drains of the P-type MOS transistor P6 and the P-type MOS transistor P13 are connected with the terminal A1; the drain electrodes of the P-type MOS tube P7 and the P-type MOS tube P16 are connected with the terminal A2; the drains of the P-type MOS transistors P14 and P-type MOS transistor P15 are connected to the terminal CAP2 and the terminal CAP3, respectively.

Since the cascode structure has high output impedance, it is ideal to be used as a cascode current mirror, and the current on each cascode current mirror branch is almost constant when the power supply voltage changes. The voltage stability is greatly improved.

As shown in fig. 5, the competition adventure elimination circuit includes a P-type MOS transistor P17, a P-type MOS transistor P18, a P-type MOS transistor P19, a P-type MOS transistor P20, a P-type MOS transistor P21, a P-type MOS transistor P22, an N-type MOS transistor N23, an N-type MOS transistor N24, an N-type MOS transistor N25, an N-type MOS transistor N26, an N-type MOS transistor N27, and an N-type MOS transistor N28;

the source electrodes of the P-type MOS tube P17, the P-type MOS tube P18, the P-type MOS tube P19, the P-type MOS tube P20, the P-type MOS tube P21 and the P-type MOS tube P22 are connected to a power supply VDD; the source electrodes of the N-type MOS tube N23, the N-type MOS tube N24, the N-type MOS tube N25, the N-type MOS tube N26, the N-type MOS tube N27 and the N-type MOS tube N28 are grounded; the gates of the P-type MOS tube P17 and the N-type MOS tube N23 and the terminal B1 are connected and input with an enable signal en; the drains of the P-type MOS tube P17 and the N-type MOS tube N23 and the gates of the P-type MOS tube P18 and the N-type MOS tube N24 are connected and output an enable signal enb; the drains of the P type MOS tube P18 and the N type MOS tube N24 are connected with the grids of the P type MOS tube P19 and the N type MOS tube N25; the drains of the P-type MOS tube P19 and the N-type MOS tube N25 are connected with the gates of the P-type MOS tube P20 and the N-type MOS tube N26; the drains of the P-type MOS tube P20 and the N-type MOS tube N26 are connected with the gates of the P-type MOS tube P21 and the N-type MOS tube N27; the drains of the P-type MOS tube P21 and the N-type MOS tube N27 are connected with the gates of the P-type MOS tube P22 and the N-type MOS tube N28; the drains of the P-type MOS transistor P22 and the N-type MOS transistor N28 are connected to the terminal B2.

For digital circuits, the output waveform can malfunction due to switching delays caused by the non-ideal characteristics of the gate. In this circuit, by using an even number of inverters, the input signal is appropriately delayed without changing the polarity of the input signal, so that the output produces the correct signal. It can be seen from the structure of the oscillator that it is a left-right complementary structure, so the mode of operation is reversed. When the circuit is started, the ends A1 and B1 of the three-input NAND gate nand1 are high potential, the output of the three-input NAND gate nand1 is determined by the potential at the position C1, due to the delay action caused by a competition hazard eliminating circuit formed by an inverter chain, when the circuit is just powered on, en is 1, but the output end B2 of the competition hazard eliminating circuit is 0 due to the existence of delay, the output of the three-input NAND gate nand2 is 1, namely the input end C1 of nand1 is 1, and the output of nand1 is 1, the competition hazard eliminating circuit delays an enable signal en, so that the two output ends of an RS trigger formed by nand1 and nand2 at the same time are ensured to have normal output without misoperation.

As shown in figure 6 of the drawings, the RC oscillation circuit comprises a capacitor C2, a capacitor C3, an N-type MOS tube N7, an N-type MOS tube N8, an N-type MOS tube N9, an N-type MOS tube N10, a three-input NAND gate nand gate 2, an inverter inv1, an inverter inv2, an inverter inv3, an inverter inv4, an inverter inv5, an inverter inv6, an inverter inv7 and an inverter inv8;

the first, second and third input ends of the three-input NAND gate nand1 are marked as a terminal A1, a terminal B1 and a terminal C1, and the output end is marked as a terminal o1; the first, second and third input ends of the three-input nand gate nand2 are marked as a terminal A2, a terminal B2 and a terminal C2, and the output end is marked as a terminal o2;

the terminal o1 is connected to the terminal C2 and the input end of the inverter inv1 respectively, the output end of the inverter inv1 is connected to the input end of the inverter inv3, the output end of the inverter inv3 is connected to the input end of the inverter inv5, the output end of the inverter inv5 is connected to the gate of the N-type MOS transistor N8, and the drain of the N-type MOS transistor N8, one end of the capacitor C2 and the gate of the N-type MOS transistor N7 are connected and serve as a terminal CAP2; the source electrodes of the N-type MOS tube N7 and the N-type MOS tube N8 and the other end of the capacitor C2 are grounded; the drain electrode of the N-type MOS tube N7 is connected to the terminal A1;

the terminal o2 is connected to the terminal C1 and the input end of the inverter inv2 respectively, the output end of the inverter inv2 is connected to the input end of the inverter inv4, the output end of the inverter inv4 is connected to the input end of the inverter inv6, the output end of the inverter inv6 is connected to the gate of the N-type MOS transistor N9, the drain of the N-type MOS transistor N9, one end of the capacitor C3 and the gate of the N-type MOS transistor N10 are connected and serve as the terminal CAP3; the source electrodes of the N-type MOS tube N9 and the N-type MOS tube N10 and the other end of the capacitor C3 are grounded; the drain electrode of the N-type MOS tube N10 is connected to the terminal A2;

the grid electrode of the N-type MOS tube N9 is connected to the input end of the inverter inv7, the output end of the inverter inv7 is connected to the input end of the inverter inv7, and the output end of the inverter inv7 serves as the output end of the RC oscillating circuit and is marked as CLK.

When the output of the terminal o1 of the three-input nand gate nand2 is 1, the output signal enables the grid voltage of the N-type MOS transistor N9 to be low through the inverter inv2, the inverter inv4 and the inverter inv6, the capacitor C3 is charged through the terminal CPA3, and the threshold voltage Vth of the N-type MOS transistor N10 is charged _N10 The drain voltage of the N-type MOS transistor N10 is lowered, and at this time, the input state of the RS flip-flop formed by the three-input nand gates nand1 and nand2 changes, which causes the output of the RS flip-flop to be inverted, the gate voltage of the N-type MOS transistor N9 is high level, and the capacitor C3 discharges through the N-type MOS transistor N9.

Because the left circuit works in the opposite mode, the left signal can make the grid voltage of the N-type MOS tube N9 return to the low level through the RS trigger again, and the operation is repeated in a circulating mode. The charging and discharging of the capacitor C3 are converted into a switching signal controlled by the output of the inverter inv6, and the control part is an RS trigger consisting of three-input NAND gates nand1 and nand 2. The charging and discharging time of the capacitor C3 determines the magnitude of the frequency.

Affecting the period of the oscillator waveform are: vgs _N5 Current formed with resistors NTC2 and PTC2, drain voltage Vth _N7 、Vth _N10 And capacitors C2, C3. Ideally, the parameters and current of the MOSFET are fixed, so only the resistors NTC2 and PTC2, C3 affect the output waveform. However, in practice, the resistances of the resistors NTC2 and PTC2 may vary with temperature, and the voltage may also affect the leakage current of the MOSFET, thereby causing the charging current I to vary with temperature and voltage, and the threshold voltage "Vth" of the MOSFET to also vary with temperature fluctuation. But the temperature stability of the oscillator can be improved by reasonably adjusting the variation of the current I relative to the Vth along with the temperature, so that the variation of the current I and the Vth along with the temperature can be counteracted to the greatest extent.

As shown in fig. 7, the trimming circuit includes an N-type MOS transistor N11, an N-type MOS transistor N12, an N-type MOS transistor N13, an N-type MOS transistor N14, an N-type MOS transistor N15, an N-type MOS transistor N16, an N-type MOS transistor N17, an N-type MOS transistor N18, an N-type MOS transistor N19, an N-type MOS transistor N20, an N-type MOS transistor N21, an N-type MOS transistor N22, an N-type MOS transistor M32, an N-type MOS transistor M16, an N-type MOS transistor M8, an N-type MOS transistor M4, an N-type MOS transistor M2, an N-type MOS transistor M1, an N-type MOS transistor M32, an N-type MOS transistor M16, an N-type MOS transistor M8, an N-type MOS transistor M4, an N-type MOS transistor M2, and an N-type MOS transistor M1;

the drains of the N-type MOS tube N11, the N-type MOS tube N12, the N-type MOS tube N13, the N-type MOS tube N14, the N-type MOS tube N15 and the N-type MOS tube N16 are connected to the terminal CAP2; the drains of the N-type MOS transistors N17, N-type MOS transistors N18, N-type MOS transistors N19, N-type MOS transistors N20, N-type MOS transistors N21, and N-type MOS transistors N22 are connected to the terminal CAP3;

the source electrode and the drain electrode of the N-type MOS tube M32, the N-type MOS tube M16, the N-type MOS tube M8, the N-type MOS tube M4, the N-type MOS tube M2, the N-type MOS tube M1, the N-type MOS tube M32, the N-type MOS tube M16, the N-type MOS tube M8, the N-type MOS tube M4, the N-type MOS tube M2 and the N-type MOS tube M1 are all grounded;

a source electrode of an N-type MOS transistor N11 is connected to a gate electrode of an N-type MOS transistor M32, a source electrode of an N-type MOS transistor N12 is connected to a gate electrode of an N-type MOS transistor M16, a source electrode of an N-type MOS transistor N13 is connected to a gate electrode of an N-type MOS transistor M8, a source electrode of an N-type MOS transistor N14 is connected to a gate electrode of an N-type MOS transistor M4, a source electrode of an N-type MOS transistor N15 is connected to a gate electrode of an N-type MOS transistor M2, a source electrode of an N-type MOS transistor N16 is connected to a gate electrode of an N-type MOS transistor M1, a source electrode of an N-type MOS transistor N17 is connected to a gate electrode of an N-type MOS transistor M1, a source electrode of an N-type MOS transistor N18 is connected to a gate electrode of an N-type MOS transistor M2, a source electrode of an N-type MOS transistor N19 is connected to a gate electrode of an N-type MOS transistor M4, a source electrode of an N20 is connected to a gate electrode of an N-type MOS transistor M8, a source electrode of an N21 is connected to a gate electrode of an N-type MOS transistor M16, and a source electrode of an N-type MOS transistor N22 is connected to a gate electrode of an N-type MOS transistor M32;

the gates of the N-type MOS transistors N11 and N-type MOS transistors N22 are externally connected with a digital adjusting and repairing interface t32, the gates of the N-type MOS transistors N12 and N-type MOS transistors N21 are externally connected with a digital adjusting and repairing interface t16, the gates of the N-type MOS transistors N13 and N-type MOS transistors N20 are externally connected with a digital adjusting and repairing interface t8, the gates of the N-type MOS transistors N14 and N-type MOS transistors N19 are externally connected with a digital adjusting and repairing interface t4, the gates of the N-type MOS transistors N15 and N-type MOS transistors N18 are externally connected with a digital adjusting and repairing interface t2, and the gates of the N-type MOS transistors N16 and N17 are externally connected with a digital adjusting and repairing interface t1.

The digital adjusting interface is used for controlling the size of the capacitors connected in parallel on the C2 and the C3, so that the size of the charging and discharging capacitors of the oscillator is changed, and the output frequency is adjusted.

As shown in fig. 8, the three-input nand gate nand1 and the three-input nand gate nand2 have the same structure, and the three-input nand gate nand1 is taken as an example and includes a P-type MOS transistor P23, a P-type MOS transistor P24, a P-type MOS transistor P25, an N-type MOS transistor N29, an N-type MOS transistor N30, and an N-type MOS transistor N31;

the source electrodes of the P-type MOS tube P23, the P-type MOS tube P24 and the P-type MOS tube P25 are connected to a power supply VDD; the source electrode of the N-type MOS tube N29 is connected to the drain electrode of the N-type MOS tube N30, the source electrode of the N-type MOS tube N30 is connected to the drain electrode of the N-type MOS tube N31, and the source electrode of the N-type MOS tube N31 is grounded;

the drains of the P-type MOS tube P23, the P-type MOS tube P24, the P-type MOS tube P25 and the N-type MOS tube N29 are connected and used as an output end; the grids of the P-type MOS tube P23 and the N-type MOS tube N29 are connected and used as a first input end; the grids of the P24 MOS tube and the N31 MOS tube are connected and used as a third input end; and the grids of the P-type MOS tube P25 and the N-type MOS tube N30 are connected and used as second input ends.

As shown in fig. 9, the inverter inv1, the inverter inv2, the inverter inv3, the inverter inv4, the inverter inv5, the inverter inv6, the inverter inv7 and the inverter inv8 have the same structure, and each of the inverters includes a P-type MOS transistor P29 and an N-type MOS transistor N35;

the source electrode of the P-type MOS tube P29 is connected to a power supply VDD, the grid electrodes of the P-type MOS tube P29 and the N-type MOS tube N35 are connected, the drain electrodes of the P-type MOS tube P29 and the N-type MOS tube N35 are connected, and the source electrode of the N-type MOS tube N35 is grounded.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be considered as the protection scope of the present invention.

Claims (9)

1. A comparator-free RC oscillator is characterized by comprising a starting circuit, a CTAT current source, a cascode current mirror, an RC oscillating circuit, a competition hazard eliminating circuit and a trimming circuit; the RC oscillation circuit is respectively connected with a starting circuit, a cascode current mirror, a trimming circuit and a competition hazard elimination circuit, the starting circuit is respectively connected with a CTAT current source and the competition hazard elimination circuit, and the CTAT current source is connected with the cascode current mirror;

when the starting circuit receives the enabling signal en, the enabling signal enb is generated through a competition hazard eliminating circuit; when the starting circuit receives an enabling signal enb, the starting circuit drives a CTAT current source to work; the cascode current mirror copies the current of the CTAT current source and injects the current into the RC oscillating circuit; and the trimming circuit is used for trimming the output of the RC oscillating circuit.

2. The comparator-free RC oscillator according to claim 1, wherein the RC oscillator circuit comprises a capacitor C2, a capacitor C3, an N-type MOS transistor N7, an N-type MOS transistor N8, an N-type MOS transistor N9, an N-type MOS transistor N10, a three-input NAND gate nand1, a three-input NAND gate nand2, an inverter inv1, an inverter inv2, an inverter inv3, an inverter inv4, an inverter inv5, an inverter inv6, an inverter inv7, and an inverter inv8;

the first, second and third input ends of the three-input NAND gate nand1 are marked as a terminal A1, a terminal B1 and a terminal C1, and the output end is marked as a terminal o1; the first, second and third input ends of the three-input nand gate nand2 are marked as a terminal A2, a terminal B2 and a terminal C2, and the output end is marked as a terminal o2;

the terminal o1 is connected to the terminal C2 and the input end of the inverter inv1 respectively, the output end of the inverter inv1 is connected to the input end of the inverter inv3, the output end of the inverter inv3 is connected to the input end of the inverter inv5, the output end of the inverter inv5 is connected to the gate of the N-type MOS transistor N8, and the drain of the N-type MOS transistor N8, one end of the capacitor C2 and the gate of the N-type MOS transistor N7 are connected and serve as the terminal CAP2; the source electrodes of the N-type MOS tube N7 and the N-type MOS tube N8 and the other end of the capacitor C2 are grounded; the drain electrode of the N-type MOS tube N7 is connected to the terminal A1;

the terminal o2 is respectively connected to the terminal C1 and the input end of the inverter inv2, the output end of the inverter inv2 is connected to the input end of the inverter inv4, the output end of the inverter inv4 is connected to the input end of the inverter inv6, the output end of the inverter inv6 is connected to the gate of the N-type MOS transistor N9, and the drain of the N-type MOS transistor N9, one end of the capacitor C3 and the gate of the N-type MOS transistor N10 are connected and serve as the terminal CAP3; the source electrodes of the N-type MOS tube N9 and the N-type MOS tube N10 and the other end of the capacitor C3 are grounded; the drain electrode of the N-type MOS tube N10 is connected to a terminal A2;

the grid electrode of the N-type MOS tube N9 is connected to the input end of the inverter inv7, the output end of the inverter inv7 is connected to the input end of the inverter inv7, and the output end of the inverter inv7 serves as the output end of the RC oscillating circuit and is marked as CLK.

3. The comparator-less RC oscillator according to claim 2, wherein the three-input NAND gate nand1 and the three-input NAND gate nand2 have the same structure, and each of the three-input NAND gate nand2 comprises a P-type MOS transistor P23, a P-type MOS transistor P24, a P-type MOS transistor P25, an N-type MOS transistor N29, an N-type MOS transistor N30 and an N-type MOS transistor N31;

the source electrodes of the P-type MOS tube P23, the P-type MOS tube P24 and the P-type MOS tube P25 are connected to a power supply VDD; the source electrode of the N-type MOS tube N29 is connected to the drain electrode of the N-type MOS tube N30, the source electrode of the N-type MOS tube N30 is connected to the drain electrode of the N-type MOS tube N31, and the source electrode of the N-type MOS tube N31 is grounded;

the drains of the P-type MOS tube P23, the P-type MOS tube P24, the P-type MOS tube P25 and the N-type MOS tube N29 are connected and used as an output end; the grids of the P-type MOS tube P23 and the N-type MOS tube N29 are connected and used as a first input end; the grids of the P-type MOS tube P24 and the N-type MOS tube N31 are connected and used as a third input end; and the grids of the P-type MOS tube P25 and the N-type MOS tube N30 are connected and used as a second input end.

4. The comparator-free RC oscillator according to claim 2, wherein the inverter inv1, the inverter inv2, the inverter inv3, the inverter inv4, the inverter inv5, the inverter inv6, the inverter inv7 and the inverter inv8 have the same structure, and each of the inverters comprises a P-type MOS transistor P29 and an N-type MOS transistor N35;

the source electrode of the P-type MOS tube P29 is connected to a power supply VDD, the grid electrodes of the P-type MOS tube P29 and the N-type MOS tube N35 are connected, the drain electrodes of the P-type MOS tube P29 and the N-type MOS tube N35 are connected, and the source electrode of the N-type MOS tube N35 is grounded.

5. The comparator-less RC oscillator of claim 2, wherein the start-up circuit comprises N-type MOS transistor N1, N-type MOS transistor N2, N-type MOS transistor N3, N-type MOS transistor N4, P-type MOS transistor P10, and capacitor C1;

the gates of the N-type MOS tube N1, the N-type MOS tube N4 and the P-type MOS tube P10 are connected and input with an enable signal enb; the source electrodes of the N-type MOS tube N1, the N-type MOS tube N2 and the N-type MOS tube N4 are grounded; the drains of the N-type MOS tube N1, the N-type MOS tube N2 and the P-type MOS tube P10 are connected with the grid of the N-type MOS tube N3; a voltage signal VGN2 is input to the grid electrode of the N-type MOS tube N2; the drain electrode of the N-type MOS tube N3 and the source electrode of the P-type MOS tube P10 are connected to a power supply VDD; the source electrode of the N-type MOS tube N3, the drain electrode of the N-type MOS tube N4 and one end of the capacitor C1 are connected and output a voltage signal VC1, and the other end of the capacitor C1 is grounded.

6. The comparator-less RC oscillator of claim 5, wherein the CTAT current source comprises a P-type MOS transistor P1, a P-type MOS transistor P2, a P-type MOS transistor P11, a P-type MOS transistor P12, an N-type MOS transistor N5, an N-type MOS transistor N6, a positive temperature coefficient resistor PTC1, a positive temperature coefficient resistor PTC2, a negative temperature coefficient resistor NTC1, and a negative temperature coefficient resistor NTC2;

the source electrodes of the P-type MOS tube P1 and the P-type MOS tube P2 are connected to a power supply VDD; the grid electrodes of the P-type MOS tube P1 and the P-type MOS tube P2, the drain electrode of the P-type MOS tube P12 and one end of the positive temperature coefficient resistor PTC1 are connected and output a voltage signal VPB1; the other end of the positive temperature coefficient resistor PTC1 is connected to the drain electrode of the N-type MOS tube N6 through a negative temperature coefficient resistor NTC 1; the drain electrodes of the P-type MOS tube P1 and the P-type MOS tube P2 are respectively connected to the source electrodes of the P-type MOS tube P11 and the P-type MOS tube P12; the grids of the P-type MOS tube P11 and the P-type MOS tube P12 and the drain of the N-type MOS tube N6 are connected and output a voltage signal VPB2; the drain electrodes of the P-type MOS tube P11 and the N-type MOS tube N5 and the grid electrode of the N-type MOS tube N6 are connected and input with a voltage signal VC1; the grid electrode of the N-type MOS tube N5, the source electrode of the N-type MOS tube N6 and one end of the positive temperature coefficient resistor PTC2 are connected and output a voltage signal VGN2; the other end of the positive temperature coefficient resistor PTC2 is grounded through a negative temperature coefficient resistor NTC2, and the source electrode of the N-type MOS tube N5 is grounded.

7. The comparator-less RC oscillator of claim 6, wherein the cascode current mirror comprises a P-type MOS transistor P3, a P-type MOS transistor P4, a P-type MOS transistor P5, a P-type MOS transistor P6, a P-type MOS transistor P7, a P-type MOS transistor P8, a P-type MOS transistor P9, a P-type MOS transistor P13, a P-type MOS transistor P14, a P-type MOS transistor P15, a P-type MOS transistor P16;

the source electrodes of the P-type MOS tube P3, the P-type MOS tube P4, the P-type MOS tube P5, the P-type MOS tube P6, the P-type MOS tube P7, the P-type MOS tube P8 and the P-type MOS tube P9 are connected to a power supply VDD; the gates of the P-type MOS tube P3, the P-type MOS tube P6 and the P-type MOS tube P7 are connected and input with an enable signal en; the drain electrode of the P-type MOS tube P3 and the grid electrodes of the P-type MOS tube P13, the P-type MOS tube P14, the P-type MOS tube P15 and the P-type MOS tube P16 are connected and input with a voltage signal VPB2; the grid electrodes of the P-type MOS tube P4, the P-type MOS tube P5, the P-type MOS tube P8 and the P-type MOS tube P9 are connected with and input a voltage signal VPB1; the drain electrode of the P-type MOS tube P4 is connected with the source electrode of the P-type MOS tube P13; the drain electrode of the P-type MOS tube P5 is connected with the source electrode of the P-type MOS tube P14; the drain electrode of the P-type MOS tube P8 is connected with the source electrode of the P-type MOS tube P15; the drain electrode of the P-type MOS tube P9 is connected with the source electrode of the P-type MOS tube P16; the drains of the P-type MOS tube P6 and the P-type MOS tube P13 are connected with the terminal A1; the drain electrodes of the P-type MOS tube P7 and the P-type MOS tube P16 are connected with the terminal A2; the drains of the P-type MOS transistors P14 and P-type MOS transistor P15 are connected to the terminal CAP2 and the terminal CAP3, respectively.

8. The comparator-less RC oscillator according to claim 7, wherein the race hazard elimination circuit comprises a P-type MOS transistor P17, a P-type MOS transistor P18, a P-type MOS transistor P19, a P-type MOS transistor P20, a P-type MOS transistor P21, a P-type MOS transistor P22, an N-type MOS transistor N23, an N-type MOS transistor N24, an N-type MOS transistor N25, an N-type MOS transistor N26, an N-type MOS transistor N27, and an N-type MOS transistor N28;

the source electrodes of the P-type MOS tube P17, the P-type MOS tube P18, the P-type MOS tube P19, the P-type MOS tube P20, the P-type MOS tube P21 and the P-type MOS tube P22 are connected to a power supply VDD; the source electrodes of the N-type MOS tube N23, the N-type MOS tube N24, the N-type MOS tube N25, the N-type MOS tube N26, the N-type MOS tube N27 and the N-type MOS tube N28 are grounded; the gates of the P-type MOS tube P17 and the N-type MOS tube N23 and the terminal B1 are connected and input with an enable signal en; the drains of the P-type MOS tube P17 and the N-type MOS tube N23 and the gates of the P-type MOS tube P18 and the N-type MOS tube N24 are connected and output an enable signal enb; the drains of the P-type MOS tube P18 and the N-type MOS tube N24 are connected with the gates of the P-type MOS tube P19 and the N-type MOS tube N25; the drain electrodes of the P-type MOS tube P19 and the N-type MOS tube N25 are connected with the grid electrodes of the P-type MOS tube P20 and the N-type MOS tube N26; the drains of the P-type MOS tube P20 and the N-type MOS tube N26 are connected with the gates of the P-type MOS tube P21 and the N-type MOS tube N27; the drains of the P-type MOS tube P21 and the N-type MOS tube N27 are connected with the gates of the P-type MOS tube P22 and the N-type MOS tube N28; the drains of the P-type MOS transistor P22 and the N-type MOS transistor N28 are connected with the terminal B2.

9. The comparator-less RC oscillator according to claim 8, wherein the trimming circuit comprises an N-type MOS transistor N11, an N-type MOS transistor N12, an N-type MOS transistor N13, an N-type MOS transistor N14, an N-type MOS transistor N15, an N-type MOS transistor N16, an N-type MOS transistor N17, an N-type MOS transistor N18, an N-type MOS transistor N19, an N-type MOS transistor N20, an N-type MOS transistor N21, an N-type MOS transistor N22, an N-type MOS transistor M32, an N-type MOS transistor M16, an N-type MOS transistor M8, an N-type MOS transistor M4, an N-type MOS transistor M2, an N-type MOS transistor M1, an N-type MOS transistor M32, an N-type MOS transistor M16, an N-type MOS transistor M8, an N-type MOS transistor M4, an N-type MOS transistor M2, and an N-type MOS transistor M1;

the drains of the N-type MOS tube N11, the N-type MOS tube N12, the N-type MOS tube N13, the N-type MOS tube N14, the N-type MOS tube N15 and the N-type MOS tube N16 are connected to a terminal CAP2; the drains of the N-type MOS transistor N17, the N-type MOS transistor N18, the N-type MOS transistor N19, the N-type MOS transistor N20, the N-type MOS transistor N21 and the N-type MOS transistor N22 are connected to a terminal CAP3;

the source electrode and the drain electrode of the N-type MOS tube M32, the N-type MOS tube M16, the N-type MOS tube M8, the N-type MOS tube M4, the N-type MOS tube M2, the N-type MOS tube M1, the N-type MOS tube M32, the N-type MOS tube M16, the N-type MOS tube M8, the N-type MOS tube M4, the N-type MOS tube M2 and the N-type MOS tube M1 are all grounded;

the source of the N-type MOS transistor N11 is connected to the gate of the N-type MOS transistor M32, the source of the N-type MOS transistor N12 is connected to the gate of the N-type MOS transistor M16, the source of the N-type MOS transistor N13 is connected to the gate of the N-type MOS transistor M8, the source of the N-type MOS transistor N14 is connected to the gate of the N-type MOS transistor M4, the source of the N-type MOS transistor N15 is connected to the gate of the N-type MOS transistor M2, the source of the N-type MOS transistor N16 is connected to the gate of the N-type MOS transistor M1, the source of the N-type MOS transistor N17 is connected to the gate of the N-type MOS transistor M1, the source of the N-type MOS transistor N18 is connected to the gate of the N-type MOS transistor M2, the source of the N-type MOS transistor N19 is connected to the gate of the N-type MOS transistor M4, the source of the N-type MOS transistor N20 is connected to the gate of the N-type MOS transistor M8, the source of the N-type MOS transistor N21 is connected to the gate of the N-type MOS transistor M16, and the source of the N22 is connected to the gate of the N32;

the external digital interface t32 of transferring of grid of N type MOS pipe N11, N type MOS pipe N22, the external digital interface t16 of transferring of grid of N type MOS pipe N12, N type MOS pipe N21, the external digital interface t8 of transferring of grid of N type MOS pipe N13, N type MOS pipe N20, the external digital interface t4 of transferring of grid of N type MOS pipe N14, N type MOS pipe N19, the external digital interface t2 of transferring of grid of N type MOS pipe N15, N type MOS pipe N18, the external digital interface t1 of transferring of grid of N type MOS pipe N16, N type MOS pipe N17.

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