CN217935090U - Dual drive circuit - Google Patents
Dual drive circuit Download PDFInfo
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- CN217935090U CN217935090U CN202221710450.6U CN202221710450U CN217935090U CN 217935090 U CN217935090 U CN 217935090U CN 202221710450 U CN202221710450 U CN 202221710450U CN 217935090 U CN217935090 U CN 217935090U
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Abstract
The present application relates to a dual drive circuit. Outputting a first voltage domain signal through a first end or a second end of the driving unit, converting the first voltage domain signal into a second voltage domain signal through a voltage conversion unit connected with the first end, and transmitting the second voltage domain signal to a target circuit, thereby realizing the output of the second voltage domain signal; or the first voltage domain signal is directly transmitted to the target circuit through the second end, so that the output of the first voltage domain signal is realized, and the output of multi-voltage range signals can be realized by selecting different ports of the driving unit for output.
Description
Technical Field
The application relates to the technical field of electronic driving, in particular to a dual-drive circuit.
Background
The universal programmer is a device for programming common chips such as MCU, CPLD, EEPROM, FLASH and NVRAM, and the programming of the chip is realized by connecting the external interface of the universal programmer with each signal pin and power supply pin of the chip. Usually, a Field Programmable Gate Array (FPGA) is used to provide an IO driver to program an external chip, and the voltage of an IO port of the FPGA is determined by the VCCIO voltage of the BANK where the IO port is located, so the voltage of the IO port is limited by the VCCIO voltage of the FPGA, but the chip can be programmed only when the voltage of the IO port of the FPGA is consistent with the voltage allowed by the chip to be programmed, otherwise, the chip to be programmed cannot effectively receive a signal output by the FPGA, and may even be damaged.
The existing IO driving circuit mainly has two modes for adjusting the IO voltage, one mode is that the voltage of the IO port is adjusted by changing the VCCIO voltage of the BANK where the IO port of the FPGA is located, so that the voltage of the IO port is matched with the chip to be programmed; and the other is to realize the matching of the IO voltage and the chip to be programmed by adding a bidirectional voltage conversion chip at the rear end of the FPGA. However, both of these two methods can only achieve output in one voltage range, and cannot be applied to a scenario with multiple voltage range requirements.
SUMMERY OF THE UTILITY MODEL
The application provides a can be suitable for two drive circuit of many voltage range demands.
A dual drive circuit comprising:
a drive unit including a first end and a second end;
the input end of the voltage conversion unit is connected with the first end, and the output end of the voltage conversion unit is connected with the second end and is connected with a target circuit;
the drive unit is configured to:
outputting a first voltage domain signal to the target circuit; or
Outputting the first voltage domain signal to the voltage conversion unit so as to convert the first voltage domain signal into a second voltage domain signal when the voltage conversion unit is in a working state, and transmitting the second voltage domain signal to the target circuit;
wherein a voltage of the second voltage domain signal is greater than a voltage of the first voltage domain signal.
In one embodiment, the dual driving circuit further includes:
and a first overvoltage protection unit, a first connection end of the first overvoltage protection unit is connected with the output end, a second connection end of the first overvoltage protection unit is connected with the second end in common and is connected with the target circuit, and the first overvoltage protection unit is used for clamping the voltage output by the target circuit to the voltage conversion unit within a first voltage threshold.
In one embodiment, the dual driving circuit further includes:
the first overvoltage protection unit is used for controlling the first overvoltage protection unit to disconnect a conductive path between the voltage conversion unit and the target circuit if the current flowing to the voltage conversion unit from the first overvoltage protection unit exceeds a first current threshold value.
In one embodiment, the dual driving circuit further includes:
and the anode of the first diode is respectively connected with the first overvoltage protection unit and the first overcurrent protection unit, and the cathode of the first diode is used for receiving a first protection voltage.
In one embodiment, the dual driving circuit further includes:
and a second overvoltage protection unit, a first connection end of the second overvoltage protection unit is connected with the second end, a second connection end of the second overvoltage protection unit is connected with the output end in common and is connected with the target circuit, and the second overvoltage protection unit is used for clamping the voltage output by the target circuit to the second end within a second voltage threshold.
In one embodiment, the dual driving circuit further includes:
and the first connecting end of the second overcurrent protection unit is connected with the output end, the second connecting end of the second overcurrent protection unit is connected with the first connecting end of the second overvoltage protection unit, and the second overcurrent protection unit is used for controlling the second overvoltage protection unit to disconnect a conductive path between the second end and the target circuit if the current flowing to the second end of the second overvoltage protection unit exceeds a second current threshold.
In one embodiment, the dual driving circuit further includes:
and the anode of the second diode is respectively connected with the second overvoltage protection unit and the second overcurrent protection circuit, and the cathode of the second diode is used for receiving a second protection voltage.
In one embodiment, the driving unit is further configured to receive the second voltage domain signal through the second terminal to verify the second voltage domain signal when the first voltage domain signal is output through the first terminal.
In one embodiment, the voltage conversion unit includes a signal buffer, wherein an input pin of the signal buffer serves as the input terminal, an output pin of the signal buffer serves as the output terminal, and a power supply pin of the signal buffer is configured to receive the second voltage domain signal.
In one embodiment, the driving unit is further configured to receive a communication signal transmitted back by the target circuit through the second terminal.
The double-driving circuit outputs a first voltage domain signal through the first end or the second end of the driving unit, and then converts the first voltage domain signal into a second voltage domain signal through the voltage conversion unit connected with the first end, and transmits the second voltage domain signal to the target circuit, thereby realizing the output of the second voltage domain signal; or the first voltage domain signal is directly transmitted to the target circuit through the second end, so that the output of the first voltage domain signal is realized, and the output of multi-voltage range signals can be realized by selecting different ports of the driving unit for output.
Drawings
FIG. 1 is a block diagram of a dual driver circuit according to an embodiment of the present application;
FIG. 2 is a block diagram of a dual drive circuit according to another embodiment of the present application;
FIG. 3 is a block diagram of a dual drive circuit according to another embodiment of the present application;
FIG. 4 is a block diagram of a dual drive circuit according to another embodiment of the present application;
FIG. 5 is a block diagram of a dual drive circuit according to another embodiment of the present application;
FIG. 6 is a block diagram of a dual drive circuit according to another embodiment of the present application;
FIG. 7 is a block diagram of a dual drive circuit according to another embodiment of the present application;
FIG. 8 is a block diagram of a dual drive circuit according to another embodiment of the present application;
FIG. 9 is a block diagram of a dual drive circuit according to another embodiment of the present application;
FIG. 10 is a block diagram of a dual driver circuit according to another embodiment of the present application;
FIG. 11 is a block diagram of a dual driver circuit according to another embodiment of the present application;
FIG. 12 is a block diagram of a dual drive circuit according to another embodiment of the present application;
FIG. 13 is a block diagram of a dual drive circuit according to another embodiment of the present application.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without inventive step, are within the scope of the present disclosure.
It should be noted that all directional indicators (such as upper, lower, left, right, front and rear \8230;) in the embodiments of the present application are only used for explaining the relative positional relationship between the components, the motion situation, etc. in a specific posture (as shown in the attached drawings), and if the specific posture is changed, the directional indicators are correspondingly changed, and the connection can be a direct connection or an indirect connection.
Furthermore, descriptions in this application as to "first," "second," etc. are for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
FIG. 1 is a block diagram of a dual driving circuit according to an embodiment, the dual driving circuit includes a driving unit 110 and a voltage converting unit 120, the driving unit 110 includes a first terminal and a second terminal; the input end of the voltage conversion unit 120 is connected to the first end, and the output end of the voltage conversion unit 120 is connected to the second end and connected to the target circuit 100; the driving unit 110 is configured to: outputting a first voltage domain signal to the target circuit 100; or outputting the first voltage domain signal to the voltage converting unit 120, so that the voltage converting unit 120 converts the first voltage domain signal into the second voltage domain signal in the operating state, and transmits the second voltage domain signal to the target circuit 100; wherein the voltage of the second voltage domain signal is greater than the voltage of the first voltage domain signal.
It is understood that the voltage of the first voltage domain signal is within a first voltage domain, the voltage of the second voltage domain signal is within a second voltage domain, the first voltage domain and the second voltage domain are different voltage domains, wherein the voltage of the signal within the second voltage domain is greater than the voltage of the signal within the first voltage domain.
The voltage of the second voltage domain signal is greater than that of the first voltage domain signal, and the driving unit 110 selects one of the first terminal and the second terminal to output when outputting the first voltage domain signal. The first end is connected to the voltage conversion unit 120 so that the voltage conversion unit 120 boosts the first voltage domain signal and transmits the boosted first voltage domain signal to the target circuit 100, which can be identified as a high voltage driving line, the second end is directly connected to the target circuit 100 so as to transmit the first voltage domain signal, which can be identified as a normal voltage driving line, the driving unit 110 can be an FPGA device, and outputs a voltage depending on the VCCIO pin of the FPGA device, the voltage value of the first voltage domain signal is within a voltage limit range allowed to be received by the VCCIO pin, which is usually 0V-3.3V, and the second voltage domain signal converted by the voltage conversion unit 120 is greater than 3.3V and exceeds the voltage limit range of the VCCIO pin. Therefore, when the required voltage of the target circuit 100 is within the voltage limit of the VCCIO pin, the target circuit 100 may be driven by using a normal voltage driving line; when the required voltage of the target circuit 100 is greater than the voltage limit range of the VCCIO pin, the target circuit 100 may be driven by using a high-voltage driving circuit.
The voltage conversion unit 120 may include a bidirectional voltage conversion chip or a signal buffer 121, so as to implement voltage conversion.
The voltage converting unit 120 can convert the first voltage domain signal into the second voltage domain signal only when it is in a working state, and the working state can be controlled by an external circuit, the driving unit 110, or a worker. The target circuit 100 may be an external circuit to be driven, and may include a chip to be programmed.
The embodiment of the present invention outputs the first voltage domain signal through the first end or the second end of the driving unit 110, and then converts the first voltage domain signal into the second voltage domain signal through the voltage converting unit 120 connected to the first end, and transmits the second voltage domain signal to the target circuit 100, thereby realizing the output of the second voltage domain signal; or the first voltage domain signal is directly transmitted to the target circuit 100 through the second terminal, so that the output of the first voltage domain signal is realized, and thus, by selecting different ports of the driving unit 110 for output, the output of multiple voltage range signals can be realized, the matching of the voltage output and the target circuit 100 is realized, and the circuit is simple and reliable.
In one embodiment, as shown in fig. 2, the dual drive circuit further includes a first overvoltage protection unit 130, a first connection end of the first overvoltage protection unit 130 is connected to the output end, a second connection end of the first overvoltage protection unit 130 is commonly connected to the second end and is connected to the target circuit 100, and the first overvoltage protection unit 130 is configured to clamp a voltage output by the target circuit 100 to the voltage conversion unit 120 within a first voltage threshold.
The first voltage threshold may be determined according to a voltage withstanding characteristic of the voltage converting unit 120, and may not exceed a maximum voltage that the voltage converting unit 120 is allowed to receive. It is understood that the target circuit 100 is connected with a high voltage power supply, and in order to prevent external high voltage from the target circuit 100 from flowing into the voltage converting unit 120 and causing damage to the voltage converting unit 120, a first overvoltage protecting unit 130 may be connected between the voltage converting unit 120 and the target circuit 100 to monitor the voltage flowing into the first overvoltage protecting unit 130 by the target circuit 100. The first overvoltage protection unit 130 is respectively connected between the common connection end of the driving circuit and the target circuit 100 and the output end of the voltage conversion unit 120, so as to ensure that the first overvoltage protection unit 130 performs overvoltage protection on the high-voltage driving circuit.
In one embodiment, as shown in fig. 3, the first overvoltage protection unit 130 may include a field effect transistor M1, wherein the field effect transistor M1 may be an N-type field effect transistor, a gate of the field effect transistor M1 is configured to receive the control voltage VHMAX1, a source of the field effect transistor M1 is connected to the output terminal of the voltage conversion unit 120 as a first connection terminal of the first overvoltage protection unit 130, and a drain of the field effect transistor M1 is connected to the second terminal of the driving unit 110 as a second connection terminal of the first overvoltage protection unit 130. In the process that the driving unit 110 converts the first voltage domain signal into the second voltage domain signal through the voltage converting unit 120 and transmits the second voltage domain signal to the target circuit 100, since the voltage of the gate of the field effect transistor M1 is equal to VHMAX1 and is greater than the voltage of the second voltage domain signal, the field effect transistor M1 is turned on and transmits the second voltage domain signal output by the voltage converting unit 120 to the target circuit 100; when the target circuit 100 generates a high voltage output exceeding the first voltage threshold and transmits the high voltage output to the voltage conversion unit 120, the fet M1 clamps the voltage output to the voltage conversion unit 120 within the first voltage threshold, thereby preventing the high voltage on the target circuit 100 side from being transmitted to the voltage conversion unit 120, and achieving the purpose of overvoltage protection. Wherein the first voltage threshold may be within a first voltage domain.
The first overvoltage protection unit 130 may further include a resistor R11 and a diode D11; where D11 may be a schottky diode. The first connection end of the resistor R11 is connected with the grid electrode of the field-effect tube M1, the second connection end of the resistor R11 is used for receiving the control voltage VHMAX1, the anode of the diode D11 is respectively connected with the first connection end of the resistor R11 and the grid electrode of the field-effect tube M1, and the cathode of the diode D11 is connected with the second connection end of the resistor R11 so as to receive the control voltage VHMAX1 together. The control voltage VHMAX1 is an overvoltage clamp protection voltage to control the conduction of the fet M1. As can be seen, the first voltage threshold can be VHMAX1-V gs1 The voltage flowing through the field effect transistor M1 is within the first voltage threshold, where V gs1 Is the turn-on voltage of the fet M1.
In one embodiment, as shown in fig. 4, the dual driving circuit further includes a first over-current protection unit 140, a first connection end of the first over-current protection unit 140 is connected to the output end, a second connection end of the first over-current protection unit 140 is connected to a first connection end of the first over-voltage protection unit 130, and the first over-current protection unit 140 is configured to control the first over-voltage protection unit 130 to disconnect a conductive path between the voltage conversion unit 120 and the target circuit 100 if a current flowing from the first over-voltage protection unit 130 to the voltage conversion unit 120 exceeds a first current threshold.
The first current threshold may be determined according to the current withstanding characteristics of the voltage converting unit 120. Since the target circuit 100 is connected to a high voltage power supply, when a large current is generated at the target circuit 100 and flows to the voltage converting unit 120, in order to prevent the voltage converting unit 120 from being damaged due to the large current, a first overcurrent protecting unit 140 may be connected between the voltage converting unit 120 and the first voltage protecting unit to monitor the current flowing into the target circuit 100.
It can be understood that the voltage conversion unit 120, the first overcurrent protection unit 140, the first overvoltage protection unit 130 and the target circuit 100 are connected in sequence; in one embodiment, the first over-current protection unit 140 controls the first over-voltage protection unit 130 to disconnect a conductive path between the voltage conversion unit 120 and the target circuit 100, and the first over-voltage protection unit 130 may be controlled by the first over-current protection unit 140 to disconnect the first over-current protection unit 140 itself. As shown in fig. 5, the first overcurrent protection unit 140 may include a resistor R12, a resistor R13, a capacitor C11, and a transistor Q1. The first connection end of the resistor R12 is respectively connected with the first connection end of the capacitor C11, the first connection end of the resistor R13 and the source electrode of the field-effect tube M1; a second connecting end of the resistor R12 is respectively connected with a second connecting end of the capacitor C11 and an emitting electrode of the triode Q1; the base set of the triode Q1 is connected with the second connecting end of the resistor R13, and the collector of the triode Q1 is respectively connected with the first connecting end of the resistor R11 and the grid of the field-effect tube M1.
It can be understood that, in the process that the driving unit 110 converts the first voltage domain signal into the second voltage domain signal through the voltage converting unit 120 and transmits the second voltage domain signal to the target circuit 100, because there is a voltage drop in the resistor R12, the voltage at the base of the transistor Q1 is lower than the voltage at the emitter, the transistor Q1 is not conductive, and the second voltage domain signal is transmitted to the target circuit 100 through the fet M1. When a large current is generated at the side of the target circuit 100 and flows to the voltage conversion unit 120, a voltage drop exists at two ends of the resistor R12, the base voltage of the triode Q1 is greater than the emitter voltage, the triode Q1 is turned on, the gate voltage of the field-effect tube M1 is equal to the voltage at the second end of the resistor R12 and is less than the source voltage of the field-effect tube M1, and the field-effect tube M1 is turned off, so that the purpose of overcurrent protection is achieved.
In one embodiment, as shown in fig. 6, the dual drive circuit further includes a first diode D12, an anode of the first diode D12 is connected to the first overvoltage protection unit 130 and the first overcurrent protection unit 140, respectively, and a cathode of the first diode D12 is configured to receive the first protection voltage VCLAMP1.
It can be understood that a line between the first overvoltage protection unit 130 and the first overcurrent protection unit 140 is connected to the anode of the first diode D12, and the cathode of the first diode D12 is used for receiving the first protection voltage VCLAMP1, so that the voltage between the first overvoltage protection unit 130 and the first overcurrent protection unit 140 can be clamped at the first protection voltage VCLAMP1, and the two-stage overvoltage protection of the voltage conversion unit 120 is realized.
In one embodiment, as shown in fig. 7, the dual driving circuit further includes a second overvoltage protection unit 150, a first connection terminal of the second overvoltage protection unit 150 is connected to the second terminal, a second connection terminal of the second overvoltage protection unit 150 is commonly connected to the output terminal and is connected to the target circuit 100, and the second overvoltage protection unit 150 is configured to clamp the voltage output from the target circuit 100 to the second terminal of the driving unit 110 within the second voltage threshold.
The second voltage threshold may be determined according to a voltage withstanding characteristic of the driving unit 110, and does not exceed a maximum voltage allowed to be received by the second terminal of the driving unit 110. It is understood that the target circuit 100 is connected to a high voltage power supply, and in order to prevent external high voltage from the target circuit 100 from flowing into the driving unit 110 and causing damage to the driving unit 110, a second overvoltage protection unit 150 may be connected to the normal voltage driving line between the driving unit 110 and the target circuit 100 to monitor the voltage input from the target circuit 100 to the second terminal of the driving unit 110. The second overvoltage protection unit 150 is connected between the common connection end of the voltage conversion unit 120 and the target circuit 100 and the second end of the driving unit 110, so as to ensure that the second overvoltage protection unit 150 performs overvoltage protection on the normal-voltage driving circuit.
In one embodiment, as shown in fig. 8, the second overvoltage protection unit 150 may include a field effect transistor M2, wherein the field effect transistor M2 may be an N-type field effect transistor, a gate of the field effect transistor M2 is configured to receive the control voltage VHMAX2, a source of the field effect transistor M2 is connected to the second terminal of the driving unit 110 as a first connection terminal of the second overvoltage protection unit 150, and a drain of the field effect transistor M2 is connected to the output terminal of the voltage conversion unit 120 and connected to the target circuit 100 as a second connection terminal of the second overvoltage protection unit 150. In the process that the driving unit 110 transmits the first voltage domain signal to the target circuit 100 through the second end, since the voltage of the gate of the field-effect transistor M2 is equal to the control voltage VHMAX2 and is greater than the voltage of the first voltage domain signal, the field-effect transistor M2 is turned on, and the first voltage domain output by the driving unit 110 is transmitted to the target circuit 100; when the target circuit 100 generates a high voltage output exceeding the second voltage threshold and transmits the high voltage output to the second end of the driving unit 110 through the normal voltage driving circuit, the fet M2 clamps the voltage output from the target circuit 100 to the second end of the driving unit 110 within the second voltage threshold, thereby preventing the high voltage on the side of the target circuit 100 from being transmitted to the second end of the driving unit 110, and achieving the purpose of overvoltage protection. Wherein the second voltage threshold may be within a second voltage domain.
The second overvoltage protection unit 150 may further include a resistor R21 and a diode D21; where D21 may be a schottky diode. The first connection end of the resistor R21 is connected with the grid electrode of the field-effect tube M2, the second connection end of the resistor R21 is used for receiving the control voltage VHMAX2, the anode of the diode D21 is respectively connected with the first connection end of the resistor R21 and the grid electrode of the field-effect tube M2, and the cathode of the diode D21 is connected with the second connection end of the resistor R21 so as to receive the control voltage VHMAX2 together. The control voltage VHMAX2 is an overvoltage clamp protection voltage for driving the fet M2. As can be seen from the figure, the second voltage threshold is VHMAX2-V gs2 The voltage flowing through the field effect transistor M2 is within the second voltage threshold, where V gs2 Is the turn-on voltage of the fet M2.
In an embodiment, the dual drive circuit further includes a second over-current protection unit 160, as shown in fig. 9, a first connection end of the second over-current protection unit 160 is connected to the second end, a second connection end of the second over-current protection unit 160 is connected to the first connection end of the second over-voltage protection unit 150, and the second over-current protection unit 160 is configured to control the second over-voltage protection unit 150 to break a conductive path between the second end and the target circuit 100 if a current flowing from the second over-voltage protection unit 150 to the second end of the driving unit 110 exceeds a second current threshold.
The second current threshold may be determined according to the current withstanding characteristics of the driving unit 110. Since the target circuit 100 is connected to the high voltage power supply, when a large current is generated at the side of the target circuit 100 and flows to the second end of the driving unit 110, in order to prevent the driving unit 110 from being damaged due to the large current, a second over-current protection unit 160 may be connected between the driving unit 110 and the second voltage protection unit, so as to monitor the current flowing from the target circuit 100 to the second over-current protection unit 160.
It can be understood that the second terminal of the driving unit 110, the second overcurrent protection unit 160, the second overvoltage protection unit 150, and the target circuit 100 are connected in sequence; in one embodiment, the second over-current protection unit 160160 controls the second over-voltage protection unit 150 to disconnect the conductive path between the second terminal and the target circuit 100, and the second over-voltage protection unit 150 can be controlled by the second over-current protection unit 160 to disconnect the second over-current protection unit 160 itself. As shown in fig. 10, the second overcurrent protection unit 160 may include a resistor R22, a resistor R23, a capacitor C21, and a transistor Q2. The first connection end of the resistor R22 is respectively connected with the first connection end of the capacitor C21, the first connection end of the resistor R21 and the source electrode of the field-effect tube M2; a second connecting end of the resistor R22 is respectively connected with a second connecting end of the capacitor C21 and an emitting electrode of the triode Q2; the base set of the triode Q2 is connected with the second end of the resistor R23, and the collector of the triode Q2 is respectively connected with the first connecting end of the resistor R21 and the grid of the field-effect tube M2.
It can be understood that, in the process that the driving unit 110 transmits the voltage domain signal of the first voltage domain signal to the target circuit 100 through the second terminal, because there is a voltage drop in the resistor R22, the voltage at the base of the transistor Q2 is smaller than the voltage at the emitter, the transistor Q2 is not conductive, and the first voltage domain signal is transmitted to the target circuit 100 through the field effect transistor M2. When a large current is generated at the side of the target circuit 100 and flows to the target circuit 100, a voltage drop exists at two ends of the resistor R22, the base voltage of the triode Q2 is greater than the emitter voltage, the triode Q2 is conducted, the grid voltage of the field-effect tube M2 is equal to the voltage of the second end of the resistor R22 and is less than the source voltage of the field-effect tube M2, and the field-effect tube M2 is disconnected, so that the purpose of overcurrent protection is achieved.
In one embodiment, as shown in fig. 11, the dual drive circuit further includes a second diode D22, an anode of the second diode D22 is connected to the second overvoltage protection unit 150 and the second overcurrent protection circuit, respectively, and a cathode of the second diode D22 is configured to receive the second protection voltage.
It can be understood that a line point between the second overvoltage protection unit 150 and the second overcurrent protection unit 160 is connected to an anode of the second diode D22, and a cathode of the second diode D22 is used for receiving the second protection voltage VCLAMP2, so that the voltage between the second overvoltage protection unit 150 and the second overcurrent protection unit 160 can be clamped at the second protection voltage VCLAMP2, and the second-stage overvoltage protection of the driving unit 110 is realized.
In one embodiment, the driving unit 110 is further configured to receive a second voltage domain signal through the second terminal to verify the second voltage domain signal in case that the first voltage domain signal is output through the first terminal.
It can be understood that when the driving unit 110 outputs the first voltage domain signal through the first terminal, the second terminal thereof can be used as a receiving terminal to receive the second voltage domain signal output by the voltage converting unit 120, and then the received second voltage domain signal is compared with the reference value for verification, so as to further determine whether the second voltage domain signal converted by the voltage converting unit 120 meets the driving requirement of the target circuit 100.
In one embodiment, the voltage converting unit 120 may include a signal buffer 121, as shown in fig. 12, wherein an input pin of the signal buffer 121 serves as an input terminal of the voltage converting unit 120, an output pin of the signal buffer 121 serves as an output terminal of the voltage converting unit 120, and a power supply pin of the signal buffer 121 is used for receiving the second voltage domain signal.
Specifically, the input pin a of the signal buffer 121 is connected to the first end of the driving unit 110 for receiving the first voltage domain signal output by the driving unit 110, the output pin Y of the signal buffer 121 is connected to the target circuit 100, and the power supply pin VCC of the signal buffer 121 receives the second voltage domain signal, which is denoted by a symbol HVIO in the figure.
It can be understood that the signal buffer 121 has a unidirectional output characteristic, and can effectively protect the driving unit 110 from the high voltage impact from the target circuit 100 side, and prevent the driving unit 110 from being damaged.
The signal buffer 121 may further include an enable pin EN for receiving an enable signal to control an operation state of the signal buffer 121, so as to implement input and output of the signal buffer 121. Wherein the enable pin EN can be connected with the driving unit 110, so that the signal buffer 121 is provided with an enable signal by the driving unit 110.
In one embodiment, the driving unit 110 is further configured to receive the communication signal transmitted back by the target circuit 100 through the second terminal.
It can be understood that the conventional method connects a bidirectional voltage conversion chip between the driving unit 110 and the target circuit 100 to realize voltage conversion and bidirectional communication between the driving unit 110 and the target circuit 100, but the bidirectional communication in this method needs to switch the communication direction, which may cause the signal transmission rate to be affected, thereby affecting the programming speed. The embodiment can perform voltage conversion through the high-voltage driving circuit, and receive the returned communication signal through the normal-voltage driving circuit, so that voltage conversion and bidirectional communication can be realized, communication direction does not need to be switched in the bidirectional communication process, and signal transmission rate is not influenced.
The embodiment of the present invention further provides a dual driving circuit, as shown in fig. 13, the dual driving circuit includes a driving unit 110, a voltage converting unit 120, a first overvoltage protection unit 130, a first overcurrent protection unit 140, a first diode D12, a second overvoltage protection unit 150, a second overcurrent protection unit 160, and a second diode D22.
Among them, the driving unit 110 may include an FPGA element 111; the voltage conversion unit 120 may include a signal buffer 121; the first overvoltage protection unit 130 includes a field effect transistor M1, a resistor R11, and a diode D11; the first overcurrent protection unit 140 includes a resistor R12, a resistor R13, a capacitor C11, and a transistor Q1; the second overvoltage protection unit 150 includes a field effect transistor M2, a resistor R21, and a diode D21; the second overcurrent protection unit 160 may include a resistor R22, a resistor R23, a capacitor C21, and a transistor Q2.
Specifically, the VCCIO terminal of the FPGA device 111 is configured to receive the voltage VC, the output terminal IO1 is connected to the enable terminal OE of the signal buffer 121, the output terminal IO2 is used as the first terminal of the driving unit 110 and connected to the input terminal a of the signal buffer 121, and the output terminal IO3 is used as the second terminal of the driving unit 110 and commonly connected to the second connection terminal of the resistor R22, the second connection terminal of the capacitor C21, and the emitter of the transistor Q2. A GND terminal of the signal buffer 121 is grounded, a power supply terminal VCC is configured to receive a second voltage domain signal (HVIO), and an output terminal Y is connected to a second connection terminal of the resistor R12, a second connection terminal of the capacitor C11, and an emitter of the transistor Q1, respectively; the first connection end of the resistor R12 is respectively connected with the first connection end of the capacitor C11, the first connection end of the resistor R13, the anode of the first diode D12 and the source electrode of the field-effect tube M1; the second connecting end of the resistor R13 is connected with the base electrode of the triode Q1; the cathode of the first diode D12 is used for receiving a first protection voltage VCLAMP1; the collector of the triode Q1 is respectively connected with the first connection end of the resistor R11, the grid of the field effect transistor M1 and the anode of the diode D11; a second connection of the resistor R11 is commonly connected to the cathode of the diode D11 and is configured to receive the voltage VHMAX1.
The first connection end of the resistor R22, the first connection end of the capacitor C21, the first connection end of the resistor R23, the anode of the second diode D22 and the source electrode of the field-effect tube M2 are connected together; a second connecting end of the resistor R23 is connected with the base electrode of the triode Q2; the collector of the triode Q2, the first connecting end of the resistor R21, the grid of the field-effect tube M2 and the anode of the diode D21 are connected together; the second connecting end of the resistor R21 and the cathode of the diode D21 are connected together and used for receiving a voltage VHMAX2; the drain of the field effect transistor M2 is commonly connected to the drain of the field effect transistor M1, and is connected to the target circuit 100.
In one embodiment, a resistor RW may be further connected between the drain of the fet M2, the drain of the fet M1, and the target circuit 100 to improve signal quality. In addition, a connector may be disposed between the resistor RW and the target circuit 100 to achieve circuit connection.
For the specific working principle and effect of the dual driving circuit of this embodiment, reference is made to the above embodiments, which are not described herein again.
The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all the equivalent structures or equivalent processes that can be directly or indirectly applied to other related technical fields by using the contents of the specification and the drawings of the present application are also included in the scope of the present application.
Claims (10)
1. A dual drive circuit, comprising:
a drive unit including a first end and a second end;
the input end of the voltage conversion unit is connected with the first end, and the output end of the voltage conversion unit is connected with the second end and is connected with a target circuit;
the drive unit is used for:
outputting a first voltage domain signal to the target circuit; or
Outputting the first voltage domain signal to the voltage conversion unit so as to convert the first voltage domain signal into a second voltage domain signal when the voltage conversion unit is in a working state, and transmitting the second voltage domain signal to the target circuit;
wherein a voltage of the second voltage domain signal is greater than a voltage of the first voltage domain signal.
2. A dual drive circuit according to claim 1, wherein said dual drive circuit further comprises:
the first overvoltage protection unit is connected with the output end through a first connection end, a second connection end of the first overvoltage protection unit is connected with the second end in common and is connected with the target circuit, and the first overvoltage protection unit is used for clamping the voltage output by the target circuit to the voltage conversion unit within a first voltage threshold.
3. A dual drive circuit according to claim 2, wherein said dual drive circuit further comprises:
the first overvoltage protection unit is used for controlling the first overvoltage protection unit to disconnect a conductive path between the voltage conversion unit and the target circuit if the current flowing to the voltage conversion unit from the first overvoltage protection unit exceeds a first current threshold value.
4. The dual drive circuit of claim 3, further comprising:
and the anode of the first diode is respectively connected with the first overvoltage protection unit and the first overcurrent protection unit, and the cathode of the first diode is used for receiving a first protection voltage.
5. A dual drive circuit according to claim 1, wherein said dual drive circuit further comprises:
and a second overvoltage protection unit, a first connection end of the second overvoltage protection unit is connected with the second end, a second connection end of the second overvoltage protection unit is connected with the output end in common and is connected with the target circuit, and the second overvoltage protection unit is used for clamping the voltage output by the target circuit to the second end within a second voltage threshold.
6. The dual drive circuit of claim 5, further comprising:
and the first connecting end of the second overcurrent protection unit is connected with the output end, the second connecting end of the second overcurrent protection unit is connected with the first connecting end of the second overvoltage protection unit, and the second overcurrent protection unit is used for controlling the second overvoltage protection unit to disconnect a conductive path between the second end and the target circuit if the current flowing to the second end of the second overvoltage protection unit exceeds a second current threshold.
7. A dual drive circuit according to claim 6, wherein said dual drive circuit further comprises:
and the anode of the second diode is respectively connected with the second overvoltage protection unit and the second overcurrent protection circuit, and the cathode of the second diode is used for receiving a second protection voltage.
8. The dual drive circuit according to claim 1, wherein said drive unit is further configured to receive said second voltage domain signal through said second terminal to verify said second voltage domain signal if said first voltage domain signal is output through said first terminal.
9. A dual drive circuit according to claim 1, wherein said voltage conversion unit comprises a signal buffer, wherein an input pin of said signal buffer is used as said input terminal, an output pin of said signal buffer is used as said output terminal, and a power supply pin of said signal buffer is used for receiving said second voltage domain signal.
10. The dual drive circuit according to claim 1, wherein said driving unit is further configured to receive a communication signal transmitted back from said target circuit through said second terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221710450.6U CN217935090U (en) | 2022-07-05 | 2022-07-05 | Dual drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221710450.6U CN217935090U (en) | 2022-07-05 | 2022-07-05 | Dual drive circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217935090U true CN217935090U (en) | 2022-11-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221710450.6U Active CN217935090U (en) | 2022-07-05 | 2022-07-05 | Dual drive circuit |
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| Country | Link |
|---|---|
| CN (1) | CN217935090U (en) |
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2022
- 2022-07-05 CN CN202221710450.6U patent/CN217935090U/en active Active
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