CN217880303U

CN217880303U - General drive control circuit applied to low-frequency bus

Info

Publication number: CN217880303U
Application number: CN202222237775.3U
Authority: CN
Inventors: 杜孝寒; 缪祥烨; 杜永博; 夏海峰; 李昭; 张方方
Original assignee: Xi'an Yimandi Electronic Technology Co ltd
Current assignee: Xi'an Yimandi Electronic Technology Co ltd
Priority date: 2022-08-24
Filing date: 2022-08-24
Publication date: 2022-11-22
Anticipated expiration: 2032-08-24

Abstract

A general drive control circuit applied to a low-frequency bus comprises a single chip microcomputer, a level conversion circuit unit and an I/O high-low level control unit; the level conversion circuit unit and the I/O high-low level control unit are connected to the single chip microcomputer; the level conversion circuit unit is used for connecting single-chip microcomputers of different voltage systems to carry out level conversion; the I/O high-low level control unit is used for realizing high-low level control through the singlechip. The portable control circuit of the utility model skillfully utilizes the mos tube to realize data communication among different voltage systems; the level conversion rate can reach 10Mhz; the low-frequency bus communication of a conventional serial port bus, an I2C bus, SPI, RS254, RS422, CAN and the like CAN be met. The cost is saved from the design, and the data communication between different voltage systems is easily realized.

Description

General drive control circuit applied to low-frequency bus

Technical Field

The utility model belongs to low frequency bus data transmission control field, in particular to be applied to general drive control circuit of low frequency bus.

Background

In the increasingly developed modern society, the types of products are more and more, and with the application of the traditional low-frequency products in the technical field of bus data transmission, the low-frequency products are widely applied. In the conventional technology, in the aspect of low-frequency product bus data transmission application, the signal logic voltage mismatch between systems occurs, and the bus needs to be differentiated by pulling up or pulling down. In order to solve the current situation, an integrated circuit chip in the aspect of level conversion is used in the market, but the integrated circuit chip is high in cost, complex in application and wasteful in resources. Low frequency bus products are often characterized by large batch size, high cost control requirements, and the like.

Disclosure of Invention

An object of the utility model is to provide a be applied to general drive control circuit of low frequency bus to the solution is with high costs, uses complicacy, and the wasting of resources's problem.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

a general drive control circuit applied to a low-frequency bus comprises a single chip microcomputer, a level conversion circuit unit and an I/O high-low level control unit; the level conversion circuit unit and the I/O high-low level control unit are connected to the single chip microcomputer; the level conversion circuit unit is used for connecting single-chip microcomputers of different voltage systems to carry out level conversion; the I/O high-low level control unit is used for realizing high-low level control through the singlechip.

Further, the level conversion circuit unit comprises an NMOS transistor Q2, a resistor R55, a resistor R54, and a resistor R57; the G electrode of the NMOS tube Q2 is connected with 3.3V, and the S electrode is connected with a resistor R55; the D pole is connected with a resistor R54; and a resistor R57 is connected between the D pole and the S pole of the NMOS tube Q2.

Further, the S pole of the NMOS tube Q2 is connected with a signal of a 3.3V system singlechip; and the D pole of the NMOS tube Q2 is connected with a signal of the 5V system singlechip.

Further, the resistor R57 is a 0 ohm resistor.

Further, the resistor R55 is connected to 3.3V, and the resistor R54 is connected to 5V.

Further, the I/O high-low level control unit includes a resistor R63, a resistor R76, a resistor R59, a capacitor C28, a switch S1, and a switch S2; the resistor R59, the resistor R63 and the resistor R76 are sequentially connected in series, and the resistor R76 is connected with the capacitor C28 in parallel; the switch S1 and the switch S2 are led out from the low end of the R59 and the low end of the R63 respectively.

Furthermore, the resistor R59 is connected with a power supply by 3.3V, the lower end of the resistor R76 is grounded,

further, the switch S1 and the switch S2 are led out and then connected to an I/O pin of the single chip microcomputer.

Compared with the prior art, the utility model discloses there is following technological effect:

the low-frequency bus driving control circuit of the utility model skillfully utilizes mos tubes to realize data communication between different voltage systems; the high-frequency conductivity of the NMOS tube is utilized to realize level conversion, and the rate can reach 10Mhz; the communication of conventional serial port buses, I2C buses, SPI, RS254, RS422, CAN and other low-frequency buses CAN be met. The cost is saved in design, and data communication among different voltage systems is easily realized;

the utility model discloses a pull-up resistance down in the presetting can be in the compatible pull-up IO's of design phase circuit matching, and the pull-up of relativity or pull-down resistance cooperation bus circuit can be selected according to the demand in the actual debugging phase realizes signal drive, and the signal after the drive is controlled through the high-speed conversion of signal level of the ingenious realization low frequency bus of level conversion circuit around the NMOS pipe. The circuit serving as a generalized design can well solve the problem that the later debugging requirement cannot be met by a single pull-up or pull-down or no pull-up and pull-down design. Therefore, the development period is shortened, the development cost is reduced, the problems of various hardware design changes such as subsequent scheme iteration and the like are solved, and meanwhile, the problem of unmatched bus communication levels among different voltage systems is solved.

Drawings

FIG. 1 is a level translation circuit diagram;

fig. 2 is a pull-up/pull-down circuit diagram of signal levels.

Detailed Description

The invention is further described below with reference to the accompanying drawings:

a general drive control circuit applied to a low-frequency bus comprises a level conversion circuit unit and an I/O high-low level control unit;

a general drive control circuit applied to a low-frequency bus comprises a level conversion circuit unit and an I/O high-low level control unit; the level conversion circuit unit consists of a resistor and a mos tube; the I/O high-low level control unit consists of a resistor, a capacitor and a switch.

A is applied to the general drive control circuit of low frequency bus, the level conversion circuit unit is made up of 3 resistances and 1 mos tube; the I/O high-low level control unit consists of 3 resistors, 1 capacitor and 2 switches.

The G pole of an NMOS tube Q2 of the level conversion circuit unit is connected with 3.3V, and the S pole is connected with 4.7K resistor R55 to 3.3V; the D pole is connected with a 4.7K resistor R54 to 5V, and a 0 ohm resistor R57 is innovatively reserved; meanwhile, the S pole of the NMOS tube is connected with a signal of a 3.3V system singlechip; the D pole is connected to the signal of the 5V system singlechip. In addition, a solution is communicated with the circuit to realize level conversion.

The I/O high-low level control unit consists of 3 resistors, 1 capacitor and 2 switches. The whole circuit is formed by connecting three resistors of a 10K resistor R59, a 0 ohm resistor R63 and a 10K resistor R76 in series, the upper end of the R59 is connected with a power supply 3.3V, the lower end of the R76 resistor is grounded, and the R76 is connected with a capacitor R28 in parallel; the switches S1 and S2 are respectively led out from the low end of the R59 and the low end of the R63, and control signals are sent to the I/O pin of the single chip microcomputer, so that high-low level control of the signals is realized.

The working principle is as follows:

when the circuit works normally, the driving of signals is realized by selecting a preset pull-up resistor or a preset pull-down resistor, so that the signals are always kept at logic '1' or '0' level with high reliability in the transmission process. After being driven, the signal is connected into an NMOS level conversion circuit, and the NMOS is connected into different pull-up voltages through the front end and the rear end, namely the front voltage and the rear voltage are respectively communicated with two different voltage systems. After the signal passes through the NMOS circuit, the logic level is smoothly switched from the 1 system level voltage to the "1" or "0" level voltage of the logic level of the back-stage 2 system, so that the level conversion among different systems is skillfully and simply realized, and the normal communication among the systems is realized;

the portable control circuit of the utility model skillfully utilizes the mos tube to realize data communication between different voltage systems; the level conversion rate can reach 10Mhz; the low-frequency bus communication of a conventional serial port bus, an I2C bus, SPI, RS254, RS422, CAN and the like CAN be met. The cost is saved in design, and data communication among different voltage systems is easily realized;

the bus driving control circuit is usually required to realize the control of a certain signal through the pull-up and pull-down of an I/O level, the conventional design is only a pull-up or pull-down design at present, and under certain extremely complex conditions, along with the change of hardware possibly required in the product development process, the single pull-up or pull-down or no pull-up and pull-down design cannot meet the debugging requirement in the later period, so that the design of the circuit compatible with the pull-up and pull-down I/O and the level conversion circuit to realize the driving control of the low-frequency bus can be used as a universal design to well solve the problems. Therefore, the development period is shortened, the development cost is reduced, and a plurality of hardware design change problems such as subsequent scheme iteration are solved.

Claims

1. A general drive control circuit applied to a low-frequency bus is characterized by comprising a single chip microcomputer, a level conversion circuit unit and an I/O high-low level control unit; the level conversion circuit unit and the I/O high-low level control unit are connected to the single chip microcomputer; the level conversion circuit unit is used for connecting single-chip microcomputers of different voltage systems to carry out level conversion; the I/O high-low level control unit is used for realizing high-low level control through the singlechip.

2. The general drive control circuit applied to the low-frequency bus of claim 1, wherein the level conversion circuit unit comprises an NMOS transistor Q2, a resistor R55, a resistor R54, and a resistor R57; the G electrode of the NMOS tube Q2 is connected with 3.3V, and the S electrode is connected with a resistor R55; the D pole is connected with a resistor R54; and a resistor R57 is connected between the D pole and the S pole of the NMOS tube Q2.

3. The general drive control circuit applied to the low-frequency bus of claim 2, wherein the S pole of the NMOS tube Q2 is connected with a signal of a 3.3V system singlechip; and the D electrode of the NMOS tube Q2 is connected with a signal of the 5V system singlechip.

4. The universal driving control circuit for low frequency buses according to claim 2, characterized in that the resistor R57 is a 0 ohm resistor.

5. The universal driving control circuit for low frequency buses according to claim 2, characterized in that the resistor R55 is connected to 3.3V, and the resistor R54 is connected to 5V.

6. The general drive control circuit applied to the low-frequency bus according to claim 1, wherein the I/O high-low level control unit comprises a resistor R63, a resistor R76, a resistor R59, a capacitor C28, a switch S1 and a switch S2; the resistor R59, the resistor R63 and the resistor R76 are sequentially connected in series, and the resistor R76 is connected with the capacitor C28 in parallel; the switch S1 and the switch S2 are led out from the low end of the R59 and the low end of the R63 respectively.

7. The universal driving control circuit for low frequency buses according to claim 6, characterized in that the resistor R59 is connected to the power supply 3.3V, and the resistor R76 is connected to the ground at the lower end.

8. The universal driving control circuit applied to the low-frequency bus according to claim 6, wherein the switch S1 and the switch S2 are connected to an I/O pin of the single chip microcomputer after being led out.