CN217847970U - Heterojunction battery and assembly - Google Patents
Heterojunction battery and assembly Download PDFInfo
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- CN217847970U CN217847970U CN202221169967.9U CN202221169967U CN217847970U CN 217847970 U CN217847970 U CN 217847970U CN 202221169967 U CN202221169967 U CN 202221169967U CN 217847970 U CN217847970 U CN 217847970U
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 89
- 239000002184 metal Substances 0.000 claims abstract description 89
- 230000009467 reduction Effects 0.000 claims abstract description 44
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 31
- 239000002002 slurry Substances 0.000 claims abstract description 10
- 239000002131 composite material Substances 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 15
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 12
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims description 12
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 9
- 229910003437 indium oxide Inorganic materials 0.000 claims description 6
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 6
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 6
- 229910001887 tin oxide Inorganic materials 0.000 claims description 6
- 239000011787 zinc oxide Substances 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 5
- 239000010408 film Substances 0.000 claims 8
- 239000010409 thin film Substances 0.000 claims 5
- 230000004888 barrier function Effects 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 238000004070 electrodeposition Methods 0.000 abstract 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 40
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 29
- 238000000151 deposition Methods 0.000 description 28
- 238000004140 cleaning Methods 0.000 description 21
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- 238000006243 chemical reaction Methods 0.000 description 19
- 238000000034 method Methods 0.000 description 17
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
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- 239000001257 hydrogen Substances 0.000 description 8
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- 238000009832 plasma treatment Methods 0.000 description 8
- 239000000243 solution Substances 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 6
- 229910052738 indium Inorganic materials 0.000 description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
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- 230000000996 additive effect Effects 0.000 description 4
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
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Abstract
The utility model discloses a heterojunction battery and subassembly belongs to heterojunction battery field, including crystalline silicon layer, crystalline silicon layer openly sets gradually first intrinsic amorphous silicon layer from inside to outside, N type doping amorphous silicon layer, first transparent conducting layer, first metal electrode, the back sets gradually second intrinsic amorphous silicon layer from inside to outside, P type doping amorphous silicon layer, the transparent conducting layer of second, second metal electrode, position department and/or the transparent conducting layer surface of second is located second metal electrode position department is formed with local reduction layer under first metal electrode on the surface of first transparent conducting layer, local reduction layer carrier concentration is higher than first transparent conducting layer and/or the transparent conducting layer of second. The beneficial effects of the utility model are that: a local reduction region is formed on the surface of the transparent conducting layer below the low-temperature metal slurry electrode, so that the local carrier concentration of the transparent conducting layer is increased, the interface barrier height between the transparent conducting layer and the low-temperature metal slurry electrode is reduced, and the lower contact resistance is obtained.
Description
Technical Field
The utility model relates to a heterojunction battery field particularly, relates to a heterojunction battery and subassembly.
Background
The monocrystalline silicon heterojunction solar cell has high conversion efficiency and is recognized as one of the key technologies of the next generation of large-scale industrialization by the photovoltaic industry.
The silicon-based heterojunction solar cell is generally manufactured by adopting an N-type monocrystalline silicon wafer with a double-sided pyramid suede structure, an intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer are deposited on the front side of the silicon wafer, the intrinsic amorphous silicon layer and a p-type doped amorphous silicon layer are deposited on the back side of the silicon wafer, and then a transparent conductive film and a metal electrode are respectively formed on the two sides of the silicon wafer.
In the prior art, the transparent conducting layer is easily affected by the adsorption of water vapor, oxygen, organic matters and the like in the air, so that the contact performance between the transparent conducting layer and the low-temperature slurry is poor, the contact resistance is increased, and finally the battery efficiency is low.
SUMMERY OF THE UTILITY MODEL
For overcoming among the prior art transparent conducting layer and low temperature thick liquids and between contact performance variation, the contact resistance increase finally leads to the problem on the low side of battery efficiency, the utility model provides a heterojunction battery, including the crystalline silicon layer, the crystalline silicon layer openly sets gradually first intrinsic amorphous silicon layer from inside to outside, N type doping amorphous silicon layer, first transparent conducting layer, first metal electrode, and the crystalline silicon layer back sets gradually second intrinsic amorphous silicon layer from inside to outside, P type doping amorphous silicon layer, second transparent conducting layer, second metal electrode, wherein:
and a local reduction layer is formed on the surface of the first transparent conductive layer at the position below the first metal electrode and/or on the surface of the second transparent conductive layer at the position below the second metal electrode, and the carrier concentration of the local reduction layer is higher than that of the first transparent conductive layer and/or the second transparent conductive layer.
The local reduction layer is arranged on the surface of the transparent conductive layer below the metal electrode, so that the contact resistance between the transparent conductive layer and the metal electrode is improved, and the cell filling factor and the photoelectric conversion efficiency are improved.
Preferably, the width of the local reduction layer is 5-50um.
Preferably, the crystalline silicon layer is N-type doped monocrystalline silicon, P-type doped monocrystalline silicon or P-type doped monocrystalline silicon, and the thickness of the crystalline silicon layer is 50-250um.
Preferably, the first intrinsic amorphous silicon layer is a composite film layer formed by overlapping one or more of undoped amorphous silicon, amorphous silicon oxide and amorphous silicon carbide semiconductor films, and the thickness of the composite film layer is 2-8nm.
Preferably, the N-type doped amorphous silicon layer is one or a composite film layer formed by overlapping several of N-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon oxide and microcrystalline silicon carbide semiconductor films, and the thickness of the N-type doped amorphous silicon layer is 4-30nm.
Preferably, the P-type doped amorphous silicon layer is a composite film layer formed by laminating one or more of P-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon oxide and microcrystalline silicon carbide semiconductor films, and the thickness of the P-type doped amorphous silicon layer is 4-30nm.
Preferably, the first transparent conducting layer is a composite film layer formed by overlapping one or more of doped indium oxide, zinc oxide and tin oxide, and the thickness of the composite film layer is 70-120nm; the second transparent conducting layer is a composite film layer formed by overlapping one or more of doped indium oxide, zinc oxide and tin oxide, and the thickness of the second transparent conducting layer is 70-120nm.
Preferably, the first transparent conductive layer and the second transparent conductive layer are both ITO transparent conductive films, and the mass percentage of the indium element is 90%, and the mass percentage of the tin element is 10%.
Preferably, the first metal electrode is a low-temperature metal paste electrode which is formed by compounding one or more of Ag, cu, al and Ni, the thickness of the first metal electrode is 10-50um, and the width of the first metal electrode is 5-50um; the second metal electrode is a low-temperature metal slurry electrode which is formed by compounding one or more of Ag, cu, al and Ni, the thickness of the second metal electrode is 10-50um, and the width of the second metal electrode is 5-50um.
The utility model also provides a preparation method of above-mentioned heterojunction battery, including following step:
step one, providing a crystalline silicon layer;
step two, etching and cleaning;
step three, depositing a first intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer on the front surface of the crystalline silicon layer in the step two in sequence; depositing a second intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer on the back of the crystalline silicon layer in sequence;
depositing a first transparent conducting layer on the N-type doped amorphous silicon layer in the step three, and depositing a second transparent conducting layer on the P-type doped amorphous silicon layer;
placing a mask plate on the surface of the first transparent conducting layer and/or the second transparent conducting layer, and carrying out local cleaning and reduction on the transparent conducting layer by adopting hydrogen plasma treatment to obtain a local reduction region with relatively increased local carrier concentration, wherein the width of the local reduction region is 5-50um, and preferably 30-50um;
step six, forming a first metal electrode on the first transparent conductive layer by utilizing screen printing; forming a second metal electrode on the second transparent conductive layer by screen printing; and the metal electrode patterns of the first metal electrode and the second metal electrode are consistent with the opening pattern of the mask, and the first metal electrode and/or the second metal electrode are positioned right above the local reduction region.
A mask plate is placed on the surface of the transparent conducting layer, the opening pattern of the mask plate is consistent with the metal electrode pattern, and then hydrogen plasma treatment is adopted to carry out local cleaning and reduction on the transparent conducting layer, so that a local reduction layer with relatively increased local carrier concentration is obtained.
The utility model also provides a heterojunction battery pack, including two at least heterojunction batteries with the gear with the power, the positive negative pole of two adjacent heterojunction batteries is connected.
Has the beneficial effects that:
adopt the utility model discloses technical scheme produces beneficial effect as follows:
(1) Forming a local reduction region on the surface of the transparent conductive layer below the low-temperature metal slurry electrode, increasing the local carrier concentration of the transparent conductive layer, and reducing the interface barrier height between the transparent conductive layer and the low-temperature metal slurry electrode to obtain lower contact resistance; in addition, the surface after local treatment is cleaner and cannot be influenced by the adsorption of water vapor, oxygen and organic matters.
(2) A mask plate is placed on the surface of the transparent conducting layer, the opening pattern of the mask plate is consistent with the metal electrode pattern, and then hydrogen plasma treatment is adopted to carry out local cleaning and reduction on the transparent conducting layer, so that a local reduction layer with relatively increased local carrier concentration is obtained.
Drawings
In order to more clearly illustrate the technical solution of the embodiments of the present invention, the drawings which are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and that for those skilled in the art, other related drawings can be obtained according to these drawings without inventive efforts.
FIG. 1 is a diagram of a preferred battery layer structure of the present invention;
fig. 2 is a flow chart of a preferred heterojunction cell fabrication process of the present invention.
In the figure, 1, a crystalline silicon layer; 2. a first intrinsic amorphous silicon layer; 3. an N-type doped amorphous silicon layer; 4. a first transparent conductive layer; 5. a first metal electrode; 6. a second intrinsic amorphous silicon layer;
7. a P-type doped amorphous silicon layer; 8. a second transparent conductive layer; 9. a second metal electrode; 10. and a local reduction layer.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the drawings of the embodiments of the present invention are combined to clearly and completely describe the technical solutions of the embodiments of the present invention, and obviously, the described embodiments are some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
According to the embodiment, a local reduction region is formed on the surface of the transparent conducting layer below the low-temperature metal slurry electrode, so that the local carrier concentration of the transparent conducting layer is increased, the interface barrier height between the transparent conducting layer and the low-temperature metal slurry electrode is reduced, and lower contact resistance is obtained; in addition, the surface after local treatment is cleaner and cannot be influenced by the adsorption of water vapor, oxygen and organic matters. The specific implementation mode is as follows:
as shown in fig. 1, the heterojunction cell comprises a crystalline silicon layer 1, wherein a first intrinsic amorphous silicon layer 2, an N-type doped amorphous silicon layer 3, a first transparent conductive layer 4 and a first metal electrode 5 are sequentially disposed on the front surface of the crystalline silicon layer 1 from inside to outside, and a second intrinsic amorphous silicon layer 6, a P-type doped amorphous silicon layer 7, a second transparent conductive layer 8 and a second metal electrode 9 are sequentially disposed on the back surface of the crystalline silicon layer 1 from inside to outside, wherein:
a local reduction layer 10 is formed on the surface of the first transparent conductive layer 4 at a position below the first metal electrode 5 and/or on the surface of the second transparent conductive layer 8 at a position below the second metal electrode 9, and the carrier concentration of the local reduction layer 10 is higher than that of the first transparent conductive layer and/or the second transparent conductive layer.
The local reduction layer is arranged on the surface of the transparent conductive layer below the metal electrode, so that the contact resistance between the transparent conductive layer and the metal electrode is improved, and the cell filling factor and the photoelectric conversion efficiency are improved.
Wherein, the width of the local reduction layer 10 is 5-50um.
In a preferred embodiment, the crystalline silicon layer 1 is N-doped, P-doped, or P-doped single crystal silicon and has a thickness of 50-250um.
In a preferred embodiment, the first intrinsic amorphous silicon layer is a composite film layer formed by laminating one or more of undoped amorphous silicon, amorphous silicon oxide and amorphous silicon carbide semiconductor films, and the thickness of the composite film layer is 2-8nm.
In a preferred embodiment, the N-type doped amorphous silicon layer is a composite film layer formed by stacking one or more of N-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon oxide and microcrystalline silicon carbide semiconductor films, and the thickness of the composite film layer is 4-30nm.
In a preferred embodiment, the P-type doped amorphous silicon layer is a composite film layer formed by stacking one or more P-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon oxide and microcrystalline silicon carbide semiconductor films, and the thickness of the composite film layer is 4-30nm.
As a preferred embodiment, the first transparent conductive layer is a composite film layer formed by laminating one or more of doped indium oxide, zinc oxide and tin oxide, and the thickness of the composite film layer is 70-120nm; the second transparent conducting layer is a composite film layer formed by overlapping one or more of doped indium oxide, zinc oxide and tin oxide, and the thickness of the second transparent conducting layer is 70-120nm.
In a preferred embodiment, the first transparent conductive layer and the second transparent conductive layer are ITO transparent conductive films, and the mass percentage of the indium element is 90%, and the mass percentage of the tin element is 10%.
As a preferred embodiment, the first metal electrode is a low-temperature metal paste electrode which is formed by compounding one or more of Ag, cu, al and Ni, the thickness of the first metal electrode is 10-50um, and the width of the first metal electrode is 5-50um; the second metal electrode is a low-temperature metal slurry electrode which is formed by compounding one or more of Ag, cu, al and Ni, the thickness of the second metal electrode is 10-50um, and the width of the second metal electrode is 5-50um.
The embodiment also provides a preparation method of the heterojunction battery, which comprises the following steps:
step S101: providing a crystalline silicon layer; an N-type Czochralski monocrystalline silicon wafer is adopted, the thickness is 50-250um, the resistivity is 3 omega cm, and the minority carrier lifetime is 2000 mus.
Step S102: etching and cleaning; and (3) carrying out silicon wafer texturing by using a mixed solution of NaOH and a texturing additive with the mass percentage of 2%. And then, cleaning the surface of the silicon wafer by adopting an RCA standard cleaning method to remove surface pollution impurities. Next, the surface oxide layer was removed with a hydrofluoric acid solution of 2% by mass.
Step S103: and depositing first intrinsic amorphous silicon with the thickness of 2-8nm on the front surface of the crystalline silicon layer by adopting a PECVD (plasma enhanced chemical vapor deposition) process, wherein the reaction gases are SiH4 and H2, and the flow ratio of the H2 to the SiH4 is 5. The power density of a power supply of PECVD equipment is 20mW/cm & lt 2 & gt, the pressure is 70Pa, and the temperature of a substrate is 200 ℃; then depositing an N-type doped amorphous silicon layer with the thickness of 4-30nm on the first intrinsic amorphous silicon; the reaction gases are SiH4, H2 and PH3, the flow ratio of the H2 to the SiH4 is 5, and the flow ratio of the PH3 to the SiH4 is 0.02. The power density of a power supply of the PECVD equipment is 15mW/cm < 2 >, the pressure is 80Pa, and the temperature of a substrate is 200 ℃.
And depositing second intrinsic amorphous silicon with the thickness of 2-8nm on the front surface of the crystalline silicon layer by adopting a PECVD (plasma enhanced chemical vapor deposition) process, wherein the reaction gases are SiH4 and H2, and the flow ratio of the H2 to the SiH4 is 5. The power density of a power supply of PECVD equipment is 20mW/cm & lt 2 & gt, the pressure is 70Pa, and the temperature of a substrate is 200 ℃; and depositing a 4-30nm thick P-type doped amorphous silicon layer on the second intrinsic amorphous silicon layer, wherein the reaction gases are SiH4, B2H6 and H2, the flow ratio of H2 to SiH4 is 4, and the flow ratio of B2H6 to SiH4 is 0.04. The power density of a power supply of the PECVD equipment is 15mW/cm < 2 >, the pressure is 60Pa, and the substrate temperature is 200 ℃.
Step S104: depositing a first transparent conducting layer with the thickness of 70-120nm on the N-type doped amorphous silicon layer by adopting a PVD method, and depositing a second transparent conducting layer with the thickness of 70-120nm on the P-type doped amorphous silicon layer; the first transparent conducting layer and the second transparent conducting layer are both ITO transparent conducting films, the mass percent of indium elements in the ITO is 90%, and the mass percent of tin elements is 10%. Ar and O2 are filled in the PVD equipment, the flow ratio of the O2 to the Ar is 0.025, the pressure is 0.5Pa, and the temperature of the substrate is room temperature.
Step S105: placing a mask plate on the surface of the first transparent conducting layer and/or the second transparent conducting layer, wherein the opening pattern of the mask plate is consistent with the metal electrode pattern, and locally cleaning and reducing the transparent conducting layer by adopting hydrogen plasma treatment to obtain a local reduction region with relatively increased local carrier concentration, wherein the width of the local reduction region is 5-50um, and preferably 30-50um; the carrier concentration of the local reduction layer is higher than that of the first transparent conductive layer and/or the second transparent conductive layer.
Step S106: forming a first metal electrode on the first transparent conductive layer by screen printing; forming a second metal electrode on the second transparent conductive layer by screen printing; and the metal electrode patterns of the first metal electrode and the second metal electrode are consistent with the opening pattern of the mask, and the first metal electrode and/or the metal electrode are positioned right above the local reduction region.
A mask plate is placed on the surface of the transparent conducting layer, opening patterns of the mask plate are consistent with metal electrode patterns, and then hydrogen plasma treatment is adopted to carry out local cleaning and reduction on the transparent conducting layer, so that a local reduction layer with relatively increased local carrier concentration is obtained.
The embodiment also provides a heterojunction battery assembly which comprises at least two heterojunction batteries with the same gear and the same power, wherein the positive electrode and the negative electrode of every two adjacent heterojunction batteries are connected.
The first embodiment is as follows:
a method of making a heterojunction cell, comprising the steps of:
step one, providing a crystalline silicon layer; an N-type Czochralski monocrystalline silicon wafer is adopted, the thickness is 150 mu m, the resistivity is 3 omega cm, and the minority carrier lifetime is 2000 mu s.
Step two, etching and cleaning; and (3) carrying out silicon wafer texturing by using a mixed solution of NaOH and a texturing additive. And then, cleaning the surface of the silicon wafer by adopting an RCA standard cleaning method to remove surface pollution impurities. Next, the surface oxide layer is removed with a hydrofluoric acid solution.
And thirdly, depositing first intrinsic amorphous silicon with the thickness of 6nm on the front surface of the crystalline silicon layer by adopting a PECVD (plasma enhanced chemical vapor deposition) process, wherein the reaction gases are SiH4 and H2, and the flow ratio of the H2 to the SiH4 is 5. The power density of a power supply of PECVD equipment is 20mW/cm < 2 >, the pressure is 70Pa, and the temperature of a substrate is 200 ℃; then depositing an N-type doped amorphous silicon layer with the thickness of 6nm on the first intrinsic amorphous silicon; the reaction gases were SiH4, H2 and PH3, the flow ratio of H2 to SiH4 was 5, and the flow ratio of PH3 to SiH4 was 0.02. The power density of a power supply of the PECVD equipment is 15mW/cm < 2 >, the pressure is 80Pa, and the temperature of a substrate is 200 ℃.
And depositing second intrinsic amorphous silicon with the thickness of 7nm on the front surface of the crystalline silicon layer by adopting a PECVD process, wherein the reaction gases are SiH4 and H2, and the flow ratio of the H2 to the SiH4 is 5. The power density of a power supply of PECVD equipment is 20mW/cm & lt 2 & gt, the pressure is 70Pa, and the temperature of a substrate is 200 ℃; and depositing a 10 nm-thick P-type doped amorphous silicon layer on the second intrinsic amorphous silicon, wherein the reaction gases are SiH4, B2H6 and H2, the flow ratio of H2 to SiH4 is 4, and the flow ratio of B2H6 to SiH4 is 0.04. The power density of a power supply of the PECVD equipment is 15mW/cm < 2 >, the pressure is 60Pa, and the substrate temperature is 200 ℃.
Depositing a first transparent conducting layer with the thickness of 75nm on the N-type doped amorphous silicon layer by adopting a PVD method, and depositing a second transparent conducting layer with the thickness of 75nm on the P-type doped amorphous silicon layer; the first transparent conducting layer and the second transparent conducting layer are both ITO transparent conducting films, the mass percent of indium elements in the ITO is 90%, and the mass percent of tin elements is 10%. Ar and O2 are filled in the PVD equipment, the flow ratio of the O2 to the Ar is 0.025, the pressure is 0.5Pa, and the temperature of the substrate is room temperature.
Fifthly, respectively placing mask plates on the surfaces of the first transparent conducting layer and the second transparent conducting layer, wherein the opening patterns of the mask plates are consistent with the metal electrode patterns, and performing local cleaning and reduction on the transparent conducting layers by adopting hydrogen plasma treatment to obtain local reduction regions with relatively increased local carrier concentration, wherein the width of the local reduction regions is 30 micrometers; the carrier concentration of the local reduction layer is higher than that of the first transparent conductive layer and the second transparent conductive layer.
Step six, forming a first metal electrode on the first transparent conducting layer by utilizing screen printing; forming a second metal electrode on the second transparent conductive layer by screen printing; and the metal electrode patterns of the first metal electrode and the second metal electrode are consistent with the opening pattern of the mask, and the first metal electrode and the second metal electrode are positioned right above the local reduction region.
The second embodiment:
a method of making a heterojunction cell, comprising the steps of:
step one, providing a crystalline silicon layer; an N-type Czochralski monocrystalline silicon wafer is adopted, the thickness is 100 mu m, the resistivity is 3 omega cm, and the minority carrier lifetime is 2000 mu s.
Step two, etching and cleaning; and (3) carrying out silicon wafer texturing by using a mixed solution of NaOH and a texturing additive. And then, cleaning the surface of the silicon wafer by adopting an RCA standard cleaning method to remove surface pollution impurities. Next, the surface oxide layer is removed with a hydrofluoric acid solution.
And thirdly, depositing first intrinsic amorphous silicon with the thickness of 5nm on the front surface of the crystalline silicon layer by adopting a PECVD (plasma enhanced chemical vapor deposition) process, wherein the reaction gases are SiH4 and H2, and the flow ratio of the H2 to the SiH4 is 5. The power density of a power supply of PECVD equipment is 20mW/cm < 2 >, the pressure is 70Pa, and the temperature of a substrate is 200 ℃; then depositing an N-type doped amorphous silicon layer with the thickness of 8nm on the first intrinsic amorphous silicon; the reaction gases are SiH4, H2 and PH3, the flow ratio of the H2 to the SiH4 is 5, and the flow ratio of the PH3 to the SiH4 is 0.02. The power density of a power supply of the PECVD equipment is 15mW/cm < 2 >, the pressure is 80Pa, and the substrate temperature is 200 ℃.
And depositing second intrinsic amorphous silicon with the thickness of 7nm on the front surface of the crystalline silicon layer by adopting a PECVD process, wherein the reaction gases are SiH4 and H2, and the flow ratio of the H2 to the SiH4 is 5. The power density of a power supply of PECVD equipment is 20mW/cm < 2 >, the pressure is 70Pa, and the temperature of a substrate is 200 ℃; and depositing a 10 nm-thick P-type doped amorphous silicon layer on the second intrinsic amorphous silicon, wherein the reaction gases are SiH4, B2H6 and H2, the flow ratio of H2 to SiH4 is 4, and the flow ratio of B2H6 to SiH4 is 0.04. The power density of a power supply of the PECVD equipment is 15mW/cm < 2 >, the pressure is 60Pa, and the temperature of a substrate is 200 ℃.
Depositing a first transparent conducting layer with the thickness of 100nm on the N-type doped amorphous silicon layer by adopting a PVD method, and depositing a second transparent conducting layer with the thickness of 100nm on the P-type doped amorphous silicon layer; the first transparent conducting layer and the second transparent conducting layer are both ITO transparent conducting films, the mass percent of indium elements in the ITO is 90%, and the mass percent of tin elements is 10%. Ar and O2 are filled in the PVD equipment, the flow ratio of the O2 to the Ar is 0.025, the pressure is 0.5Pa, and the temperature of the substrate is room temperature.
Placing a mask plate on the surface of the first transparent conducting layer, wherein an opening pattern of the mask plate is consistent with a metal electrode pattern, and locally cleaning and reducing the transparent conducting layer by adopting hydrogen plasma treatment to obtain a local reduction region with relatively increased local carrier concentration, wherein the width of the local reduction region is 30 micrometers; the carrier concentration of the local reduction layer is higher than that of the first transparent conductive layer.
Step six, forming a first metal electrode on the first transparent conductive layer by utilizing screen printing; forming a second metal electrode on the second transparent conductive layer by screen printing; and the metal electrode pattern of the first metal electrode is consistent with the opening pattern of the mask, and the first metal electrode is positioned right above the local reduction region.
Example three:
a method of making a heterojunction cell, comprising the steps of:
step one, providing a crystalline silicon layer; a P-type Czochralski monocrystalline silicon wafer is adopted, the thickness is 150 mu m, the resistivity is 3 omega cm, and the minority carrier lifetime is 2000 mu s.
Step two, etching and cleaning; and (3) carrying out silicon wafer texturing by using a mixed solution of NaOH and a texturing additive. And then, cleaning the surface of the silicon wafer by adopting an RCA standard cleaning method to remove surface pollution impurities. Next, the surface oxide layer is removed with a hydrofluoric acid solution.
And thirdly, depositing first intrinsic amorphous silicon with the thickness of 5nm on the front surface of the crystalline silicon layer by adopting a PECVD (plasma enhanced chemical vapor deposition) process, wherein the reaction gases are SiH4 and H2, and the flow ratio of the H2 to the SiH4 is 5. The power density of a power supply of PECVD equipment is 20mW/cm & lt 2 & gt, the pressure is 70Pa, and the temperature of a substrate is 200 ℃; then depositing an N-type doped amorphous silicon layer with the thickness of 8nm on the first intrinsic amorphous silicon; the reaction gases are SiH4, H2 and PH3, the flow ratio of the H2 to the SiH4 is 5, and the flow ratio of the PH3 to the SiH4 is 0.02. The power density of a power supply of the PECVD equipment is 15mW/cm < 2 >, the pressure is 80Pa, and the substrate temperature is 200 ℃.
And depositing second intrinsic amorphous silicon with the thickness of 7nm on the front surface of the crystalline silicon layer by adopting a PECVD process, wherein the reaction gases are SiH4 and H2, and the flow ratio of the H2 to the SiH4 is 5. The power density of a power supply of PECVD equipment is 20mW/cm & lt 2 & gt, the pressure is 70Pa, and the temperature of a substrate is 200 ℃; and depositing a 10 nm-thick P-type doped amorphous silicon layer on the second intrinsic amorphous silicon, wherein the reaction gases are SiH4, B2H6 and H2, the flow ratio of H2 to SiH4 is 4, and the flow ratio of B2H6 to SiH4 is 0.04. The power density of a power supply of the PECVD equipment is 15mW/cm < 2 >, the pressure is 60Pa, and the temperature of a substrate is 200 ℃.
Depositing a first transparent conducting layer with the thickness of 100nm on the N-type doped amorphous silicon layer by adopting a PVD method, and depositing a second transparent conducting layer with the thickness of 100nm on the P-type doped amorphous silicon layer; the first transparent conducting layer and the second transparent conducting layer are both ITO transparent conducting films, the mass percent of indium elements in the ITO is 90%, and the mass percent of tin elements is 10%. Ar and O2 are filled in the PVD equipment, the flow ratio of the O2 to the Ar is 0.025, the pressure is 0.5Pa, and the temperature of the substrate is room temperature.
Placing a mask plate on the surface of the second transparent conducting layer, wherein an opening pattern of the mask plate is consistent with a metal electrode pattern, and performing local cleaning and reduction on the transparent conducting layer by adopting hydrogen plasma treatment to obtain a local reduction region with relatively increased local carrier concentration, wherein the width of the local reduction region is 30 microns; the carrier concentration of the local reduction layer is higher than that of the second transparent conducting layer.
Step six, forming a first metal electrode on the first transparent conductive layer by utilizing screen printing; forming a second metal electrode on the second transparent conductive layer by screen printing; and the metal electrode pattern of the second metal electrode is consistent with the opening pattern of the mask, and the second metal electrode is positioned right above the local reduction region.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. The heterojunction cell is characterized by comprising a crystalline silicon layer, wherein a first intrinsic amorphous silicon layer, an N-type doped amorphous silicon layer, a first transparent conducting layer and a first metal electrode are sequentially arranged on the front surface of the crystalline silicon layer from inside to outside, and a second intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer, a second transparent conducting layer and a second metal electrode are sequentially arranged on the back surface of the crystalline silicon layer from inside to outside, wherein:
and a local reduction layer is formed on the surface of the first transparent conductive layer at the position below the first metal electrode and/or on the surface of the second transparent conductive layer at the position below the second metal electrode, and the carrier concentration of the local reduction layer is higher than that of the first transparent conductive layer and/or the second transparent conductive layer.
2. A heterojunction cell according to claim 1, wherein said locally reduced layer has a width of 5-50um.
3. A heterojunction cell according to claim 1, wherein said crystalline silicon layer is N-doped, P-doped, or P-doped single crystal silicon and has a thickness of 50-250 μm.
4. The heterojunction cell of claim 1, wherein the first intrinsic amorphous silicon layer is a composite thin film layer formed by stacking one or more undoped amorphous silicon, amorphous silicon oxide and amorphous silicon carbide semiconductor thin films, and the thickness of the composite thin film layer is 2-8nm.
5. The heterojunction cell according to claim 1, wherein the N-type doped amorphous silicon layer is a composite film layer formed by laminating one or more of N-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon oxide and microcrystalline silicon carbide semiconductor films, and the thickness of the composite film layer is 4-30nm.
6. The heterojunction cell of claim 1, wherein the P-type doped amorphous silicon layer is a composite film layer formed by laminating one or more P-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon oxide and microcrystalline silicon carbide semiconductor films, and the thickness of the composite film layer is 4-30nm.
7. The heterojunction cell of claim 1, wherein the first transparent conductive layer is a composite thin film layer laminated by one or more of doped indium oxide, zinc oxide or tin oxide, and the thickness of the composite thin film layer is 70-120nm; the second transparent conducting layer is a composite film layer formed by overlapping one or more of doped indium oxide, zinc oxide and tin oxide, and the thickness of the second transparent conducting layer is 70-120nm.
8. A heterojunction cell according to claim 7, wherein said first transparent conductive layer and said second transparent conductive layer are ITO transparent conductive films.
9. A heterojunction cell according to claim 1, wherein said first metal electrode is a low temperature metal paste electrode having a thickness of 10-50um and a width of 5-50um;
and/or the second metal electrode is a low-temperature metal slurry electrode, the thickness of the second metal electrode is 10-50um, and the width of the second metal electrode is 5-50um.
10. A heterojunction battery assembly comprising at least two heterojunction batteries of the same power at the same level as in any of claims 1 to 9, wherein the positive and negative electrodes of two adjacent heterojunction batteries are connected.
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