CN217740183U - Testing device for automatically testing memory chip - Google Patents
Testing device for automatically testing memory chip Download PDFInfo
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- CN217740183U CN217740183U CN202221653987.3U CN202221653987U CN217740183U CN 217740183 U CN217740183 U CN 217740183U CN 202221653987 U CN202221653987 U CN 202221653987U CN 217740183 U CN217740183 U CN 217740183U
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Abstract
The utility model is suitable for a chip testing technology field provides an automatic change test storage chip's testing arrangement, include: the test board comprises a signal conversion module and a memory chip control module; the power supply module is connected with the signal conversion module and the storage chip control module; the memory chip control module is connected with an external terminal through the signal conversion module and is externally connected with a memory chip to be tested; the intelligent control module is connected with the storage chip control module and the external terminal; and the intelligent control module generates a corresponding control signal according to the type of the storage chip identified by the external terminal and automatically configures the IO port of the main control chip in the storage chip control module. The embodiment of the utility model provides a can save the cost, improve the efficiency of software testing to memory chip.
Description
Technical Field
The utility model belongs to the technical field of the chip test, especially, relate to an automatic change test storage chip's testing arrangement.
Background
Because the memory chip needs to be subjected to high-temperature aging sorting grade, high-temperature stability test needs to be carried out in large batch, and the card opening test needs to be carried out before and after the test. For Testing a memory chip, in the prior art, a single test board is used, the memory chip is manually mounted, an RDT (Reliability virtualization Testing) program is loaded and then the memory chip is placed in a high temperature furnace for Testing, and erasing and writing are simulated under a high temperature condition to accelerate the failure of a weak NAND flash memory block, so that the Reliability and the durability are improved to the maximum extent. The existing memory chip test board controls signal transmission by using a patch type dial switch, and different control chip IO configurations are needed to be carried out for different flashes, so that different branches of a main control chip are controlled by manual dial operations for different flashes during testing, IO configuration correct downloading programs of the control chips are changed, and signal transmission between a PC end and a test seat is finally realized. And because every test seat or test panel all contain more dial-up, especially when testing in batches, need a large amount of manual dials the dial-up switch, have caused a large amount of time and human cost, lead to the problem of efficiency of software testing low.
SUMMERY OF THE UTILITY MODEL
The utility model provides an automatic change test storage chip's testing arrangement, when aiming at solving among the above-mentioned prior art to big batch test, need a large amount of manual dial switch of stirring, cause time and human cost to consume, lead to the problem that efficiency of software testing is low.
The utility model is realized in such a way, and provides a testing device for automatically testing a memory chip, which comprises a testing board and an intelligent control module;
the test board comprises a power supply module, a signal conversion module and a memory chip control module;
the power supply module is connected with the signal conversion module and the storage chip control module;
the storage chip control module is connected with an external terminal through the signal conversion module, and is externally connected with a storage chip to be tested;
the intelligent control module is connected with the storage chip control module and the external terminal;
and the intelligent control module generates a corresponding control signal according to the type of the storage chip identified by the external terminal and automatically configures the IO port of the main control chip in the storage chip control module.
Furthermore, the memory chip control module comprises a plurality of main control chips, and each main control chip is externally connected with one memory chip to be tested.
Furthermore, the intelligent control module comprises an MCU chip, one end of the MCU chip is connected with the external terminal, and the other end of the MCU chip is connected with each main control chip.
Furthermore, the signal conversion module comprises bridge chips corresponding to the number of the main control chips, one end of each bridge chip is connected with one main control chip, and the other end of each bridge chip is connected to an interface of the external terminal through a signal transmitter.
Furthermore, the signal transmitter includes a USB hub, one end of the USB hub is connected to the USB interface of the external terminal, and the other end of the USB hub is correspondingly connected to the bridge chip through a plurality of included USB interfaces.
Further, the MCU chip is connected to the external terminal through wired/wireless connection.
Furthermore, the intelligent control module is externally connected with the test board.
Still further, the intelligent control module is disposed on the test board.
The utility model discloses the beneficial effect who reaches: this application is owing to provide a testing arrangement of automatic test memory chip, realizes the communication mode between automatic control external terminal and the test board through directly providing intelligent control module in testing arrangement, and external terminal sends intelligent control module after discerning the memory chip type of the memory chip that awaits measuring, and intelligent control module is according to the IO mouth of main control chip among the direct automatic configuration memory chip control module of control signal that generates, has replaced current manual dial-up to dispose. Therefore, the time and labor cost can be saved, and the testing efficiency of the memory chip is improved.
Drawings
Fig. 1 is a schematic diagram of a module structure of a testing apparatus for automatically testing a memory chip according to the present invention;
fig. 2 is a schematic structural diagram of another testing apparatus for automatically testing a memory chip according to the present invention;
fig. 3 is a configuration flowchart of a testing apparatus for automatically testing a memory chip according to the present invention;
in the figure, the device comprises an intelligent control module 1, an intelligent control module 2, a power supply module 3, a signal conversion module 4, a storage chip control module 5, an external terminal 6 and a storage chip.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The test jig in the prior art usually uses a dial switch for program control, needs manual dialing for control, consumes manpower and time, and has low efficiency. The application provides a testing device for automatically testing the memory chip, the communication mode between the external terminal and the testing board is automatically controlled by directly providing the intelligent control module in the testing device, the external terminal identifies the type of the memory chip to be tested and then sends the type of the memory chip to the intelligent control module, and the intelligent control module directly and automatically configures the IO port of the main control chip in the memory chip control module according to the generated control signal, so that the existing manual dial-up is replaced for configuration. Therefore, the time and labor cost can be saved, and the testing efficiency of the memory chip is improved.
Example one
In this embodiment, as shown in fig. 1, fig. 1 is a schematic block diagram of a testing apparatus for automatically testing a memory chip according to this embodiment. A testing device for automatically testing a memory chip comprises a testing board and an intelligent control module 1;
the test board comprises a power module 2, a signal conversion module 3 and a memory chip control module 4;
the power module 2 is connected with the signal conversion module 3 and the storage chip control module 4;
the storage chip control module 4 is connected with an external terminal 5 through the signal conversion module 3, and the storage chip control module 4 is externally connected with a storage chip 6 to be tested;
the intelligent control module 1 is connected with the storage chip control module 4 and the external terminal 5;
the intelligent control module 1 generates a corresponding control signal according to the type of the storage chip identified by the external terminal 5, and automatically configures the IO port of the main control chip in the storage chip control module 4.
The test board refers to a tool for Testing the memory chip 6 (flash), and the Testing includes opening the card and performing Reliability Testing (RDT). The intelligent control module 1 may be a single chip microcomputer for sending a control signal to the memory chip control module 4 according to the parameter configuration and performing automatic configuration according to the parameter configuration. The power module 2 is used for passing the working voltage of the testing device. The signal conversion module 3 may be used for the external terminal 5 to communicate with the memory chip control module 4. The memory chip control module 4 is used for connecting the memory chip 6 and the intelligent control module 1. The memory chips 6 to be tested include, but are not limited to, NAND, NOR, DRAM, and other tooling fixtures, and BGA, TSOP, QFN, and other packaging methods, and each memory chip 6 has a corresponding ID value.
Specifically, the external terminal 5 may identify the type of the memory chip through an IO port of the flash, then send a mapping table corresponding to the type of the memory chip to the intelligent control module 1 through any one of transmission modes including but not limited to USB interface conversion, serial port, network port, wireless, and the like, and the intelligent control module 1 generates a control signal according to parameter configuration corresponding to the type of the memory chip in the mapping table. The mapping table may include an ID value of the memory chip 6, and parameters such as corresponding parameter configuration (GPIO configuration), voltage, and corresponding card-open software, and different memory chip types correspond to different GPIO configuration tables.
Optionally, the intelligent control module 1 is externally connected to a test board, and as another possible embodiment, the intelligent control module 1 is disposed on the test board.
Specifically, after the memory chip 6 to be tested is mounted on the memory chip main control module 3, the external terminal 5 may read the ID value of the memory chip 6 to be tested based on the communication between the memory chip control module 4 and the intelligent control module 1, and may identify the type of the memory chip according to the ID value. The external terminal 5 sends the mapping table stored in the external terminal 5 to the intelligent control module 1 through any one of a serial port, a network port, a wireless mode and the like according to the type of the memory chip, and the intelligent control module 1 can correctly configure the voltages of different memory chips 6 and correctly configure the IO ports of the memory chip control module 4 through pulling up/down the potential (control signal) according to the parameter configuration in the mapping table.
It should be noted that the external terminal 5 may be various electronic devices having a display screen and supporting web browsing, and may also be referred to as a PC terminal, a terminal device, and the like, including but not limited to a smart phone, a tablet computer, a laptop portable computer, a desktop computer, and the like.
In this embodiment, by providing a testing apparatus for automatically testing a memory chip, the testing apparatus directly provides an intelligent control module 1 to implement communication between an automatic control PC and a testing board, after the PC identifies the type of the memory chip of a memory chip 6 to be tested, the PC sends the type of the memory chip to be tested to the intelligent control module 1 through any one of transmission modes including but not limited to USB interface conversion, serial port, network port, wireless, etc., and the intelligent control module 1 generates a control signal according to the correspondence between the type of the memory chip and GPIO configuration to directly and automatically configure the IO port of a main control chip in the memory chip control module 4, thereby replacing the existing manual dial-up for configuration. Therefore, the time and labor cost can be saved, and the testing efficiency of the memory chip 6 is improved.
Example two
In this embodiment, based on the first embodiment, the memory chip control module 4 includes a plurality of main control chips, and each main control chip is externally connected to one memory chip 6 to be tested. The signal conversion module 3 includes bridge chips corresponding to the number of the main control chips, one end of each bridge chip is connected to one main control chip, and the other end is connected to an interface of the external terminal 5 through a signal transmitter.
Referring to fig. 2, the main control chip includes a main control chip 1, a main control chip 2, and a main control chip 3. The bridge chip comprises a bridge chip 1, a bridge chip 2, a bridge chip 3 and a bridge chip. One bridging chip is connected with one main control chip, one main control chip is connected with one storage chip 6, all the main control chips and all the bridging chips are correspondingly connected to form a plurality of test branches, and the plurality of bridging chips are continuously connected with the PC end as a signal channel through the signal transmitter.
Optionally, the signal transmitter includes a USB HUB (USB HUB), one end of the USB HUB is connected to the USB interface of the external terminal 5, and the other end of the USB HUB is correspondingly connected to the bridge chip through a plurality of included USB interfaces. The USB HUB can realize one-to-many/one-to-many conversion of the USB interface. The bridging chip can convert the USB bus into an SATA bus protocol, realize the conversion between the USB interface and the SATA interface, and is used for the signal transmission between the external terminal 5 and the bridging chip.
Optionally, the intelligent control module 1 includes an MCU chip, one end of the MCU chip is connected to the external terminal 5, and the other end is connected to each main control chip.
Wherein, MCU Chip (MCU) is used for the IO mouth of all main control chips of automatic configuration, can carry out in batches when IO mouth disposes, for example: the test board is configured with 112 chips at the same time, but not limited to 112 chips, and can also control the configuration of more chips at the same time.
Specifically, referring to fig. 3, after the flash is connected to the main control chip, the PC terminal may identify the type of the memory chip according to the ID value by reading the ID value of the flash based on the communication between the main control chip and the MCU chip. The PC terminal sends a mapping table configured in the PC terminal to the MCU chip in any transmission mode including but not limited to USB interface conversion, serial port, network port, wireless and the like according to the type of the storage chip, and the MCU chip can realize correct configuration of different flash voltages and correct configuration of IO ports of the main control chip by generating control signals (pull-up/pull-down potential) according to parameter configuration in the mapping table.
Optionally, the MCU chip is connected to the external terminal 5 via wire/wireless.
The wireless connection means may include, but is not limited to, a 3G/4G connection, a WiFi connection, a bluetooth connection, a WiMAX connection, a Zigbee connection, a UWB (ultra wideband) connection, and other now known or later developed wireless connection means.
In this embodiment, a testing apparatus for automatically testing a memory chip is provided, in the testing apparatus, an MCU chip is directly provided to automatically control communication between a PC terminal and a testing board, after the PC terminal identifies a type of a flash memory chip to be tested, the PC terminal sends a mapping table corresponding to the type of the memory chip to the MCU chip through any one of transmission modes including but not limited to USB interface conversion, serial port, internet port, and wireless, and the MCU chip directly and automatically configures an IO port of a main control chip according to a corresponding relationship between the type of the memory chip and parameter configuration, thereby replacing the existing manual toggle dial-up switch for configuration. Therefore, the time and labor cost can be saved through automatic configuration, and the testing efficiency of the memory chip 6 is improved.
The terms "first," "second," and the like in the description and claims of this application or in the foregoing drawings are used for distinguishing between different objects and not for describing a particular sequential order. Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein may be combined with other embodiments.
The above description is only exemplary of the present invention and should not be construed as limiting the present invention, and any modifications, equivalents and improvements made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (8)
1. A kind of test device which tests the memory chip automatically, characterized by, including test board and intellectual control module;
the test board comprises a power supply module, a signal conversion module and a memory chip control module;
the power supply module is connected with the signal conversion module and the storage chip control module;
the storage chip control module is connected with an external terminal through the signal conversion module, and is externally connected with a storage chip to be tested;
the intelligent control module is connected with the storage chip control module and the external terminal;
and the intelligent control module generates a corresponding control signal according to the type of the storage chip identified by the external terminal, and automatically configures an IO port of a main control chip in the storage chip control module.
2. The apparatus as claimed in claim 1, wherein the memory chip control module comprises a plurality of main control chips, and each main control chip is externally connected to one of the memory chips to be tested.
3. The apparatus of claim 2, wherein the intelligent control module comprises an MCU chip, one end of the MCU chip is connected to the external terminal, and the other end of the MCU chip is connected to each of the main control chips.
4. The apparatus as claimed in claim 2, wherein the signal conversion module comprises bridge chips corresponding to the number of the main control chips, one end of each bridge chip is connected to one of the main control chips, and the other end of each bridge chip is connected to the interface of the external terminal through a signal transmitter.
5. The apparatus for automatically testing a memory chip as claimed in claim 4, wherein the signal transmitter comprises a USB hub, one end of the USB hub is connected to the USB interface of the external terminal, and the other end of the USB hub is correspondingly connected to the bridge chip through the plurality of USB interfaces.
6. The apparatus of claim 3, wherein the MCU chip is connected to the external terminal via wire/wireless connection.
7. The apparatus for automatically testing a memory chip as claimed in claim 1, wherein said intelligent control module is externally connected to said test board.
8. The apparatus of claim 1, wherein the intelligent control module is disposed on the test board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221653987.3U CN217740183U (en) | 2022-06-29 | 2022-06-29 | Testing device for automatically testing memory chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221653987.3U CN217740183U (en) | 2022-06-29 | 2022-06-29 | Testing device for automatically testing memory chip |
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| Publication Number | Publication Date |
|---|---|
| CN217740183U true CN217740183U (en) | 2022-11-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221653987.3U Active CN217740183U (en) | 2022-06-29 | 2022-06-29 | Testing device for automatically testing memory chip |
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| CN (1) | CN217740183U (en) |
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- 2022-06-29 CN CN202221653987.3U patent/CN217740183U/en active Active
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Address after: 518000, 1st Floor, 2nd Floor, 3rd Floor, No. 7 Xinfa East Road, Xiangshan Community, Xinqiao Street, Bao'an District, Shenzhen City, Guangdong Province, China Patentee after: Shenzhen Shi Creative Electronics Co.,Ltd. Country or region after: China Address before: 518000 floor 1, floor 2 and floor 3, No. 7, Xinfa East Road, Xiangshan community, Xinqiao street, Bao'an District, Shenzhen, Guangdong Province; No.5 1st, 2nd and 3rd floors Patentee before: SHENZHEN SHICHUANGYI ELECTRONIC CO.,LTD. Country or region before: China |
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