CN217590770U

CN217590770U - Chip packaging structure

Info

Publication number: CN217590770U
Application number: CN202221504096.1U
Authority: CN
Inventors: 谢国梁
Original assignee: China Wafer Level CSP Co Ltd
Current assignee: China Wafer Level CSP Co Ltd
Priority date: 2022-06-16
Filing date: 2022-06-16
Publication date: 2022-10-14
Anticipated expiration: 2032-06-16

Abstract

The utility model discloses a chip packaging structure, which comprises a functional substrate, wherein a rewiring layer is formed on the first surface of the functional substrate, and a plurality of cofferdams are formed on the rewiring layer; the chip to be packaged is provided with a first surface and a second surface which are arranged oppositely, a functional area and a welding pad coupled with the functional area are formed on the first surface, the first surface of the chip to be packaged and the first surface of the functional substrate are in counterpoint pressing, the welding pad is electrically connected with the rewiring layer, and the cofferdam is arranged on the periphery of the functional area of the chip to be packaged in an enclosing mode and is enclosed with the first surface of the chip to be packaged to form a cavity which surrounds the functional area. The utility model discloses a chip packaging structure, simple structure, many treat that the encapsulation chip is invertedly adorned on functional substrate, and the top surface in cofferdam contacts with the first surface of treating the encapsulation chip for the functional area of treating the encapsulation chip lies in the cavity that the cofferdam formed completely, plays the effect in protect function district.

Description

Chip packaging structure

Technical Field

The present invention relates to semiconductor packaging technology, and more particularly to a chip package structure.

Background

The surface acoustic wave filter is an important part of a mobile communication terminal product, and the raw material is made of piezoelectric crystals. The surface acoustic wave filter completes the filtering characteristic by utilizing the excitation, the transmission and the reception of the surface acoustic waves on the piezoelectric material. With the miniaturization and low cost of the mobile terminal, the requirement for packaging the surface acoustic wave filter is also increased correspondingly.

In the prior art, in order to guarantee the packaging precision of the surface acoustic wave filter, a relatively complex packaging process is generally adopted to package the surface acoustic wave filter, and the surface acoustic wave filter is packaged in a single package, so that the packaging efficiency is low, and the packaging cost is high.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information constitutes prior art already known to a person skilled in the art.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a chip packaging structure, simple structure, many treat that the encapsulation chip is adorned upside down on functional substrate, and the top surface in cofferdam contacts with the first surface of treating the encapsulation chip for the functional area of treating the encapsulation chip lies in the cavity that the cofferdam formed completely, plays the effect in protect function district.

In order to achieve the above object, an embodiment of the present invention provides a chip packaging method, including: providing a substrate; providing a chip to be packaged, wherein the chip to be packaged is provided with a first surface and a second surface which are oppositely arranged, and a functional area and a welding pad coupled with the functional area are formed on the first surface; bonding the second surfaces of the chips to be packaged with the surface of the substrate; providing a functional substrate, wherein the functional substrate is provided with a first surface, and a rewiring layer is formed on the first surface; forming a plurality of cofferdams on the first surface of the chip to be packaged and/or the rewiring layer; forming a bonding bump on the bonding pad and/or the rewiring layer; cutting the substrate to form chip units to be packaged, wherein each chip unit to be packaged comprises one or more chips to be packaged; and aligning and pressing the first surface of the chip unit to be packaged and the first surface of the functional substrate, wherein the welding pad of the chip to be packaged and the rewiring layer form electric connection through the welding bulge, and the functional area is positioned in a cavity defined by the cofferdam.

In one or more embodiments of the present invention, forming a bonding bump on the bonding pad and/or the rewiring layer includes: forming a first welding bulge on the welding pad of the first surface of each chip to be packaged; and forming a second bonding bump electrically connected to the rewiring layer on the rewiring layer; and after the first surface of the chip unit to be packaged and the first surface of the functional substrate are aligned and pressed, the first welding bulges are electrically connected with the second welding bulges.

In one or more embodiments of the invention, the welding projection may be located inside the cofferdam; or the welding projection may be located outside the cofferdam.

In one or more embodiments of the present invention, the method further comprises: and forming a metal bump on the rewiring layer after forming the rewiring layer on the first surface of the functional substrate.

In one or more embodiments of the present invention, the method further comprises: filling a plastic packaging material to carry out plastic packaging on the chip unit to be packaged, the substrate and the rewiring layer; and forming an external conductive column electrically connected with the metal bump of the rewiring layer on the plastic package material.

The utility model discloses an in one or more embodiments form on the plastic packaging material with the external conductive post that is connected of the metal lug electricity of rewiring layer includes: forming a through hole on the plastic packaging material, wherein the through hole exposes the metal bump of the rewiring layer; and forming an external conductive column in the through hole, wherein the external conductive column is electrically connected with the metal bump, and the external conductive column protrudes out of the surface of the plastic packaging material.

In one or more embodiments of the present invention, the method further comprises: and stripping the substrate to expose the metal bump of the rewiring layer.

In one or more embodiments of the present invention, a plurality of the second surfaces of the chips to be packaged and the first surface of the substrate are bonded, including: and forming a glue layer on the first surface of the substrate in a wafer-level mode, and bonding the second surface of the chip to be packaged with the first surface of the substrate through the glue layer.

In one or more embodiments of the present invention, the thickness of the glue layer is controlled by directly using the glue layer formed by the dry film; or controlling the forming thickness of the glue layer by a rotary coating mode.

The utility model also provides a chip packaging structure, include the functional substrate and treat the encapsulation chip.

The functional substrate is provided with a first surface, a rewiring layer is formed on the first surface, and a plurality of cofferdams are formed on the rewiring layer;

the chip to be packaged is provided with a first surface and a second surface which are oppositely arranged, a functional area and a welding pad coupled with the functional area are formed on the first surface, the first surface of the chip to be packaged and the first surface of the functional substrate are in counterpoint pressing, the welding pad is electrically connected with the rewiring layer, and the cofferdam is arranged around the periphery of the functional area of the chip to be packaged and is enclosed with the first surface of the chip to be packaged to form a cavity surrounding the functional area.

In one or more embodiments of the present invention, the chip package structure further includes a plastic package layer and an external conductive pillar.

The plastic packaging layer is positioned on one side of the functional substrate, which is provided with the chip to be packaged, and covers the chip to be packaged and the rewiring layer; the external conductive column is formed in the plastic package layer and electrically connected with the rewiring layer, and the external conductive column protrudes out of the surface of the plastic package layer.

In one or more embodiments of the invention, the welding projection is located inside the cofferdam.

In one or more embodiments of the invention, the welding projection is located outside the cofferdam.

In one or more embodiments of the present invention, the rewiring layer is an Al layer, a Cu layer, or a Ti layer.

In one or more embodiments of the present invention, the bonding pad and the rewiring layer are electrically connected by providing a bonding bump.

In one or more embodiments of the present invention, the material of the soldering bump may be gold, tin or tin alloy.

In one or more embodiments of the present invention, the first surface of the functional substrate is flipped with a plurality of the chips to be packaged.

Compared with the prior art, the utility model discloses embodiment's chip packaging method, it forms the carrier of waiting to encapsulate the chip through providing a temporary substrate, can plant the ball (form the welding arch) to many waiting to encapsulate the chip simultaneously, carries out the flip-chip bonding encapsulation with functional substrate again after the cutting, has promoted encapsulation efficiency greatly.

The utility model discloses embodiment's chip packaging method, its packaging technology is simple, need not too many encapsulation equipment, has reduced the encapsulation cost.

The utility model discloses embodiment's chip package structure, its simple structure, many treat that the encapsulation chip is invertedly adorned on functional substrate, and the top surface in cofferdam contacts with the first surface of treating the encapsulation chip for the functional area of treating the encapsulation chip lies in the cavity that the cofferdam formed completely, plays the effect in protect function district.

Drawings

Fig. 1 is a schematic flow chart of a chip packaging method according to an embodiment of the present invention;

fig. 2 to 18 are schematic structural diagrams of a chip packaging process according to an embodiment of the present invention;

fig. 19 is a schematic structural diagram of a chip package structure according to an embodiment of the present invention;

fig. 20 is a schematic structural diagram of a chip package structure according to another embodiment of the present invention.

Detailed Description

The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited by the following detailed description.

Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.

Just as background art says, among the prior art, in order to guarantee surface acoustic wave filter's encapsulation precision, adopt comparatively complicated packaging technology to encapsulate surface acoustic wave filter usually, and the encapsulation to surface acoustic wave filter is single encapsulation usually, and encapsulation efficiency is low, and the encapsulation cost is high. In order to solve the problem, the utility model provides a packaging method and packaging structure of chip can realize encapsulating simultaneously many surface acoustic wave filters, and packaging technology is simple, has improved encapsulation performance and packaging efficiency, has reduced the encapsulation cost.

As shown in fig. 1, an embodiment of the present invention provides a chip packaging method, including: providing a substrate s1; providing a chip s2 to be packaged, wherein the chip to be packaged has a first surface and a second surface which are oppositely arranged, and the first surface is formed with a functional area and a welding pad coupled with the functional area; bonding the second surfaces of the chips to be packaged with the surface of the substrate s3; providing a functional substrate s4, wherein the functional substrate has a first surface; forming a rewiring layer s5 on the first surface; forming a plurality of cofferdams s6 on the first surface of the chip to be packaged and/or the rewiring layer; forming a bonding bump s7 on the bonding pad and/or the rewiring layer; cutting the substrate to form chip units to be packaged s8, wherein each chip unit to be packaged comprises one or more chips to be packaged; and aligning and pressing the first surface of the chip unit to be packaged and the first surface of the functional substrate s9, forming electric connection between the welding pad of the chip to be packaged and the rewiring layer through the welding bulge, and positioning the functional area in a cavity defined by the cofferdam. And then, the substrate, the chip unit to be packaged and the rewiring layer can be subjected to plastic package by refilling a plastic package material, and an external conductive column electrically connected with the rewiring layer is formed on the plastic package material. Or, the substrate is directly stripped to expose the rewiring layer.

Fig. 2 to fig. 16 are schematic structural diagrams of a process according to an embodiment of the present invention, and the chip packaging method of the present invention is explained in detail with reference to fig. 2 to fig. 16.

First, referring to fig. 2 and fig. 3, fig. 2 is a schematic top view of a wafer 100, and fig. 3 is a cross-sectional view of a single chip 10 to be packaged at a-A1. Firstly, a wafer 100 is provided, the wafer 100 includes a plurality of chips 10 to be packaged arranged in rows and columns and dicing street regions 11 located between the chips 10 to be packaged, and the wafer 100 is diced along the dicing street regions 11 to form a plurality of chips 10 to be packaged. The wafer 100 is divided by a conventional cutting process, which is not described herein.

In this embodiment, the chip 10 to be packaged is a surface acoustic wave filter, the chip 10 to be packaged includes a first surface 10a and a second surface 10b, which are opposite to each other, and the first surface 10a has a functional region 101 and a pad 102 disposed around the functional region 101 and coupled to the functional region 101. The pads 102 serve as input and output terminals for connection of devices in the functional region 101 to external circuitry.

In the embodiment, the functional region 101 is located in the middle of the chip 10 to be packaged, and the pad 102 is located at the edge of the chip 10 to be packaged, and is disposed around the functional region 101. In other embodiments, the positions of the pads 102 and the functional regions 101 can also be flexibly adjusted according to the routing requirements.

Referring to fig. 4, a substrate 20 is provided. In this embodiment, the substrate 20 is an auxiliary temporary substrate that can be stripped in a subsequent process; the plastic package of the chip 10 to be packaged may be directly performed without removing the substrate 20. Therefore, in order to facilitate the peeling of the substrate 20, the substrate 20 may be made of glass, silicon, or ceramic, but is not limited thereto. The glass or silicon or ceramic substrate has a relatively smooth flat surface so that it can be more conveniently peeled off in a subsequent process. The substrate 20 has a size larger than that of the chip 10 to be packaged. The substrate 20 is formed with a dicing street area, and the substrate 20 may be subsequently diced along the dicing street area to form a plurality of chip units to be packaged.

Referring to fig. 5, the second surfaces 10b of the plurality of chips 10 to be packaged are bonded to the first surface 21 of the substrate 20. The specific implementation steps comprise: a glue layer is formed on the first surface 21 of the substrate 20 in a wafer-level manner, and the second surface 10b of the chip 10 to be packaged is bonded to the first surface 21 of the substrate 20 through the glue layer. In order to control the thickness of the glue layer, the glue layer can be directly a dry film; alternatively, the thickness of the glue forming the glue layer can be controlled by spin coating. The glue layer can be made of a UV adhesive releasing tape or a pyrolytic adhesive tape, the UV adhesive releasing tape or the pyrolytic adhesive tape can lose viscosity in a UV light irradiation mode, and the substrate 20 can be conveniently removed in the follow-up process if the substrate 20 needs to be removed.

Referring to fig. 6, first bonding bumps 103 are formed on the bonding pads 102 of the first surface 10a of each chip 10 to be packaged. The first bonding bump 103 forms an electrical connection with the pad 102, and the first bonding bump 103 is used to form an electrical connection with a component in a subsequent process. The shape of the first bonding bump 103 is spherical or elliptical, and the forming process of the first bonding bump 103 is a ball-mounting process. The material of the first bonding bump 103 may be gold, tin or tin alloy, and the tin alloy may be tin silver, tin lead, tin silver copper, tin silver zinc, tin bismuth indium, tin gold, tin copper, tin zinc indium, tin silver antimony, or the like.

Referring to fig. 7, the substrate 20 to which a plurality of chips 10 to be packaged are attached is cut along a dicing street area thereof to form chip units to be packaged, each of which includes one or several chips 10 to be packaged.

Referring to fig. 8, a functional substrate 30 is provided, the functional substrate 30 may be a transparent substrate, and the material of the transparent substrate is preferably glass, but not limited thereto. The functional substrate 30 has a size larger than that of the chip unit to be packaged. The functional substrate 30 has a first surface 31.

Referring to fig. 9, a rewiring layer 40 is formed on the first surface 31 of the functional substrate 30. In one embodiment, the redistribution layer 40 may be a metal layer, the metal layer includes an Al layer, a Cu layer, or a Ti layer, the redistribution layer 40 may be formed after the metal layer is patterned, and an electrical connection is formed between the redistribution layer 40 and the pad 102 of the chip 10 to be packaged in a subsequent process. There are various methods or processes for forming redistribution layer 40, and since this process is not the focus and innovation of the present application, it is sufficient to adopt the prior art without specifically describing it. The redistribution layer 40 may have metal bumps formed thereon, and the metal bumps are exposed for electrical connection with an external conductive pillar or an external circuit board.

Referring to fig. 10 and 11, fig. 10 is a schematic top view of the functional substrate 30 provided with the dam 41 and the second bonding bump 42, and fig. 11 is a cross-sectional view of the functional substrate 30 at B-B1. A plurality of banks 41 and second bonding bumps 42 are formed on the rewiring layer 40. The dam 41 is a ring-shaped hollow structure, wherein the size of the cavity is larger than or equal to the size of the functional region 101 on the chip 10 to be packaged. The material of the bank 41 may be a photosensitive paste, which may be an epoxy paste, a polyimide paste, a benzocyclobutene paste, or a polybenzoxazole paste, and in this embodiment, the material of the bank 41 is preferably an epoxy resin. The specific process of forming patterned bank 41 is as follows: an epoxy resin layer covering the redistribution layer 40 on the surface of the functional substrate 30 is formed, and the epoxy resin layer is exposed and developed to form the patterned bank 41 of the present embodiment. In other embodiments of the present invention, the material of the cofferdam 41 may also be a curing glue, and according to the material characteristics of the photosensitive glue or the curing glue, the photosensitive glue or the curing glue may be formed on the redistribution layer 40 on the surface of the functional substrate 30 through one of the screen printing process, the photolithography process or the glue dispensing process, and then the patterned cofferdam 41 is formed through the photolithography process or the curing process.

A second solder bump 42 is formed on the periphery of the dam 41 for making electrical connection with the first solder bump 103 on the surface of the chip 10 to be packaged. The shape of the second bonding bump 42 is also spherical or elliptical, and the forming process of the second bonding bump 42 is a ball-planting process. The material of the second bonding bump 42 may be gold, tin or tin alloy, and the tin alloy may be tin silver, tin lead, tin silver copper, tin silver zinc, tin bismuth indium, tin gold, tin copper, tin zinc indium, tin silver antimony, or the like.

In other embodiments, as shown in fig. 12 to 13, a second solder bump 42 may also be formed inside the dam 41, also for making electrical connection with the first solder bump 103 on the surface of the chip 10 to be packaged.

Referring to fig. 14, the first surface 10a of the chip unit to be packaged and the first surface 31 of the functional substrate 30 are aligned and bonded, the pad 102 of the chip unit to be packaged and the redistribution layer 40 are electrically connected through the first bonding bump 103 and the second bonding bump 42, and the functional region 101 is located in a cavity surrounded by the dam 41. The bonding process between the first bonding bump 103 and the second bonding bump 42 may employ eutectic bonding, ultrasonic thermocompression, thermocompression bonding, ultrasonic pressure bonding, or the like.

In the present embodiment, the first bonding bump 103 is formed on the bonding pad 102 of the chip 10 to be packaged and the second bonding bump 42 is formed on the redistribution layer 40 of the functional substrate 30, and the total height of the first bonding bump 103 and the second bonding bump 42 is made to be consistent with the height of the dam 41, so that when the chip unit to be packaged is flip-chip mounted on the functional substrate 30, the dam 41 just abuts against the surfaces of the chip 10 to be packaged and the functional substrate 30, and forms a cavity for protecting the functional region 101.

In other embodiments, a solder bump may be formed only on the pad 102 of the chip 10 to be packaged or only on the redistribution layer 40 of the functional substrate 30, and the height of the solder bump is consistent with the height of the dam 41, and also when the chip unit to be packaged is flip-chip mounted on the functional substrate 30, the dam 41 just abuts against the surfaces of the chip 10 to be packaged and the functional substrate 30, and forms a cavity for protecting the functional region 101.

In yet another embodiment, the dam 41 may also be formed on the first surface 10a of the chip 10 to be packaged.

Referring to fig. 15, a plastic sealing material is filled to perform plastic sealing on the surfaces of the chip 10 to be sealed, the substrate 20, and the functional substrate 30 provided with the rewiring layer 40, and then the plastic sealing material is cured to form a plastic sealing layer 50. The molding compound is a resin or solder resist material, such as epoxy resin or acrylic resin.

The function of forming the plastic package layer 50 is: on one hand, the formed plastic package layer 50 plays a role in protecting the chip 10 to be packaged, improves the waterproof performance and forms a waterproof advantage; on the other hand, the plastic package layer 50 plays a role of supporting the chip 10 to be packaged, so that the chip 10 to be packaged is fixed to facilitate subsequent circuit connection, and after the packaging is completed, the chip is not easy to damage. The plastic package layer 50 is formed by a plastic package process (molding) which uses a transfer method or a press-fitting method.

In the above embodiment, the substrates 20 are directly molded together. In other embodiments, the substrate 20 may be peeled off first, and then the chip 10 to be packaged, the functional substrate 30, and the rewiring layer 40 may be molded.

Referring to fig. 16, a via 51 is formed in the molding layer 50, and the bottom of the via 51 exposes the surface of the redistribution layer 40 (especially, exposes a metal bump on the redistribution layer 40, not shown). The purpose of forming the through hole 51 is to form an external conductive pillar 60 electrically connected to the metal bump in the through hole 51, and electrically connect the redistribution layer 40 to an external circuit through the external conductive pillar 60, so as to electrically connect the chip 10 to be packaged and the external circuit, and enable the packaged structure to be put into practical use.

The via hole 51 is formed using a laser drilling process or an etching process. As an embodiment, the process of forming the via hole 51 using an etching process includes: forming a patterned mask layer on the surface of the plastic packaging layer 50, wherein a groove is formed in the patterned mask layer, and the position and the width of the groove correspond to the position and the width of a through hole 51 to be formed subsequently; etching the plastic packaging layer 50 by taking the patterned mask layer as a mask until the surface of the rewiring layer is exposed, and forming a through hole 51 exposing the surface of the rewiring layer in the plastic packaging layer 50; and removing the patterned mask layer.

In this embodiment, the through hole 51 is formed in the plastic package layer 50, so that the chip 10 to be packaged is electrically connected to an external circuit, adverse effects caused by the formation of the through hole in the chip 10 to be packaged are avoided, and the performance of a subsequently formed package structure is improved.

Referring to fig. 17, the external conductive pillars 60 filling the through holes 51 are formed, and the tops of the external conductive pillars 60 are higher than the surface of the molding compound layer 50, so as to form a completely packaged chip package structure.

The chip 10 to be packaged is electrically connected to an external circuit through the external conductive column 60, so that the chip 10 to be packaged normally operates. The top surface of the external conductive post 60 is arc-shaped. The external conductive column 60 is made of conductive metal and conductive alloy, including gold, tin or tin alloy, and the tin alloy may be tin silver, tin lead, tin silver copper, tin silver zinc, tin bismuth indium, tin gold, tin copper, tin zinc indium or tin silver antimony, etc. The external conductive column 60 is formed in the plastic packaging layer 50, the top of the external conductive column 60 is slightly higher than the surface of the plastic packaging layer 50, so that the chip 10 to be packaged can be electrically connected with an external circuit, and the top of the external conductive column 60 is slightly higher than the surface of the plastic packaging layer 50, so that the overall thickness of a packaging structure formed subsequently can be reduced, and the packaging integration level can be improved.

In the above embodiment, the external conductive pillars 60 are formed in the through holes 51 by forming the molding layer 50, and then forming the through holes 51 on the molding layer 50.

In other embodiments, the external conductive pillars 60 may be formed at corresponding positions on the redistribution layer 40 of the functional substrate 30, and then the chip 10 to be packaged is flipped and filled with the plastic package material, so that the external conductive pillars 60 are not immersed in the plastic package material, and the chip 10 to be packaged can be electrically connected to other external components through the external conductive pillars 60.

Referring to fig. 18, in another embodiment, after the chip unit to be packaged is flip-chip mounted on the functional substrate 30, the substrate 20 is directly peeled off without filling the plastic package material for plastic package, and the metal bumps on the redistribution layer 40 are exposed, thereby forming a completely packaged chip package structure.

Referring to fig. 19, the present invention further provides a chip package structure, which includes a functional substrate 30 and a chip 10 to be packaged.

The functional substrate 30 has a first surface 31, a redistribution layer 40 formed on the first surface 31, and a plurality of dam 41 and metal bumps 43 electrically connectable to the outside formed on the redistribution layer 40.

The chip 10 to be packaged has a first surface 10a and a second surface 10b which are oppositely arranged, the first surface 10a is formed with a functional region 101 and a bonding pad coupled with the functional region 101, the first surface 10a of the chip 10 to be packaged is aligned and pressed with the first surface 31 of the functional substrate 30, the bonding pad 102 is electrically connected with the rewiring layer 40, the rewiring layer 40 exposes the functional region 101 of the chip 10 to be packaged, and the cofferdam 41 is arranged around the periphery of the functional region 101 of the chip 10 to be packaged and is enclosed with the first surface 10a of the chip 10 to be packaged to form a cavity surrounding the functional region 101.

Referring to fig. 20, the present invention further provides a chip package structure, which includes a functional substrate 30, a chip 10 to be packaged, a plastic package layer 50, and an external conductive pillar 60.

The functional substrate 30 has a first surface 31, a redistribution layer 40 is formed on the first surface 31, and a plurality of dams 41 and metal bumps 43 electrically connectable to the outside are formed on the redistribution layer 40;

The plastic package layer 50 is located on one side of the functional substrate 30 where the chip 10 to be packaged is disposed, and covers the chip 10 to be packaged and the redistribution layer 40.

The external conductive pillars 60 are formed in the plastic package layer 50 and electrically connected to the metal bumps 43 on the redistribution layer 40, and the external conductive pillars 60 are disposed to protrude from the surface of the plastic package layer 50. The material of the external conductive post 60 may be gold, tin or tin alloy.

In one embodiment, a first bonding bump 103 is formed on a bonding pad 102 of the chip 10 to be packaged, a second bonding bump 42 is formed on a redistribution layer 40 of the functional substrate 30, and the bonding pad 102 of the chip 10 to be packaged and the redistribution layer 40 are electrically connected through the first bonding bump 103 and the second bonding bump 42.

In other embodiments, the bonding bumps may be formed only on the pads 102 of the chip 10 to be packaged or the re-wiring layer 40 of the functional substrate 30.

Further, the first surface 31 of the functional substrate 30 is flip-chip mounted with a plurality of chips 10 to be packaged.

The various aspects, embodiments, features and examples of the present invention should be considered illustrative in all respects and not intended to be limiting, the scope of the invention being defined only by the claims. Other embodiments, modifications, and uses will be apparent to those skilled in the art without departing from the spirit and scope of the claimed invention.

The use of headings and chapters in this application is not meant to limit the invention; each section may apply to any aspect, embodiment, or feature of the present invention.

Throughout this application, where a composition is described as having, containing, or including specific components, or where a process is described as having, containing, or including specific process steps, it is contemplated that the compositions taught by the present invention also consist essentially of, or consist of, the recited components, and that the processes taught by the present invention also consist essentially of, or consist of, the recited process steps.

In this application, where an element or component is referred to as being included in and/or selected from a list of recited elements or components, it is understood that the element or component can be any one of the recited elements or components and can be selected from a group consisting of two or more of the recited elements or components. Moreover, it should be understood that elements and/or features of a composition, apparatus or method described herein may be combined in various ways, whether explicitly described or implicitly described herein, without departing from the spirit and scope of the present teachings.

Unless specifically stated otherwise, use of the terms "comprising," "having," and the like, are generally to be understood as being open-ended and not limiting.

The use of the singular herein includes the plural (and vice versa) unless specifically stated otherwise. Furthermore, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. In addition, where the term "about" is used before a quantity, the teachings of the present invention also include the particular quantity itself, unless specifically stated otherwise.

It should be understood that the order of steps or the order in which particular actions are performed is not critical, so long as the teachings of the present invention remain operable. Further, two or more steps or actions may be performed simultaneously.

It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding of the present invention, while eliminating, for purposes of clarity, other elements. However, those skilled in the art will recognize that these and other elements may be desirable. However, because such elements are well known in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements is not provided herein. It should be understood that the figures are presented for illustrative purposes and not as construction diagrams. The omission of details and modifications or alternative embodiments is within the scope of one skilled in the art.

It is to be understood that in certain aspects of the present invention, a single component may be replaced by multiple components and multiple components may be replaced by a single component to provide an element or structure or to perform a given function or functions. Such substitutions are considered to be within the scope of the present invention, except where such substitution would not operate to practice a particular embodiment of the invention.

While the invention has been described with reference to illustrative embodiments, it will be understood by those skilled in the art that various other changes, omissions and/or additions may be made and substantial equivalents may be substituted for elements thereof without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims. Moreover, unless specifically stated any use of the terms first, second, etc. do not denote any order or importance, but rather the terms first, second, etc. are used to distinguish one element from another.

Claims

1. A chip package structure, comprising:

the chip to be packaged comprises a first surface and a second surface which are oppositely arranged, a functional area and a welding pad coupled with the functional area are formed on the first surface, the first surface of the chip to be packaged and the first surface of the functional substrate are in counterpoint pressing, the welding pad is electrically connected with the rewiring layer, and the cofferdam is arranged on the periphery of the functional area of the chip to be packaged in a surrounding mode and is enclosed with the first surface of the chip to be packaged to form a cavity surrounding the functional area.

2. The chip package structure according to claim 1, wherein the redistribution layer has metal bumps formed thereon, the metal bumps being distributed around the periphery of the dam.

3. The chip packaging structure of claim 2, further comprising:

the plastic packaging layer is positioned on one side of the functional substrate, which is provided with the chip to be packaged, and covers the chip to be packaged and the rewiring layer;

and the external conductive column is formed in the plastic package layer and is electrically connected with the metal bump of the rewiring layer, and the external conductive column is arranged to protrude out of the surface of the plastic package layer.

4. The chip package structure of claim 1, wherein the first surface of the functional substrate is flip-chip mounted with a plurality of chips to be packaged.

5. The chip package structure of claim 1, wherein the bonding pads and the redistribution layer are electrically connected by providing bonding bumps.

6. The chip packaging structure according to claim 5, wherein a first bonding bump is formed on the bonding pad of the first surface of the chip to be packaged;

and a second welding bump electrically connected with the rewiring layer is formed on the rewiring layer, and the first welding bump is electrically connected with the second welding bump.

7. The chip package structure according to claim 5, wherein the solder bump is located inside the dam.

8. The chip package structure of claim 5, wherein the solder bump is located outside the dam.

9. The chip package structure according to claim 5, wherein the material of the solder bump is gold, tin or tin alloy.

10. The chip packaging structure of claim 1, wherein the rewiring layer is an Al layer or a Cu layer or a Ti layer.