CN114999939A - Chip packaging method and packaging structure - Google Patents

Chip packaging method and packaging structure Download PDF

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Publication number
CN114999939A
CN114999939A CN202210644287.6A CN202210644287A CN114999939A CN 114999939 A CN114999939 A CN 114999939A CN 202210644287 A CN202210644287 A CN 202210644287A CN 114999939 A CN114999939 A CN 114999939A
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chip
packaged
transparent substrate
forming
packaging
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CN202210644287.6A
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Chinese (zh)
Inventor
谢国梁
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China Wafer Level CSP Co Ltd
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China Wafer Level CSP Co Ltd
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Priority to CN202210644287.6A priority Critical patent/CN114999939A/en
Publication of CN114999939A publication Critical patent/CN114999939A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/111—Manufacture and pre-treatment of the bump connector preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body

Abstract

The invention discloses a chip packaging method and a chip packaging structure, wherein the chip packaging method comprises the following steps: providing a transparent substrate, and forming a rewiring layer on the transparent substrate; providing a chip to be packaged, wherein an induction area and a welding pad coupled with the induction area are formed on the first surface of the chip to be packaged; forming a welding bump on the welding pad or the rewiring layer; forming a cofferdam on one side of the transparent substrate or the first surface of the chip to be packaged; aligning and pressing the first surface of the chip to be packaged and the surface of the transparent substrate, wherein the induction area is positioned in a space defined by the cofferdam, and the salient points are welded, and the rewiring layer and the welding pad are electrically connected; filling plastic packaging materials to carry out plastic packaging on the chip to be packaged and the transparent substrate; and forming an external conductive column electrically connected with the rewiring layer, wherein the external conductive column protrudes out of the plastic packaging material. The chip packaging method can form the sealed cavity which effectively protects the chip sensing area in the packaging process, improves the packaging performance and the packaging efficiency and reduces the packaging cost.

Description

Chip packaging method and packaging structure
Technical Field
The present invention relates to semiconductor packaging technology, and more particularly, to a chip packaging method and structure.
Background
The surface acoustic wave filter is an important part of a mobile communication terminal product, and the raw material is made of piezoelectric crystals. The surface acoustic wave filter completes the filtering characteristic by utilizing the excitation, the transmission and the reception of the surface acoustic waves on the piezoelectric material. With the miniaturization and low cost of the mobile terminal, the requirement for packaging the surface acoustic wave filter is also increased correspondingly. Meanwhile, due to the performance and design function requirements of the surface acoustic wave filter product, the functional area of the filter chip is required to be ensured not to contact any substance, namely, the cavity structure design.
Based on the requirement of the surface acoustic wave filter on the cavity structure in the package structure, the prior art generally covers the cover plate above the surface acoustic wave filter chip functional region to construct a cavity structure, and the flip-chip technology is adopted or the cover plate is provided with a through hole to realize the electrical connection between the solder ball and the chip pad. However, the above-mentioned package structure and method have certain requirements for the thickness and material of the cover plate, the package cost is high, and the package efficiency needs to be improved.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a chip packaging method and a chip packaging structure, which can form a sealed cavity for effectively protecting a chip sensing area in a packaging process, improve the packaging performance and packaging efficiency and reduce the packaging cost.
In order to achieve the above object, an embodiment of the present invention provides a chip packaging method, including:
providing a transparent substrate, and forming a rewiring layer on the transparent substrate;
providing a chip to be packaged, wherein the chip to be packaged comprises a first surface and a second surface which are opposite, and an induction area and a welding pad coupled with the induction area are formed on the first surface;
forming a welding salient point on the welding pad or the rewiring layer;
forming a cofferdam on one side of the transparent substrate on which the rewiring layer is formed or the first surface of the chip to be packaged;
aligning and pressing the first surface of the chip to be packaged and the surface of the transparent substrate with the rewiring layer, wherein the induction area is positioned in a space surrounded by the cofferdam, and the welding salient points, the rewiring layer and the welding pads are electrically connected;
filling a plastic packaging material to carry out plastic packaging on the chip to be packaged and the transparent substrate;
and forming an external conductive column electrically connected with the rewiring layer, wherein the external conductive column protrudes out of the plastic packaging material.
In one or more embodiments of the present invention, a plurality of the banks are formed on the transparent substrate, and a scribe line region is formed between adjacent banks;
aligning, pressing and electrically connecting a plurality of chips to be packaged and the transparent substrate, wherein each chip to be packaged corresponds to one cofferdam;
filling a plastic packaging material to carry out integral plastic packaging on the chips to be packaged and the transparent substrate;
forming an external conductive column electrically connected with each chip to be packaged on the plastic packaging material;
and cutting the transparent substrate and the plastic package material along the cutting path area to form a single chip packaging structure.
In one or more embodiments of the present invention, a cofferdam is formed on the first surface of the chip to be packaged, and the cofferdam is disposed to surround the sensing area;
aligning and pressing a plurality of chips to be packaged on the same transparent substrate to form electric connection;
filling a plastic packaging material to carry out integral plastic packaging on the chips to be packaged and the transparent substrate;
forming an external conductive column electrically connected with each chip to be packaged on the plastic packaging material;
and cutting the transparent substrate to form a single chip packaging structure.
In one or more embodiments of the present invention, the solder bump on the pad is located at the periphery of the dam.
In one or more embodiments of the present invention, when the solder bump, the redistribution layer, and the pad are in contact and form an electrical connection, the top surface of the dam is in sealing contact with the first surface of the chip to be packaged and/or the transparent substrate.
In one or more embodiments of the present invention, forming an external conductive pillar electrically connected to the redistribution layer includes:
forming a through hole on the plastic packaging material, wherein the through hole exposes the rewiring layer;
and forming an external conductive column in the through hole, wherein the external conductive column is protruded on the surface of the plastic packaging material.
In one or more embodiments of the present invention, forming a re-wiring layer on a transparent substrate includes:
adhering a metal layer on the surface of the transparent substrate;
and patterning the metal layer to form a rewiring layer.
In one or more embodiments of the present invention, a material of the transparent substrate includes glass.
In one or more embodiments of the present invention, a material of the dam includes an epoxy resin.
The invention also provides a chip packaging structure packaged by the chip packaging method.
Compared with the prior art, the chip packaging method provided by the embodiment of the invention has the advantages that the cofferdam is formed on the transparent substrate or the chip to be packaged, so that when the chip to be packaged is inversely arranged on the transparent substrate, the chip to be packaged, the transparent substrate and the cofferdam can form the sealed cavity surrounding the induction area, and the effect of effectively protecting the induction area of the chip to be packaged is achieved.
The chip packaging method of the embodiment of the invention can be used for simultaneously inversely packaging a plurality of chips to be packaged on the transparent substrate and packaging, thereby greatly improving the packaging performance and the packaging efficiency.
According to the chip packaging method provided by the embodiment of the invention, the plastic packaging layer formed by the plastic packaging material surrounds the chip to be packaged and the surface of the transparent substrate, so that the cavity where the sensing area is located is of a closed structure, and the chip packaging method has the advantage of water resistance.
Drawings
FIG. 1 is a flow chart illustrating a chip packaging method according to an embodiment of the invention;
FIGS. 2-11 are schematic structural diagrams illustrating a chip packaging process according to an embodiment of the invention;
fig. 12 is a schematic structural diagram of a chip package structure according to an embodiment of the invention.
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
As background art, based on the requirement of the saw filter for the cavity structure in the package structure, in the prior art, a cover plate is usually covered above the saw filter chip functional region to construct a cavity structure, and an electrical connection between a solder ball and a chip pad is realized by using a flip chip technique or by providing a through hole on the cover plate. However, the above-mentioned package structure and method have certain requirements for the thickness and material of the cover plate, the package cost is high, and the package efficiency needs to be improved. In order to solve the above problems, the present invention provides a chip packaging method, which can form a sealed cavity for effectively protecting a chip sensing region during a packaging process, thereby improving packaging performance and packaging efficiency, and reducing packaging cost.
As shown in fig. 1, an embodiment of the invention provides a chip packaging method, which includes providing a transparent substrate and forming a redistribution layer s1 on the transparent substrate; providing a chip to be packaged s2, wherein the chip to be packaged includes a first surface and a second surface opposite to the first surface, and the first surface is formed with an induction area and a welding pad coupled with the induction area; forming a bonding bump s3 on the pad or the rewiring layer; forming a cofferdam s4 on one side of the transparent substrate where the rewiring layer is formed or the first surface of the chip to be packaged; the first surface of the chip to be packaged and the surface of the transparent substrate forming the rewiring layer are pressed in an opposite position, and the welding salient points, the rewiring layer and the welding pads are electrically connected s5, wherein the induction area is located in a space defined by the cofferdam; filling a plastic packaging material to carry out plastic packaging on the second surface of the chip to be packaged, the rewiring layer and the transparent substrate s 6; and forming an external conductive column s7 electrically connected with the redistribution layer, wherein the external conductive column protrudes out of the plastic packaging material.
Fig. 2 to 12 are schematic structural diagrams of processes according to an embodiment of the present invention, and the chip packaging method of the present invention is described in detail below with reference to fig. 2 to 12.
Referring to fig. 2 and fig. 3, fig. 2 is a schematic top view of the wafer 100, and fig. 3 is a cross-sectional view of a single chip 10 to be packaged at a-a 1. Firstly, a wafer 100 is provided, the wafer 100 includes a plurality of chips 10 to be packaged arranged in rows and columns and dicing street regions 11 located between the chips 10 to be packaged, and the wafer 100 is diced along the dicing street regions 11 to form a plurality of chips 10 to be packaged. The wafer 100 is divided by a conventional cutting process, which is not described herein.
In this embodiment, the chip 10 to be packaged is a surface acoustic wave filter, the chip 10 to be packaged includes a first surface 10a and a second surface 10b, which are opposite to each other, and the first surface 10a has a sensing region 101 and a pad 102 disposed around the sensing region 101 and coupled to the sensing region 101. Pads 102 serve as input and output terminals for devices within sensing region 101 to connect to external circuitry.
In the embodiment, the sensing region 101 is located in the middle of the chip 10 to be packaged, and the pad 102 is located at the edge of the chip 10 to be packaged, and is disposed around the sensing region 101. In other embodiments, the positions of the pads 102 and the sensing regions 101 can be flexibly adjusted according to the wiring requirements.
Referring to fig. 4, a solder bump 103 is formed on a pad 102. The solder bumps 103 are used to make electrical connections with other components in subsequent processes. The shape of the solder bump 103 is a sphere or a cylinder, but not limited thereto. The forming process of the welding bump 103 is a ball planting process. The material of the solder bump 103 may be gold, tin or tin alloy, and the tin alloy may be tin silver, tin lead, tin silver copper, tin silver zinc, tin bismuth indium, tin gold, tin copper, tin zinc indium, tin silver antimony, or the like.
Referring to fig. 5, a transparent substrate 20 is provided. In this embodiment, the material of the transparent substrate is preferably glass, but is not limited thereto. The size of the transparent substrate 20 is larger than the size of the chip 10 to be packaged.
A rewiring layer (not shown) is formed on one surface of the transparent substrate 20. In one embodiment, the redistribution layer may be a metal layer, the metal layer includes an Al layer, a Cu layer, or a Ti layer, and the redistribution layer may be formed after patterning the metal layer, and forms an electrical connection with the pad 102 of the chip 10 to be packaged in a subsequent process. There are various methods or processes for forming the rewiring layer, and since the processes are not the focus and innovation of the present application, the present application does not specifically describe them, and the prior art is adopted.
Referring to fig. 6 and 7, fig. 6 is a schematic top view of the transparent substrate 20, and fig. 7 is a cross-sectional view of the transparent substrate 20 at B-B1. A bank 21 is formed on the rewiring layer of the transparent substrate 20. The dam 21 is an annular hollow structure, wherein the size of the cavity is larger than or equal to the size of the sensing region 101 on the chip 10 to be packaged, but smaller than the size of the pad 102 around the sensing region 101 or the space surrounded by the sensing region surrounded by the solder bump 103 on the pad 102. The material of the cofferdam 21 may be a photosensitive glue, and the photosensitive glue may be an epoxy glue, a polyimide glue, a benzocyclobutene glue, a polybenzoxazole glue, or the like, and in this embodiment, the material of the cofferdam 21 is preferably an epoxy resin. The specific process of forming the patterned bank 21 is: an epoxy resin layer is formed to cover the rewiring layer on the surface of the transparent substrate 20, and the epoxy resin layer is subjected to exposure and development processes to form the patterned banks 21 of the present embodiment. In other embodiments of the present invention, the material of the dam 21 may also be a curing adhesive, and according to the material characteristics of the photosensitive adhesive or the curing adhesive, the photosensitive adhesive or the curing adhesive may be formed on the redistribution layer on the surface of the transparent substrate 20 through one of a screen printing process, a photolithography process, or a dispensing process, and then the patterned dam 21 is formed through the photolithography process or the curing process.
In the embodiment, a plurality of cofferdams 21 are formed on the transparent substrate 20, the cofferdams 21 are distributed on the surface of the transparent substrate 20 in an array, a cut channel to be cut is formed between adjacent cofferdams 21, and a plurality of chips 10 to be packaged can be packaged on the transparent substrate 20 at the same time. After the subsequent packaging is completed, the transparent substrate 20 can be cut along the channel to be cut as required to form a single chip packaging structure.
In other embodiments, only one dam 21 may be formed on the transparent substrate 20 to package a single chip 10 to be packaged.
In the present embodiment, the dam 21 is formed on the surface of the transparent substrate 20, in other embodiments, the dam 21 may also be formed on the first surface 10a of the chip 10 to be packaged and disposed to surround the sensing region 101, and the solder bump 103 is disposed on the periphery of the dam 21, so as to facilitate forming an electrical connection between the solder bump 103 and the redistribution layer in the subsequent process. During packaging, the chips 10 to be packaged, which form the dam 21, may be flip-chip mounted on the same transparent substrate 20, and then the chips 10 to be packaged may be integrally packaged. After the subsequent packaging is completed, the transparent substrate 20 may also be cut as needed to form a single chip package structure.
Referring to fig. 8, the first surface 10a of the chip 10 to be packaged and the redistribution layer of the transparent substrate 20 are aligned and bonded, and the solder bumps 103 on the chip 10 to be packaged and the redistribution layer are soldered and bonded to form an electrical connection therebetween. Wherein the solder bumps 103 are located at the periphery of the dam 21, and the dam 21 and the first surface 10a enclose to form a sealed cavity 22 surrounding the sensing region 101. The sensing region 101 of the chip 10 to be packaged is located within the sealed cavity 22. The welding bonding process can adopt eutectic bonding, ultrasonic hot pressing, hot pressing welding, ultrasonic pressure welding and the like.
In the present embodiment, the height of the dam 21 may be controlled such that the top surface of the dam 21 is in sealing contact with the first surface 10a of the chip 10 to be packaged to form the sealed cavity 22 after the chip 10 to be packaged and the transparent substrate 20 are pressed and electrically connected in alignment; alternatively, a sealing adhesive layer may be formed on the first surface of the chip 10 to be packaged and around the sensing region, so that after the chip 10 to be packaged and the transparent substrate 20 are pressed and electrically connected in an aligned manner, the top surface of the dam 21 is in sealing contact with the sealing adhesive layer on the chip 10 to be packaged, thereby forming the sealed cavity 22.
In the above embodiment, the solder bump 103 is formed on the pad 102 of the chip 10 to be packaged, and then electrically connected to the redistribution layer of the substrate 20; in other embodiments, the solder bumps 103 may be formed on the rewiring layer first, and then electrically connected to the pads 102 of the chip 10 to be packaged during subsequent packaging.
Referring to fig. 9, a plastic packaging material is filled to perform plastic packaging on the second surface 10b of the chip 10 to be packaged, the two side surfaces of the chip 10 to be packaged, and the surface of the transparent substrate 20 provided with the rewiring layer, and then the plastic packaging material is cured to form a plastic packaging layer 30. The molding compound is a resin or solder resist material, such as epoxy resin or acrylic resin.
The function of forming the plastic package layer 30 is: on one hand, the formed plastic package layer 30 plays a role in protecting the chip 10 to be packaged, ensures that a cavity where the sensing area of the chip 10 to be packaged is located is a sealed cavity, prevents the performance failure of the chip 10 to be packaged caused by the influence of an external environment, prevents moisture from invading from the outside, is electrically insulated from the outside, improves the waterproof performance, and forms a waterproof advantage; on the other hand, the plastic package layer 30 plays a role of supporting the chip 10 to be packaged, so that the chip 10 to be packaged is fixed to facilitate subsequent circuit connection, and after the packaging is completed, the chip is not easy to damage.
And forming the plastic packaging layer 30 by adopting a plastic packaging process (molding), wherein the plastic packaging process adopts a transfer mode or a pressing mode, and the top surface of the plastic packaging layer 30 is flush with the second surface 10b of the chip 10 to be packaged or higher than the second surface 10b of the chip 10 to be packaged.
In this embodiment, the molding compound may partially or completely cover the chip 10 to be packaged, surround the side surface of the chip 10 to be packaged, the redistribution layer, and the surface of one side of the transparent substrate 20, and then be directly cured to form the molding layer 30.
Referring to fig. 10, a through hole 31 is formed in the molding layer 30, and a bottom of the through hole 31 exposes a surface of the redistribution layer.
Specifically, the through hole 31 formed in the present embodiment exposes the surface of the redistribution layer. The purpose of forming the through hole 31 is to form an external conductive pillar 40 in the through hole 31, and electrically connect the redistribution layer with an external circuit through the external conductive pillar 40, so as to electrically connect the chip 10 to be packaged with the external circuit, and make the package structure formed after packaging capable of being put into practical application.
The through-hole 31 is formed using a laser drilling process or an etching process. As an embodiment, the process of forming the through hole 31 using an etching process includes: forming a patterned mask layer on the surface of the plastic packaging layer 30, wherein a groove is formed in the patterned mask layer, and the position and the width of the groove correspond to the position and the width of a through hole 31 to be formed subsequently; etching the plastic packaging layer 30 by taking the patterned mask layer as a mask until the surface of the redistribution layer is exposed, and forming a through hole 31 exposing the surface of the redistribution layer in the plastic packaging layer 30; and removing the patterned mask layer.
In this embodiment, the purpose of electrically connecting the chip 10 to be packaged and the external circuit is achieved by forming the through hole 31 in the plastic package layer 30, so that adverse effects caused by forming the through hole in the chip 10 to be packaged are avoided, and the performance of a subsequently formed packaging structure is improved.
In the process of forming the through hole 31, due to the existence of the cofferdam 21 on the transparent substrate 20, the sensing area 101 of the chip 10 to be packaged is located in a sealed cavity, so that the process of forming the through hole 31 is prevented from damaging the sensing area 101 of the chip 10 to be packaged or introducing impurities into the sensing area of the chip 10 to be packaged to influence the functions of the chip.
Referring to fig. 11, the external conductive pillars 40 are formed to fill the through holes 31, and the tops of the external conductive pillars 40 are higher than the surface of the molding layer 30.
The chip 10 to be packaged is electrically connected to an external circuit through the external conductive posts 40, so that the chip 10 to be packaged normally works. The top surface of the external conductive post 40 is arc-shaped. The external conductive column 40 is made of conductive metal and conductive alloy, including gold, tin or tin alloy, and the tin alloy may be tin silver, tin lead, tin silver copper, tin silver zinc, tin bismuth indium, tin gold, tin copper, tin zinc indium or tin silver antimony, etc. The external conductive column 40 is formed in the plastic packaging layer 30, the top of the external conductive column 40 is slightly higher than the surface of the plastic packaging layer 30, so that the chip 10 to be packaged can be electrically connected with an external circuit, and the top of the external conductive column 40 is slightly higher than the surface of the plastic packaging layer 30, so that the overall thickness of a packaging structure formed subsequently can be further reduced, and the packaging integration level can be improved.
In the above embodiment, the external conductive pillars 40 are formed in the through holes 31 by forming the molding layer 30 first, and then forming the through holes 31 on the molding layer 30.
In other embodiments, the external conductive pillars 40 may be formed at corresponding positions on the redistribution layer of the transparent substrate 20, and then the chip 10 to be packaged is flipped and filled with the plastic package material, so that the external conductive pillars 40 are not immersed in the plastic package material, and the chip 10 to be packaged can be electrically connected to other external components through the external conductive pillars 40.
As shown in fig. 12, the transparent substrate 20 is cut along the scribe line region to form a single chip package structure.
The invention also provides a chip packaging structure which is packaged by the chip packaging method.
Compared with the prior art, the chip packaging method provided by the embodiment of the invention has the advantages that the cofferdam is formed on the transparent substrate or the chip to be packaged, so that when the chip to be packaged is inversely arranged on the transparent substrate, the chip to be packaged, the transparent substrate and the cofferdam can form the sealed cavity surrounding the induction area, and the effect of effectively protecting the induction area of the chip to be packaged is achieved.
The chip packaging method of the embodiment of the invention can be used for simultaneously inversely packaging a plurality of chips to be packaged on the transparent substrate and packaging, thereby greatly improving the packaging performance and the packaging efficiency.
According to the chip packaging method provided by the embodiment of the invention, the plastic packaging layer formed by the plastic packaging material surrounds the chip to be packaged and the surface of the transparent substrate, so that the cavity where the sensing area is located is of a closed structure, and the chip packaging method has the advantage of water resistance.
The aspects, embodiments, features and examples of the present invention should be considered as illustrative in all respects and not intended to be limiting of the invention, the scope of which is defined only by the claims. Other embodiments, modifications, and uses will be apparent to those skilled in the art without departing from the spirit and scope of the claimed invention.
The use of headings and sections in this application is not meant to limit the invention; each section may apply to any aspect, embodiment, or feature of the disclosure.
Throughout this application, where a composition is described as having, containing, or comprising specific components or where a process is described as having, containing, or comprising specific process steps, it is contemplated that the composition of the present teachings also consist essentially of, or consist of, the recited components, and the process of the present teachings also consist essentially of, or consist of, the recited process steps.
In this application, where an element or component is referred to as being included in and/or selected from a list of recited elements or components, it is understood that the element or component can be any one of the recited elements or components and can be selected from a group consisting of two or more of the recited elements or components. Moreover, it should be understood that elements and/or features of the compositions, apparatus, or methods described herein may be combined in various ways, whether explicitly described or implicitly described herein, without departing from the spirit and scope of the present teachings.
Unless specifically stated otherwise, use of the terms "comprising", "having", and "has" are generally to be construed as open-ended and not limiting.
The use of the singular herein includes the plural (and vice versa) unless specifically stated otherwise. Furthermore, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. In addition, where the term "about" is used before a quantity, the present teachings also include the particular quantity itself unless specifically stated otherwise.
It should be understood that the order of steps or the order in which particular actions are performed is not critical, so long as the teachings of the invention remain operable. Further, two or more steps or actions may be performed simultaneously.
It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding of the present invention, while eliminating, for purposes of clarity, other elements. However, those skilled in the art will recognize that these and other elements may be desirable. However, because such elements are well known in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements is not provided herein. It should be understood that the figures are presented for illustrative purposes and not as construction diagrams. Details and modifications or alternative embodiments omitted are within the scope of one of ordinary skill in the art.
It is to be understood that in certain aspects of the present invention, a single component may be replaced by multiple components and multiple components may be replaced by a single component to provide an element or structure or to perform a given function or functions. Except where such substitution would not operate to practice a particular embodiment of the invention, such substitution is considered within the scope of the invention.
While the invention has been described with reference to illustrative embodiments, it will be understood by those skilled in the art that various other changes, omissions and/or additions may be made and substantial equivalents may be substituted for elements thereof without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims. Moreover, unless specifically stated any use of the terms first, second, etc. do not denote any order or importance, but rather the terms first, second, etc. are used to distinguish one element from another.

Claims (10)

1. A method of chip packaging, comprising:
providing a transparent substrate, and forming a rewiring layer on the transparent substrate;
providing a chip to be packaged, wherein the chip to be packaged comprises a first surface and a second surface which are opposite, and an induction area and a welding pad coupled with the induction area are formed on the first surface;
forming a welding bump on the welding pad or the rewiring layer;
forming a cofferdam on one side of the transparent substrate on which the rewiring layer is formed or the first surface of the chip to be packaged;
aligning and pressing the first surface of the chip to be packaged and the surface of the transparent substrate with the rewiring layer, wherein the induction area is positioned in a space surrounded by the cofferdam, and the welding salient points, the rewiring layer and the welding pads are electrically connected;
filling a plastic packaging material to carry out plastic packaging on the chip to be packaged and the transparent substrate;
and forming an external conductive column electrically connected with the rewiring layer, wherein the external conductive column protrudes out of the plastic packaging material.
2. The chip packaging method of claim 1,
forming a plurality of cofferdams on the transparent substrate, wherein a cutting path area is formed between every two adjacent cofferdams;
aligning, pressing and electrically connecting a plurality of chips to be packaged and the transparent substrate, wherein each chip to be packaged is arranged corresponding to one cofferdam;
filling a plastic packaging material to carry out integral plastic packaging on the chips to be packaged and the transparent substrate;
forming an external conductive column electrically connected with each chip to be packaged on the plastic packaging material;
and cutting the transparent substrate and the plastic package material along the cutting path area to form a single chip packaging structure.
3. The chip packaging method of claim 1,
forming a cofferdam on the first surface of the chip to be packaged, wherein the cofferdam surrounds the induction area;
aligning and pressing a plurality of chips to be packaged on the same transparent substrate to form electric connection;
filling a plastic packaging material to carry out integral plastic packaging on the chips to be packaged and the transparent substrate;
forming an external conductive column electrically connected with each chip to be packaged on the plastic packaging material;
and cutting the transparent substrate to form a single chip packaging structure.
4. The chip packaging method according to claim 1, wherein the solder bumps are located at the periphery of the dam.
5. The chip packaging method according to claim 1, wherein when the solder bump, the rewiring layer and the pad are in contact and form an electrical connection, a top surface of the dam is in sealing contact with the first surface of the chip to be packaged and/or the transparent substrate.
6. The chip packaging method according to claim 1, wherein forming an external conductive pillar electrically connected to the redistribution layer includes:
forming a through hole on the plastic packaging material, wherein the through hole exposes the rewiring layer;
and forming an external conductive column in the through hole, wherein the external conductive column is protruded on the surface of the plastic packaging material.
7. The chip packaging method according to claim 1, wherein forming a rewiring layer on the transparent substrate comprises:
adhering a metal layer on the surface of the transparent substrate;
and patterning the metal layer to form a rewiring layer.
8. The chip packaging method according to claim 1, wherein the material of the transparent substrate comprises glass.
9. The method of claim 1, wherein the dam comprises an epoxy resin.
10. A chip packaging structure, which is packaged by the chip packaging method according to any one of claims 1 to 9.
CN202210644287.6A 2022-06-08 2022-06-08 Chip packaging method and packaging structure Pending CN114999939A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210644287.6A CN114999939A (en) 2022-06-08 2022-06-08 Chip packaging method and packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210644287.6A CN114999939A (en) 2022-06-08 2022-06-08 Chip packaging method and packaging structure

Publications (1)

Publication Number Publication Date
CN114999939A true CN114999939A (en) 2022-09-02

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210644287.6A Pending CN114999939A (en) 2022-06-08 2022-06-08 Chip packaging method and packaging structure

Country Status (1)

Country Link
CN (1) CN114999939A (en)

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