CN217563633U - Level conversion circuit - Google Patents

Abstract

The utility model relates to a level conversion circuit, the circuit includes: the circuit comprises a first signal end, a second signal end, a first input end, a second input end, a first output end, a second output end, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a first triode and a second triode. This application will last level signal conversion to a required height level signal to can adjust to suitable pulse width through the adjustment parameter, supply follow-up circuits such as MCU to use, be applicable to the application scenario that the baud rate is less than 460 kbps, can realize the conversion between the different levels, through the reference voltage who sets for, can be accurate carry out level switching, the triode can switch on fast simultaneously, response speed is adjustable.

Description

Level conversion circuit

Technical Field

The utility model relates to the technical field of circuits, especially, relate to a level shift circuit.

Background

In electronic circuit design, with the introduction of low voltage logic, the problem of inconsistent input/output logic often occurs inside a system, thereby increasing the complexity of system design. For example, when a 1.8V digital circuit communicates with an analog circuit operating at 3.3V, the problem of switching between two levels needs to be solved first, and a level switching circuit is required.

In the prior art, as ICs with different operating voltages are emerging, the necessity of logic level conversion is more prominent, and the level conversion manner will also vary with the logic voltage, the form of data bus, such as 4-wire SPI, 32-bit parallel data bus, etc., and the data transmission rate. Although many logic chips can now implement higher logic level to lower logic level conversion, such as 5V level to 3V level, these products are not directed to serial buses with data rates lower than 20Mbps, such as SPITM, I2CTM, USB, etc., and these devices have larger package size, larger pin count and I/O direction control pins, and are therefore not suitable for small serial or peripheral interfaces and higher rate buses.

Therefore, how to better perform level conversion is a technical problem that needs to be solved urgently by those skilled in the art.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a level shift circuit to solve prior art's problem.

To achieve the above object, a first aspect of the present application provides a level shift circuit, including:

the circuit comprises a first signal end, a second signal end, a first input end, a second input end, a first output end, a second output end, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a first triode and a second triode;

the first signal end is connected with a third end of the first triode through a third resistor;

the first end of the first triode is connected with the first resistor and the first capacitor;

the second end of the first triode is connected with the second resistor and the first output end;

the first input end is connected with the first resistor, the first capacitor and the second resistor;

the first output end is connected with the second resistor;

the second signal end is connected with the fourth resistor and the second end of the second triode;

the first end of the second triode is connected with the second capacitor and the fifth resistor;

the third end of the second triode is connected with the sixth resistor;

the first input end is connected with the second capacitor and the fifth resistor;

the second input end is connected with the fourth resistor;

the second output end is connected with the sixth resistor.

Specifically, the following technical effects can be achieved:

this application is through inserting a continuous level signal, will last level signal conversion to a required high-low level signal to can adjust to suitable pulse width through the adjustment parameter, supply follow-up circuits such as MCU to use, be applicable to the application scenario that the baud rate is less than 460 kbps, can realize the conversion between the different levels, through the reference voltage who sets for, can be accurate carry out level conversion, the triode can switch on fast simultaneously, response speed is adjustable.

Drawings

Fig. 1 is a schematic structural diagram of a level shift circuit provided in an embodiment of the present invention.

Detailed Description

The following examples are intended to illustrate the invention, but are not intended to limit the scope of the invention.

Examples

As shown in fig. 1, the level shift circuit provided in the present application includes:

the circuit comprises a first signal end STM _ TX, a second signal end STM _ RX, a first input end VDD _ EXT, a second input end STM _ VCC, a first output end MAIN _ RXD, a second output end MAIN _ TXD, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a second capacitor C2, a first triode Q1 and a second triode Q2;

the first signal end STM _ TX is connected with a third end of the first triode Q1 through a third resistor R3;

the first end of the first triode Q1 is connected with the first resistor R1 and the first capacitor C1;

the second end of the first triode Q1 is connected with the second resistor R2 and the first output end VDD _ EXT;

the first input end VDD _ EXT is connected with the first resistor R1, the first capacitor C1 and the second resistor R2;

the first output terminal MAIN _ RXD is connected to the second resistor R2;

the second signal end STM _ RX is connected with the fourth resistor R4 and a second end of the second triode Q2;

the first end of the second triode Q2 is connected with the second capacitor C2 and the fifth resistor R5;

the third end of the second triode Q2 is connected with the sixth resistor R6;

the first input end VDD _ EXT is connected with the second capacitor C2 and the fifth resistor R5;

the second input end STM _ VCC is connected with the fourth resistor R4;

the second output terminal MAIN _ TXD is connected to the sixth resistor R6.

When the method is specifically executed, after the first input end VDD _ EXT is connected to the required low level, the first signal end STM _ TX is used for inputting, due to the conduction characteristics of the first triode Q1 and the second triode Q2, the charging time of the first capacitor C1 and the second capacitor C2 is designed and calculated to obtain the trigger condition, and therefore corresponding actions are executed.

When the first signal terminal STM _ TX is input to be a higher level value, the voltage at the first input terminal VDD _ EXT is set through a level conversion circuit, and the second signal terminal STM _ RX obtains a required level value. The delay of the rising edge and the falling edge can be reduced by reducing the first resistor R1 and the third resistor R3, so that the quick response of the circuit can be realized, and the current can be limited.

When the first signal end STM _ TX is high, the first triode Q1 is cut off, and the second signal end STM _ RX is pulled high along with the level changes of the first input end VDD _ EXT and the second input end STM _ VCC.

When the first signal terminal STM _ TX is low, the first transistor Q1 is turned on, and the second signal terminal STM _ RX is pulled low as a function of the level of the first signal terminal stmtx.

In the description of the present specification, reference to the description of the terms "in one embodiment," "in another embodiment," "exemplary" or "in a particular embodiment," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the invention has been described in detail in the foregoing by way of general description, specific embodiments and experiments, it will be apparent to those skilled in the art that certain modifications and improvements may be made thereto based on the invention. Accordingly, such modifications and improvements are intended to be within the scope of this invention without departing from the spirit thereof.

Claims (1)

1. A level shift circuit, comprising:

the circuit comprises a first signal end, a second signal end, a first input end, a second input end, a first output end, a second output end, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a first triode and a second triode;

the first signal end is connected with a third end of the first triode through a third resistor;

the first end of the first triode is connected with the first resistor and the first capacitor;

the second end of the first triode is connected with the second resistor and the first output end;

the first input end is connected with the first resistor, the first capacitor and the second resistor;

the first output end is connected with the second resistor;

the second signal end is connected with the fourth resistor and the second end of the second triode;

the first end of the second triode is connected with the second capacitor and the fifth resistor;

the third end of the second triode is connected with the sixth resistor;

the first input end is connected with the second capacitor and the fifth resistor;

the second input end is connected with the fourth resistor;

the second output end is connected with the sixth resistor.

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