CN217562532U

CN217562532U - Light-emitting diode and light-emitting diode display

Info

Publication number: CN217562532U
Application number: CN202123417756.0U
Authority: CN
Inventors: 陈卫军
Original assignee: Shenzhen Jing Xiang Technologies Co ltd; Guangdong Jingxiang Photoelectric Technology Co ltd
Current assignee: Shenzhen Jing Xiang Technologies Co ltd; Guangdong Jingxiang Photoelectric Technology Co ltd
Priority date: 2020-09-30
Filing date: 2021-09-27
Publication date: 2022-10-11
Anticipated expiration: 2031-09-27
Also published as: CN113808980A; CN216793639U; CN114300402A; TWM628422U; TW202230786A; CN216793641U; CN113871334A; CN114121746A; CN113871333A; CN114121747A; WO2022068939A1; WO2022068940A1; CN113871332A; CN114300401A; TWI823150B; CN216793640U; CN217361526U

Abstract

The utility model provides a light emitting diode and light emitting diode display, include: a substrate; a semiconductor epitaxial structure disposed on the substrate; the transparent conducting layer is arranged on the first electrode on the semiconductor structure and is arranged on the first semiconductor layer of the semiconductor epitaxial structure; a second electrode disposed on the transparent conductive layer; and a waterproof protective layer disposed on the transparent conductive layer and a portion of the first electrode and the second electrode. Through the utility model provides a pair of light emitting diode can prevent the invasion of steam.

Description

Light-emitting diode and light-emitting diode display

Technical Field

The utility model relates to a semiconductor field, in particular to emitting diode and emitting diode display.

Background

The light emitting diode has the characteristics of electricity saving, high definition, fast response time and the like in the application of the backlight field, and is widely applied to various backlights and displays. However, as the applications become more widespread, various adverse environments often result in failure of the led. Particularly, moisture is permeated, and the damage to the chip is particularly serious.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned prior art's defect, the utility model provides a light emitting diode and light emitting diode display aims at improving the steam infiltration, and then leads to the problem that light emitting diode became invalid.

To achieve the above and other objects, the present invention provides a light emitting diode, including:

a substrate;

a semiconductor epitaxial structure disposed on the substrate;

a transparent conductive layer disposed on the semiconductor epitaxial structure;

a first electrode disposed on a first semiconductor layer of the semiconductor epitaxial structure;

a second electrode disposed on the transparent conductive layer; and

and the waterproof protective layer is arranged on the transparent conductive layer and part of the first electrode and the second electrode.

Optionally, the waterproof layer includes a protective film layer covering the transparent conductive layer and extending toward the first electrode and the second electrode, and the protective film layer covers a side wall and a part of a top wall of the first electrode and the second electrode.

Optionally, the protective film layer includes a first waterproof protective layer, and the first waterproof protective layer is an oxide layer.

Optionally, the thickness of the first waterproof protective layer is 100-300 nm.

Optionally, the protective film layer includes a second waterproof protective layer, the second waterproof protective layer covers the first waterproof protective layer, and the second waterproof protective layer is a gradual change layer of the oxide layer and the nitride layer.

Optionally, the thickness of the second waterproof protective layer is 20nm.

Optionally, the protective film layer includes a third water-proof layer, the third water-proof layer covers on the second water-proof layer, and the third water-proof layer is a nitride layer.

Optionally, the third water-proofing protective layer has a thickness of 20 to 50nm.

Optionally, the waterproof protective layer includes a hydrophobic film layer disposed on the protective film layer.

Optionally, the waterproof protective layer includes a water fence layer, the water fence layer is disposed on the hydrophobic film layer, and the water fence layer includes a plurality of protruding structures.

Optionally, the light emitting diode is a micro light emitting diode.

The utility model also provides a light emitting diode display, include as above light emitting diode.

To sum up, the utility model provides a light emitting diode and light emitting diode display is equipped with special protective layer in the outer lane of first electrode and second electrode and send out light zone, can let moisture content unlikely to stop on the chip, can make the chip keep dry, and then avoids the harmfulness that steam leads to.

Drawings

FIG. 1: the structure of the semiconductor device in this embodiment is schematically illustrated.

FIG. 2: in this embodiment, a schematic diagram of a transition chamber structure is shown.

FIG. 3: the structure of the cleaning cavity in this embodiment is schematically illustrated.

FIG. 4: the structure of the preheating chamber in this embodiment is schematically illustrated.

FIG. 5: the structure of the growth chamber in this embodiment is schematically illustrated.

FIG. 6: the target and the backing plate in this embodiment are schematically illustrated.

FIG. 7: another semiconductor device structure in this embodiment is schematically illustrated.

FIG. 8: the structure of the deposition chamber in this embodiment is schematically illustrated.

FIG. 9: the first deposition chamber is schematically structured.

FIG. 10: schematic view of a diffuser plate.

FIG. 11: the first air inlet pipeline and the second air inlet pipeline are in schematic structural diagrams.

FIG. 12: schematic view of the substrate inlet.

FIG. 13: schematic of a second circuit.

FIG. 14: a structure diagram of a semiconductor device.

FIG. 15: a semiconductor epitaxial structure provided with a hole injection layer.

FIG. 16: schematic diagram of polar plane and non-polar plane.

FIG. 17: a semiconductor epitaxial structure having a stable wavelength.

FIG. 18 is a schematic view of: a semiconductor epitaxial structure provided with a resistive layer.

FIG. 19: fig. 18 is an equivalent circuit diagram of the semiconductor epitaxial structure.

FIG. 20: a schematic structure of a micro light emitting diode.

FIG. 21: a schematic diagram of a large-angle micro light-emitting diode structure.

FIG. 22: a schematic diagram of a small-angle micro light-emitting diode structure.

FIG. 23: FIG. 22 is a schematic view of a shielding layer structure.

FIG. 24: a schematic view of a barrier covering two sides.

FIG. 25 is a schematic view of: a schematic view of a barrier covering four sides.

FIG. 26: a schematic structure diagram of a micro light emitting diode with a filling layer is provided.

FIG. 27 is a schematic view of: fig. 26 is a schematic view of the structure of the leveling layer.

FIG. 28: fig. 26 is a schematic diagram of the stress applied to the substrate by soldering the micro led.

FIG. 29: the schematic view of the light-emitting angle of the micro light-emitting diode structure without the leveling layer.

FIG. 30: fig. 26 is a schematic view of the light emitting angle of the micro light emitting diode.

FIG. 31: a schematic diagram of a micro light emitting diode with a metal lamination arranged on an electrode.

FIG. 32: a micro light emitting diode with a special conductive structure is disclosed.

FIG. 33 is a schematic view of: a micro light-emitting diode with a waterproof protective layer is disclosed.

FIG. 34 is a schematic view of: fig. 33 is a schematic view of the structure of the protective film layer.

FIG. 35: FIG. 33 is a schematic electron microscope image of the projection structure.

FIG. 36: the included angle between the tangent line of the edge of the liquid drop and the reference plane is schematically shown on the surface with different hydrophobicity.

FIG. 37: a micro light-emitting diode with a supporting layer arranged between electrodes is disclosed.

FIG. 38: a structure diagram of a micro light emitting diode transfer device.

FIG. 39: a top view of a micro light emitting diode transfer device.

FIG. 40: a schematic diagram of a cutting groove of a micro light-emitting diode transfer device.

FIG. 41: a schematic diagram of a cutting position of a micro light emitting diode transfer device is provided.

FIG. 42: a structure diagram of a micro light-emitting diode display panel is provided.

FIG. 43: a top view of a micro light emitting diode display panel.

FIG. 44: a schematic structure of an electronic device is provided.

FIG. 45: a semiconductor device structure is schematically shown.

FIG. 46: a schematic structure of a radio frequency module is provided.

Detailed Description

The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can be implemented or applied by other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

Referring to fig. 1, the present embodiment provides a semiconductor apparatus 100, which may be a chemical vapor deposition apparatus, a physical vapor deposition apparatus, or a combination of a physical vapor deposition apparatus, a chemical vapor deposition apparatus, or other semiconductor apparatuses, for example.

As shown in fig. 1, in an embodiment of the present invention, a plurality of chambers are disposed in the semiconductor apparatus 100, and in an embodiment of the present invention, the semiconductor apparatus 100 may include, for example, a transfer chamber 110, a preheating chamber 140, a cleaning chamber 130, a transition chamber 120, and a plurality of growth chambers 150. In the manufacturing process of the semiconductor device, substrate preheating and plasma cleaning may be performed on the substrate, the substrate after cleaning may be transferred to the growth chamber 150, a thin film may be grown in the growth chamber 150, and then cooling may be performed.

As shown in fig. 1, in the present embodiment, the transfer chamber 110 includes a substrate handling robot 111, and the substrate handling robot 111 is operable to transfer substrates between the chambers. The size of the substrate handling robot 111 may also be adjusted according to the spatial dimensions of the different chambers. More specifically, the substrate handling robot 111 may have dual substrate handling blades adapted to simultaneously transfer two substrates from one chamber to another. Substrates may be transferred between the transfer chamber 110 and other chambers via the slit valve 112. The movement of the substrate handling robot 111 may be controlled by a motor drive system (not shown), which may include a servo motor or a stepper motor.

Referring to fig. 1, in some embodiments, the semiconductor apparatus further comprises a manufacturing interface 113, wherein the manufacturing interface 113 comprises a cassette containing a substrate to be processed and a substrate handling robot (not shown) that may comprise a substrate planning system to load the substrate in the cassette into the transition chamber 120, and in particular, to place the substrate on a tray of the stage.

Referring to fig. 1, in the present embodiment, the preheating chamber 140 is connected to the transfer chamber 110, the preheating chamber 140 is located on a sidewall of the transfer chamber 110, and when the substrate enters the transition chamber 120, the substrate handling robot 111 in the transfer chamber 110 then transfers the substrate from the transition chamber 120 to the preheating chamber 140 for preheating and plasma cleaning.

Referring to fig. 1, in the present embodiment, a plurality of growth chambers 150 are disposed on the sidewall of the transfer chamber 110, and after the substrate is processed, the substrate loading and unloading robot 111 in the transfer chamber 110 transfers the substrate into the growth chambers 150 for operation, so that a uniform magnetic field is formed in the growth chambers 150, thereby forming uniform sputter ions on the surface of the substrate, and forming a uniform thin film on the substrate.

Referring to FIG. 2, in the present embodiment, the transition chamber 120 is connected to the transfer chamber 110, wherein the transition chamber 120 is located between the manufacturing interface 113 and the transfer chamber 110. The transition chamber 120 provides a vacuum interface between the fabrication interface 113 and the transfer chamber 110.

As shown in fig. 1 and 2, in some embodiments, the transition chamber 120 may implement processes of substrate transfer, pre-heating, and cleaning. The transition chamber 120 includes a housing 120a, and the housing 120a is, for example, a sealed cylinder, and a suction opening and a discharge opening are disposed on a sidewall of the housing 120 a. The transition chamber 120 is provided with a plurality of air passage channels, such as air inlets 128. A plurality of air paths such as the air inlet 128 and a power supply are additionally arranged in the transition cavity 120, so that the baking preheating and plasma cleaning processes are realized, and a single pump is used for pumping and filling air, so that the whole process flow is smoother, and the whole time consumption is saved.

Referring to fig. 2, in some embodiments, a carrier 122 is disposed in the transition chamber 120, and the carrier 122 is fixed to the bottom of the housing 120a by a lift base motor 121. A tray 123 may be provided on the carrier 122, and a multi-layer open transfer box 124 may be provided on the tray 123 to perform a function of transferring disks at the same time. In this embodiment, the stage 122 may be, for example, cylindrical or rectangular or other shapes, and the stage 122 may be fixed in the housing 120a by, for example, the lifting base motor 121. A laser sensor 125 may be disposed inside the housing 120 a. The transition cavity 120 allows multiple disks to enter simultaneously, only needs to be vacuumized once at the beginning and filled with atmosphere once at the end, so that the frequent filling and pumping time of the intermediate transmission disk is saved, and the time consumed by filling and pumping of the transmission node is reduced.

In some embodiments, as shown in fig. 1 and 2, the transition chamber 120 further comprises a pumping port connected to a vacuum pump 327, and the transition chamber 120 is pumped down by the vacuum pump 127. Multiple N2 gas paths are added to the transition chamber 120 to introduce gas, so that gas cooling can be provided instead of the cooling chamber when the chamber is not transferring.

Referring again to fig. 1 and 2, in another embodiment of the present invention, the transition chamber 120 performs only a substrate transfer function, and the plasma cleaning and cooling of the substrate are performed in the cleaning chamber 130. In this embodiment, the cleaning chamber 130 is connected to the transfer chamber 110, the cleaning chamber 130 is located on a sidewall of the transfer chamber 110, and when the substrate enters the transition chamber 120, the substrate handling robot 111 in the transfer chamber 110 then transfers the substrate from the transition chamber 120 to the cleaning chamber 130 for cleaning, and after growing a thin film on the substrate, transfers the substrate to the cleaning chamber 130 for cooling.

Referring to fig. 3, a substrate support assembly 131 is disposed in the cleaning chamber 130, the substrate support assembly 131 is disposed at the bottom of the cleaning chamber 130, and the substrate support assembly 131 does not contact the cleaning chamber 130. The substrate support assembly 131 comprises a pedestal electrode 1311 and an electrostatic chuck 1312, wherein the electrostatic chuck 1312 is disposed on the pedestal electrode 1311, the electrostatic chuck 1312 is used for placing a substrate, at least one substrate can be placed on the electrostatic chuck 1312, and in some embodiments, a plurality of substrates can be disposed on the electrostatic chuck 1312 while cleaning the plurality of substrates, thereby improving the work efficiency.

As shown in fig. 3, in the embodiment, the substrate support assembly 131 is connected to an elevating and rotating mechanism 134, and specifically, the elevating and rotating mechanism 134 is connected to the pedestal electrode 1311, so that the elevating and rotating mechanism 134 can raise and lower or rotate the substrate support assembly 131, and indirectly raise and lower or rotate the substrate. When the substrate support assembly 131 is rotated up or down, the distance between the substrate and the electrode 132 is changed to adjust the electric field strength between the pedestal electrode 1311 and the electrode 132, so that the plasma can better clean the substrate.

Referring to FIG. 3, in the present embodiment, the cleaning chamber 130 further includes an electrode 132, the electrode 132 is disposed above the substrate support assembly 131, the electrode 132 does not contact the top of the cleaning chamber 130, and in some embodiments, the distance between the electrode 132 and the substrate support assembly 131 may be 2-25cm. The electrode 132 is also connected to a lifting/lowering mechanism 133, and the lifting/lowering mechanism 133 and the lifting/lowering mechanism 134 are identical in structure. When the electrode 132 is rotated up or down, the distance between the electrode 132 and the substrate is changed to adjust the strength of the electric field between the electrode 132 and the substrate, so that the plasma can uniformly clean the substrate. When the electrode 132 and the substrate support assembly 131 are rotated simultaneously, the rotation speed of the electrode 132 and the rotation speed of the substrate support assembly 131 may be the same or have a certain speed difference, so that the substrate is uniformly cleaned by the plasma.

In the present embodiment, as shown in FIG. 3, the substrate support assembly 131 is further coupled to at least one RF bias power source 138, and in particular, the RF bias power source 138 is coupled to the pedestal electrode 1311. The rf frequency of the rf bias power source 138 may be high, medium, or low. The RF power source 137 and the RF bias power source 138 are both driven by a synchronization pulse, which can be turned on and off simultaneously to reduce the temperature of the electrons in the cleaning chamber 130, and the synchronization pulse has good control over the cleaning (etch depth) of the dense region of the substrate.

In the present embodiment, as shown in FIG. 3, the purge chamber 130 further comprises a gas inlet near the electrode 132, the gas inlet is connected to a gas source 135, and a gas, which is a precursor gas for the purge application, is supplied into the purge chamber 130 through the gas source 135. In this embodiment, the cleaning chamber 130 further comprises a pumping port proximate to the substrate support assembly 131, the pumping port being coupled to a vacuum pump 136, the vacuum pump 136 being configured to pump a gas from the cleaning chamber 130.

As shown in fig. 1, fig. 3 and fig. 4, in another embodiment of the present invention, when semiconductor manufacturing is performed, the substrate needs to be placed in the preheating chamber 140 for preheating before growing the thin film on the substrate, the preheated substrate is transported to the cleaning chamber 130 for cleaning, the cleaned substrate is transported to the growth chamber 150 for growing the thin film, and after the thin film is grown, the substrate is transported to the cleaning chamber 130 for cooling. In the process of forming the thin film, the thermal radiation loss is easily caused in the cleaning process between the preheating chamber 140 for preheating the substrate and the cleaning chamber 130, in this embodiment, the cleaning structure is additionally installed in the preheating chamber 140, and the substrate can be simultaneously subjected to plasma cleaning when being preheated.

In another embodiment of the present invention, as shown in fig. 4, the preheating chamber 140 includes a housing 140a, a support 141 is provided at the bottom of the housing 140a, the support 141 may be a hollow structure, for example, and then a wire is placed in the inner structure of the support 141 and connected to the heater 142. In this embodiment, the support 141 may be made of a high temperature resistant material, for example.

As shown in fig. 4, a heater 142 is disposed in the preheating chamber 140, the heater 142 is fixed to the bracket 141, and the heater 142 may include a base plate and a heating coil disposed at the bottom of the base plate. A plurality of measuring points are further disposed on a surface of the tray 143 adjacent to the substrate 144, and then the plurality of measuring points are connected to a temperature measuring device, which can be disposed in the preheating chamber 140 or outside the preheating chamber 140, so that the temperature of the substrate 144 can be measured in real time by the temperature measuring device, and the surface temperature and the thermal uniformity of the substrate 144 can be controlled.

As shown in fig. 4, at least one pumping port may be further disposed at the bottom of the preheating chamber 140, the pumping port is connected to a vacuum pump 145, and the vacuum pump 145 is used to perform a vacuum process on the preheating chamber 140 to obtain a vacuum preheating chamber 140. At least one heater 142 is disposed in the preheating chamber 140, and it should be noted that a plurality of heaters 142 may be disposed on the sidewall of the preheating chamber 140, or a plurality of heaters may be disposed on the top of the preheating chamber 140, so as to ensure the uniformity of the overall temperature of the preheating chamber 140.

Referring to FIG. 4, at least one electrode 149 may be disposed on the top of the preheating chamber 140 and above the substrate 144, the electrode 149 does not contact the top of the preheating chamber 140, and the distance between the electrode 149 and the substrate 144 may be 2-25cm, such as 10-20 cm, or 16-18 cm. The electrode 149 is also connected to the lifting and rotating mechanism 146, the lifting and rotating mechanism 146 may be identical to the lifting and rotating mechanism 133 shown in fig. 3, when the electrode 149 rotates to lift or lower, the distance between the electrode 149 and the substrate is changed to adjust the electric field intensity between the electrode 149 and the substrate, so that the plasma can uniformly clean the substrate.

Referring to fig. 3 and 4, a lifting and rotating mechanism 134 and an rf bias power source 138 may be disposed on the support 141 and the heater 142. When the electrode 149 and the substrate 144 are rotated simultaneously, the rotation speed of the electrode 149 and the rotation speed of the substrate 144 on the heater 142 may be the same or have a predetermined speed difference, so that the plasma uniformly cleans the substrate. And the electrode 149 is also connected to at least one rf power source 148, the rf power source 148 being arranged in the same manner as the rf power source 148 shown in fig. 3.

Referring to fig. 4, a gas inlet is disposed on the sidewall of the preheating chamber 140, the gas inlet is close to the electrode 149, the gas inlet is connected to a gas source 147, and the gas source 147 is used to deliver gas, which is a precursor gas for cleaning applications, into the preheating chamber 140.

Referring to fig. 1, 3 and 4, the plasma cleaning process is performed in a constant high temperature environment, and a plasma cleaning apparatus is installed in the preheating chamber 140 to simultaneously perform plasma cleaning on the substrate while preheating the substrate. After being heated in the preheating chamber 140, the substrate may be directly transferred to the growth chamber 150 to form a thin film without being transferred to the cleaning chamber 130 for cleaning, or after being preheated and cleaned in the preheating chamber 140.

Referring to fig. 5-7, growth chamber 150 includes a growth chamber housing 151, a pedestal 152, a target 153, and a magnet 154. A water cooling device 1508 is added inside or on the side wall of the growth chamber 150, as shown in fig. 5. A susceptor 152 may be disposed at the bottom end of the growth chamber housing 151, allowing one or more substrates 155 to be placed on the susceptor 152. The susceptor 152 may be formed from a variety of materials, including silicon carbide or graphite coated with silicon carbide. The base 152 is further connected to a driving unit 156, the driving unit 156 is connected to a control unit (not shown), the driving unit 156 is used for driving the base 152 to ascend or descend, the driving unit 156 may be a driving device such as a servo motor or a stepping motor, and the control unit is used for controlling the driving unit 156 to drive the base 152 to ascend during the magnetron sputtering process, so that the distance between the target 153 and the base 152 is always kept at a predetermined value.

Referring to fig. 5-7, in the present embodiment, the target 153 is disposed on the top of the growth chamber housing 151, and the target 153 is electrically connected to a sputtering power source (not shown) that outputs sputtering power to the target 153 during the magnetron sputtering process, so that the plasma formed in the growth chamber housing 151 etches the target 153. The target 153 has at least one surface portion composed of a material to be sputter deposited on a substrate 155 disposed on the pedestal 152. When the magnet 154 in the processing chamber of the machine is as large as the tray, for example, less than or equal to 330mm, the thickness of the deposited aluminum nitride is too thin at the outer position of the outer ring of the tray, which may affect the overall thickness uniformity. In this embodiment, the target 153 and the backing plate 1509 are enlarged as a whole, and the diameter of the bombarded surface of the target 153 is set to be larger than or equal to, for example, 400mm to 600mm, and the diameter of the magnet operation covering surface is larger than or equal to 400mm to 600mm. The target 153 and backing plate 1509 are surrounded on their outer sides by a protective ring 1510, which may be a ceramic ring or a stainless steel ring. In some embodiments, after loading the substrate 155 into the growth chamber housing 151, a continuous aluminum nitride film may be deposited on the substrate 155 by using an aluminum-containing target and a nitrogen-containing process gas, which may include, but is not limited to, a nitrogen-containing gas and an inert gas, used during the sputtering process.

Referring to fig. 5 to 7, in the present embodiment, the magnet 154 is located above the target 153, the magnet 154 rotates around the central axis of the target 153, and the magnet 154 can rotate around the central axis of the target 153 by any angle. In this embodiment, the magnet 154 is connected to a driving mechanism, and the driving mechanism drives the magnet 154 to rotate and reciprocate up and down. The driving mechanism includes a first motor 157, a transmission rod 158, a second motor 159 and a lifting assembly. The first motor 157 is connected to the second motor 159 through a transmission rod 158, the first motor 157 can drive the second motor 159 to reciprocate up and down through the transmission rod 158, and the first motor 157 drives the transmission rod 158 to rotate in the forward direction or the reverse direction, so that the second motor 159 can reciprocate. In this embodiment, the lifting assembly includes an outer shaft 1501 and an inner shaft 1502, in this embodiment, the second motor 159 is connected to the inner shaft 1502 through an output shaft 1504, the output shaft 1504 is partially located in the outer shaft 1501, the second motor 159 can drive the inner shaft 1502 to rotate through the output shaft 1504, meanwhile, the first motor 157 drives the second motor 159 to reciprocate up and down through a transmission rod 158, when the first motor 157 and the second motor 159 are simultaneously turned on, the inner shaft 1502 can reciprocate up and down and also rotate, so as to drive the magnet 154 on the inner shaft 1502 to correspondingly move. The inner shaft 1502 may only reciprocate up and down when the first motor 157 is turned on and the second motor 159 is turned off. The inner shaft 1502 may only perform rotational movement when the first motor 157 is turned off and the second motor 159 is turned on. Whereby the operator can choose to turn the first motor 157 and/or the second motor 159 on and/or off depending on the implementation.

Referring to fig. 5-7, in some implementations, the target 153 may remain stationary or may rotate about its central axis while the magnet 154 is in rotational motion, but there is a speed difference between the target 153 and the magnet 154. The relative motion of the target 153 and the magnet 154 can make the magnetic field generated by the magnet 154 scan the sputtering surface of the target 153 uniformly, and since the electric field and the magnetic field uniformly distributed on the sputtering surface of the target 153 act on the secondary electrons simultaneously in the present embodiment, the motion trajectory of the secondary electrons can be adjusted to increase the number of times of collision between the secondary electrons and the argon atoms, so that the argon atoms near the sputtering surface of the target 153 are sufficiently ionized to generate more argon ions. And more argon ions bombard the target 153, so that the sputtering utilization rate and sputtering uniformity of the target 153 can be effectively improved, and the quality and uniformity of the deposited film are further improved.

The utility model discloses an in the embodiment, to preheating the semiconductor equipment that the chamber can realize preheating and cleaning function, this application still provides a semiconductor equipment's application method, include:

s11: placing the multi-layer open transfer box in a transition chamber on the tray and transferring the substrate to a pre-heating chamber;

s12: baking and preheating in a preheating cavity, and introducing gas for plasma cleaning;

s13: growing a thin film in the growth cavity;

s14: and introducing gas into the middle cavity of the cleaning cavity, and cooling the tray.

As shown in fig. 1 and 8, in an embodiment of the present invention, a semiconductor apparatus 100 is, for example, a chemical vapor deposition apparatus, and a plurality of deposition chambers are disposed on a sidewall of a transfer chamber 110. In the present embodiment, four deposition chambers, i.e., a first deposition chamber 161, a second deposition chamber 162, a third deposition chamber 163, and a fourth deposition chamber 164 are shown. The robot 311 in the transfer chamber 110 may sequentially transfer the substrate or wafer into the first deposition chamber 161, the second deposition chamber 162, the third deposition chamber 163 and the fourth deposition chamber 164 to form a thin film on the substrate or wafer. In this embodiment, at least one of the first deposition chamber 161, the second deposition chamber 162, the third deposition chamber 163 and the fourth deposition chamber 164 may be detachable, which means that the detachable chamber may be detached alone without affecting the operation of the entire semiconductor apparatus 100. The present embodiment, for example, provides the first deposition chamber 161 as a detachable chamber. In other embodiments, a removable chamber may be provided separately.

As shown in fig. 9, fig. 9 is a sectional view showing the first deposition chamber 161. As can be seen from the figure, the first deposition chamber 161 includes a main chamber 101, a base 102 is arranged inside the main chamber 101, and the base 102 may be arranged at the bottom of the main chamber 101. A radio frequency assembly 103 is arranged on the top of the main cavity 102, and the radio frequency assembly 103 and the base 102 are arranged oppositely. The RF assembly 103 and the pedestal 102 form a plasma generation region. The material of the main chamber 101 is, for example, stainless steel. In some embodiments, the rf assembly 103 may also be rotated during deposition to make the film deposition more uniform.

As shown in fig. 9, in some embodiments, the base 102 may further be connected to a rotation unit for rotating the base 102 during film deposition, further improving the thickness uniformity of the plated film, and improving the stress uniformity of the plated film.

As shown in fig. 9, of course, in some embodiments, a heating unit may be disposed on the back of the base 102, and the substrate may be heated by the heating unit. In some embodiments, the heating unit may be a radio frequency heater, an infrared radiation heater, or a resistance heater, and may be selected differently according to the size and material of the main chamber 101. In the rf heating mode, the graphite base 102 is heated by the rf coil through inductive coupling, which can be applied to a large main chamber 101.

As shown in fig. 9, in the present embodiment, the rf assembly 103 is further connected to an rf power source, and a voltage is supplied to the rf assembly 103 through the rf power source, so as to ionize the precursor gas into plasma.

As shown in fig. 9, in this embodiment, an air inlet is further included at the top of the main chamber 101, an air inlet pipe 104 is connected to the air inlet, one end of the air inlet pipe 104 is connected to the air inlet, and the other end of the air inlet pipe 104 is connected to an external air source 105. Through this external gas source 105, the gas inlet line 104 and the gas inlet can deliver the reactive gas into the main chamber 101.

As shown in fig. 9, in the present embodiment, the air inlet is disposed at one side of the rf module 103, and the air inlet 104 includes a first pipe 1041 and a second pipe 1042. One end of the first pipe 1041 is connected to the external air source 105, and the other end of the first pipe 1041 is connected to the second pipe 1042. The first pipe 1041 is connected to the second pipe 1042, for example, by a quick coupling 107. The first pipe 1041 and the second pipe 1042 can be connected or separated by rotating the quick structure 107. The first pipe 106 is provided with a first valve 106, and when gas is supplied into the main chamber 101, the first valve 106 is, for example, in an open state, and when the chamber needs to be removed, the first valve 106 is, for example, in a closed state, so that heavy metal dust can be prevented from entering the clean room.

As shown in fig. 9 and 10, in the present embodiment, one end of the second pipe 1042 extends into the main chamber 101, and a diffusion plate 108 is disposed at one end of the second pipe 1042. The diffusion plate 108 has a plurality of diffusion holes 1081. The reaction gas can be uniformly diffused into the main chamber 101 through the diffusion holes 1081. In addition, the diameters of the diffusion holes 1081 may be the same or different, and the arrangement density of the diffusion holes 1081 may be changed.

As shown in fig. 9 and 11, in some embodiments, a plurality of air inlets may be further disposed on the top of the main chamber 101, that is, a plurality of air inlet pipes 104 are disposed, for example, a first air inlet pipe 104a and a second air inlet pipe 104b are disposed, the first air inlet pipe 104a may be connected to a first air inlet device, and the second air inlet pipe 104b may be connected to a second air inlet device. The first air inlet pipeline 104a and the second air inlet pipeline 104b are located on two sides of the main cavity 101, and the height of the first air inlet pipeline 104a is greater than that of the second air inlet pipeline 104b, and because the first air inlet pipeline 104a and the second air inlet pipeline 104b have a height difference, the gases delivered to the main cavity 101 through the first air inlet pipeline 104a and the second air inlet pipeline 104b cannot affect each other.

As shown in fig. 9, in this embodiment, at least one exhaust port is further disposed at the bottom of the main chamber 101, one end of the exhaust pipeline 109 is connected to the exhaust port, and the other end is connected to the air pump 1013, and the air pump 1013 performs air pumping operation on the main chamber 101 to pump away the extra plasma, thereby reducing the probability of the extra ions falling onto the film and improving the quality of the film. A second valve body 1014 is further provided at the bottom of the main chamber 101, the second valve body 1014 being located at the exhaust port, the second valve body 110 being in an open state when the pumping operation is performed, and the second valve body 1014 being in a closed state when the deposition operation is completed to prevent the plasma from being diffused out.

As shown in fig. 8 and 12, in this embodiment, the main chamber 101 further includes a substrate entrance through which a robot arm within the transfer chamber 110 places a substrate within the main chamber 101. The substrate access includes two telescoping doors 1011. When the two retractable doors 1011 are opened, that is, the substrate entrance is opened. When the two retractable doors 1011 are closed, that is, the substrate outlet is closed. The main housing 101 is further coupled to a locking unit 1012, and the locking unit 1012 may maintain the substrate access in a locked state when the main housing 101 is disassembled, that is, the locking unit 1012 may maintain the substrate access in a closed or locked state when the main housing 101 is de-energized. When the substrate inlet is kept in a locked state, the plasma remaining in the main chamber 101 can be prevented from diffusing into the clean room, thereby preventing heavy metal contamination of the clean room.

As shown in fig. 9, in this embodiment, the substrate inlet may also be used as a substrate outlet, that is, the robot arm can put the substrate into the main chamber 101 or take the substrate out of the main chamber 101 through the substrate inlet. In some embodiments, the main chamber 101 may further include a substrate outlet, i.e., the substrate outlet is disposed opposite to the substrate inlet, so that when the robot arm places the substrate in the main chamber 101 through the substrate inlet, the substrate is taken out of the main chamber 101 through the substrate outlet. Because the base plate export sets up with the base plate entry is relative, consequently open the base plate export, the heavy metal dust in the main cavity 101 can not spread to the clean room in, consequently can not cause the clean room pollution.

As shown in fig. 13, in some embodiments, the end of the second pipe 1042 may also be designed to bend toward the space between the rf assembly 103 and the base 102, so that the gas can diffuse between the rf assembly 103 and the base 102.

As shown in fig. 1 and 9, in the present embodiment, the semiconductor apparatus 100 includes a transfer chamber 110 and a detachable chamber, a robot 311 in the transfer chamber 110 transfers a substrate into or out of the detachable chamber, when an operation is performed in any one of the chambers (including preheating, cleaning, deposition, growth, and cooling), by closing the first valve body and the second valve body, gas in a gas source cannot enter the detachable chamber, and at the same time, reaction gas in the detachable chamber cannot be discharged from the gas outlet, and at the same time, a substrate inlet of the detachable chamber is closed by a locking unit, and then the detachable chamber is moved into another clean room, the substrate inlet is opened, and then the substrate is taken out, thereby preventing heavy metal contamination of the original clean room, and then the detachable chamber can be maintained and then disposed outside the transfer chamber 310.

Referring to fig. 14, in some embodiments, a plurality of reaction chambers 170 are disposed in the coating system 180 of the semiconductor apparatus 100, and the reaction chambers 170 may be growth chambers in a physical vapor deposition apparatus or deposition chambers in a chemical deposition apparatus. In the present embodiment, the reaction chamber 170 includes, for example, a first reaction chamber 171 and a second reaction chamber 172. And two chamber doors, for example, a first chamber door 173 and a second chamber door 174, are disposed on each of the first reaction chamber 171 and the second reaction chamber 172. Each of the chambers corresponds to one of the substrate handler robots 111, for example, includes a first robot 111a corresponding to the first chamber door 173 and a second robot 111b corresponding to the second chamber door 174, and an air inlet duct 183 and a transfer rail 181 are further provided at one side of the reaction chamber 170. And the first reaction chamber 171 and the second reaction chamber 172 are connected by an open/close valve, so that the substrate can be conveniently transported and the processing efficiency can be improved.

As shown in fig. 14, the first chamber door 173 and the second chamber door 174 are disposed on the first reaction chamber 171 and the second reaction chamber 172, in some embodiments, the first chamber door 173 and the second chamber door 174 are disposed on the same side of the reaction chamber, and in other embodiments, the first chamber door 173 and the second chamber door 174 are disposed on opposite sides of the reaction chamber. The specific structure of the first and

second chamber doors

173 and 174 may be a telescopic door as shown in fig. 12, and will not be described again. And the first chamber gate 173 serves as a substrate inlet/outlet and the second chamber gate 174 serves as a substrate outlet/inlet during an actual thin film growth process. By separating the substrate outlet from the substrate inlet, contamination of the substrate is reduced. The substrate handling robot 111 provided corresponding to the chamber door includes a first robot 111a and a second robot 111b. During the transfer of the substrate, the first robot 111a may transfer the substrate into the reaction chamber 170 through the first chamber door 173, for example, and the second robot 111b may transfer the substrate out of the reaction chamber 170 through the second chamber door 174, for example. The two mechanical arms are arranged, so that the substrates can be picked up conveniently, the substrates can be transmitted in and out simultaneously, and the transmitted substrate loading and unloading mechanical arms 111 are distinguished, so that the pollution of the substrates can be further reduced, and the quality and uniformity of deposited films can be improved.

As shown in FIG. 14, the pedestal 152 (or pedestal 102) is disposed at the top of the reaction chamber 170, and the target 153 (or RF module 103) is disposed at the bottom of the reaction chamber 170. In contrast to the position in fig. 5 (or fig. 9), the reactants move from bottom to top. In some embodiments, the base 152 has a retaining clip thereon for retaining a substrate. In the present embodiment, the pedestal 152 is a magnetic pedestal, allowing multiple magnetic pedestals to be placed on opposite sides of the target 153, in which case the pedestal 152 may directly attract the substrate to the pedestal 152 without requiring additional structures to secure the substrate. The susceptor 152 may comprise sapphire, silicon carbide, silicon, gallium nitride, diamond, lithium aluminate, zinc oxide, tungsten, copper, and/or aluminum gallium nitride, and the susceptor 152 may be metallized such that the susceptor 152 is metallic. A magnet is provided in the base 152 to provide the base 152 with an adsorption function. When the magnet rotates, the base 152 can rotate around its central axis. When the magnet is rotated, the susceptor 152 may be driven to rotate around its central axis by a power source such as a motor, so that the magnetic field generated by the magnet closely adheres to the susceptor 152, further improving the quality and uniformity of the deposited film, and the size of the susceptor 152 is, for example, 2 to 12 inches.

As shown in fig. 14, the transfer track 181 connects the reaction chamber 170 with other semiconductor devices, such as a chamber door, which may be a cleaning device, a preheating device, or other semiconductor devices. The gas inlet line 182 is connected to an external gas source, which supplies gas into the reaction chamber 170 through the gas inlet line 182. The air inlet pipe 182 may include a first air inlet pipe connected to the first reaction chamber 171 and a second air inlet pipe connected to the second reaction chamber 172, and the air inlet pipes are designed to facilitate input and output of gas.

The semiconductor device of the present application can manufacture a high-quality contamination-free thin film such as a metal thin film, a semiconductor thin film, an insulating thin film, a compound thin film, or a thin film of other material.

As shown in fig. 15, in an embodiment of the present invention, when a semiconductor epitaxial structure 20 is manufactured by using the semiconductor device of the present disclosure, the semiconductor epitaxial structure 20 may include a substrate 200, and a first semiconductor layer 203, an active layer 204, and a second semiconductor structure 21 sequentially disposed on the substrate 200.

As shown in fig. 15, the substrate 200 may be a sapphire substrate 200. In other embodiments, the substrate 200 may also be silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), lithium aluminate (LiAlO) ₂ ) And the like.

As shown in fig. 15-16, in some embodiments, the substrate 200 may beThe material of the substrate 200 is made of a crystal axis material without an electroless reaction, or a special flattening layer is formed on the substrate 200 to select the crystal phase direction of the substrate 200 and eliminate the influence of the piezoelectric effect on the substrate 200. In some embodiments, the substrate 200 may be made of an N-plane (1100) or an a-plane (1120), such as GaN, alN, and InN. In other embodiments, when the substrate 200 is another substrate 200, such as SiCO ₃ SiC, etc., a planarization layer may be formed on the substrate 200 to eliminate lattice defects. The material of the leveling layer can be selected from a compound consisting of group IIA elements and nitrogen, and specifically, for example, a non-polar AlN material or a non-polar GaN material. By selecting a special crystal axis material or arranging a leveling layer, the generation of lattice torsion in the substrate 200 caused by leading in large current can be avoided, and further piezoelectric cavities are generated to cause heating cracking of the material.

As shown in fig. 15, in some embodiments, to obtain a flat substrate 200 surface, after lapping and polishing the substrate 200 surface, the substrate 200 surface has stress marks that form defects with the semiconductor layer disposed thereon. The crushed crystal particles on the surface of the substrate 200 can be oxidized to form crushed crystal oxide, and then the oxide etching liquid is used for cleaning the crushed crystal oxide, so that a flat substrate 200 surface is obtained. In one embodiment, the substrate 200 is a silicon substrate, for example, and the primary surface processing may be performed by grinding or polishing, etc. to form crushed crystal grains of silicon on the surface of the substrate 200. The generation of the broken crystal particles causes stress marks on crystal lattices, influences the growth of crystals, and therefore needs to be processed. In this embodiment, the influence of the crushed crystal particles can be eliminated by a physical or chemical method. When using a physical method, the substrate 200 may be heated in a preheating chamber to reach a surface temperature of, for example, 300 to 400 degrees, and oxygen or other oxides may be introduced into the chamber to cause oxidation of the crushed crystal particles to form crushed crystal oxides. When a chemical method is used, oxidants such as hydrogen peroxide and the like can be used to react with the crushed crystal particles to generate crushed crystal oxides. During the reaction, the oxidation reaction rate can be increased by raising the temperature, for example, in the range of 40 to 80 ℃. In this embodiment, the crushed crystal oxide is silicon dioxide, and after oxidation, a dense silicon dioxide layer is formed on the surface of the substrate 200, and the substrate 200 having a complete crystal form can be obtained by cleaning with an oxide etching solution, so that the substrate 200 has no crushed crystal defect. In this embodiment, hydrofluoric acid or ammonium sulfide may be used to remove the crushed crystal oxide. In other embodiments, the material of the substrate 200 is not limited to a silicon substrate, and a SiC substrate and other substrates may be selected, and different methods may be used to oxidize the crushed crystal particles and different solutions may be used to remove the crushed crystal oxide, depending on the material of the substrate 200.

As shown in fig. 15, in some embodiments, a buffer layer 201 may be disposed between the first semiconductor layer 203 and the substrate 200 to alleviate lattice mismatch between the first semiconductor layer 203 and the substrate 200, thereby causing dislocation, stacking fault, or void-type defects. The material of the buffer layer 201 may be, but is not limited to, aluminum nitride, gallium nitride, etc., but the buffer layer 201 does not sufficiently solve the lattice mismatch problem, and thus voids are generated. In the present embodiment, by providing the transition metal layer between the substrate 200 and the buffer layer 201, the lattice mismatch problem between the first semiconductor layer 203 and the buffer layer 201 can be further alleviated. The transition metal layer may be made of a group IIA element, for example, aluminum, as a lattice layer. After the transition metal layer is deposited on the substrate 200, the transition metal layer is annealed to form an annealing interface between the surface of the silicon substrate 200 and the transition layer, and during annealing, an inert gas, such as nitrogen, is filled in the cavity. In the annealing process, on the interface between the transition metal layer and the substrate 200, the crystal lattices of metal Al in the transition metal layer and Si in the substrate 200 are converted, so that the defects of dislocation and the like generated by directly growing the buffer layer 201 on the silicon substrate are reduced. The annealing temperature may range, for example, from 400 to 600 degrees, and the specific time may range, for example, from 520 degrees, and the time of the annealing treatment may range, for example, from 5 to 30 minutes.

As shown in FIG. 15, in other embodiments, the buffer layer 201 includes, for example, a periodic aluminum nitride layer and a barrier layer, and the defect of only the aluminum nitride layer as the buffer layer is too largeA barrier layer is periodically inserted into the aluminum nitride layer to block the defects, thereby improving the lattice defects. The temperature of the reaction chamber may be set to, for example, 500to 1000 degrees, and the buffer layer 201 may be grown to a thickness of, for example, 20 to 300nm. Specifically, an aluminum nitride layer having a thickness of, for example, 10 to 25nm may be grown first, and the growth may be stopped. At this time, the surface of the aluminum nitride layer is purged with nitrogen oxide or oxygen for 30 to 60 seconds, and an aluminum oxide layer having a thickness of, for example, 3 to 5nm is formed on the surface of the aluminum nitride layer as a barrier layer. The shielding layer is, for example, spherical alumina, and is disposed at the defect position to block the lattice defect, and as the thickness of the buffer layer 201 increases, the lattice defect is less and less, thereby improving the quality of the buffer layer 201. Wherein the nitrogen oxide may be nitrous oxide (N) ₂ O) or nitrogen dioxide (NO) ₂ ). The aluminum nitride layer is repeatedly grown in this manner, and a barrier layer is formed on the aluminum nitride layer, thereby finally forming the buffer layer 201 having a thickness of, for example, 20 to 300nm. Each of the shielding layers can alleviate lattice defects in the aluminum nitride layer above the shielding layer, so that the higher the thickness of the buffer layer 201 is, the fewer defects are. The thickness of the aluminum nitride layer grown at each time may be set according to the desired thickness of the buffer layer 201, and the present application is not limited thereto.

As shown in fig. 15, in other embodiments, the buffer layer 201 is, for example, a gallium nitride layer. Specifically, the buffer layer 201 can be formed by introducing ammonia gas and trimethylgallium (TMGa) into the reaction chamber at a temperature of, for example, 500to 850 ℃, for example, 500to 550 ℃, and a pressure of the reaction chamber of, for example, 100to 650Torr, for example, 200 to 500Torr, and then growing a layer of gallium nitride with a thickness of, for example, 200 to 400 angstroms or 400 to 600 angstroms on the substrate 200.

As shown in fig. 15, after the buffer layer 201 is formed, an undoped gallium nitride layer 202 may be grown on the buffer layer 201, and specifically, ammonia gas and trimethylgallium (TMGa) may be introduced into the reaction chamber under conditions of a temperature of, for example, 1000 to 1200 ℃, or, for example, 1050 to 1200 ℃, a pressure of the reaction chamber of, for example, 100to 500Torr, and, for example, 200 to 500Torr, and further, a gallium nitride layer having a thickness of, for example, 10000 to 30000 angstroms may be grown on the buffer layer 201 to form the undoped gallium nitride layer 202. By arranging the buffer layer 201 and the undoped gallium nitride layer 202 between the substrate 200 and the first semiconductor layer 203, the problem of lattice mismatch between the substrate 200 and the first semiconductor layer 203 can be alleviated, and the quality of the semiconductor epitaxial structure 20 can be improved.

As shown in fig. 15, the first semiconductor layer 203 is, for example, a first type gallium nitride layer, specifically, an N type gallium nitride layer, and the doping ions of the first semiconductor layer 203 may be silicon. In this embodiment, ammonia, trimethylgallium (TMGa) and Silane (SiH) may be introduced into the reaction chamber at a temperature of, for example, 1000 to 1200 ℃ and, for example, 1050 to 1200 ℃ under a pressure of, for example, 100to 600Torr and, for example, 200 to 500Torr in the reaction chamber ₄ ) Further, an N-type GaN layer having a thickness of, for example, 10000 to 30000 angstroms, or 20000 to 40000 angstroms, is grown on the undoped GaN layer 202. The ion concentration of silicon ions in the first semiconductor layer 203 is, for example, 1 × 10 ¹⁸ ～7×10 ¹⁸ atom/cm ³ And is, for example, 8X 10 ¹⁸ ～2×10 ¹⁹ atoms/cm3. In some embodiments, the first semiconductor layer 203 may be a superlattice structure of an N-type gallium nitride layer doped with silicon ions and an undoped gallium nitride layer, and in other embodiments, the first semiconductor layer 203 may include an N-type gallium nitride layer and a superlattice structure disposed on the N-type gallium nitride.

As shown in fig. 15, the active layer 204 is located on the first semiconductor layer 203, and in the present embodiment, the active layer 204 includes one or more periodic quantum barrier layers and quantum well layers that are alternately formed, and the quantum barrier layers include, for example, a GaN/AlGaN superlattice structure, and the quantum well layers include, for example, inGaN. The thickness of the active layer 204 is, for example, 200nm to 300nm, the thickness of the quantum well layer per cycle is, for example, 3nm to 4nm, and the thickness of the quantum barrier layer per cycle is, for example, 12nm to 16nm, wherein the thickness of the middle GaN constituting the quantum barrier layer is, for example, 1.5nm to 3nm, and the thickness of the middle AlGaN constituting the quantum barrier layer is, for example, 1.5nm to 3nm. The active layer 204 in this embodiment adopts a modulation-doped GaN/AlGaN superlattice structure, which can effectively guide impulse current, so that pulse current is conducted in two-dimensional electron gas of the GaN/AlGaN structure in the transverse direction, the density distribution of the pulse current is more uniform, and the recombination efficiency of electrons and holes can be effectively improved.

As shown in FIG. 15, gaN having a thickness of, for example, 1nm to 3nm can be grown under conditions of a temperature of, for example, 810 to 860 ℃ and a pressure of, for example, 200 to 500Torr, and then AlGaN modulation-doped to a thickness of, for example, 1nm to 3nm can be grown on the GaN. GaN and AlGaN form a superlattice unit structure, and the superlattice unit structure with 2-6 periods grows alternately and continuously to form a quantum barrier layer of the superlattice structure. After the quantum barrier layer is formed, inGaN having a thickness of, for example, 2 to 6nm is grown on the quantum barrier layer to form a quantum well layer, under conditions of, for example, a temperature of 710 to 760 ℃ and a pressure of, for example, 200 to 500Torr, with an indium source such as trimethylindium (TMIn) being changed. The active layer 204 may be formed by alternately and continuously growing the quantum barrier layers and the quantum well layers for 2 to 6 or 9 to 12 periods.

As shown in fig. 15, in some embodiments, the second semiconductor structure 21 may include a second semiconductor layer 205 and a hole injection layer 22, the second semiconductor layer 205 being on the active layer 204, the hole injection layer 22 being on the second semiconductor layer 205. The second semiconductor layer 205 is an electron blocking layer, and may be a second type gallium nitride layer, or may be a second type aluminum gallium nitride layer, or may be made of AlGaN that is not doped with magnesium or is doped with magnesium, and in some embodiments, the second semiconductor layer 205 includes a P-type GaN layer and a P-type AlGaN layer that are cyclically cycled between 3 and 10 periods.

Specifically, as shown in fig. 15, in an embodiment, the second semiconductor layer 205 is a P-type AlGaN layer, alGaN with a thickness of 5 to 10nm is grown on the active layer 204 under a temperature of, for example, 700 to 950 ℃ and a pressure of, for example, 50to 500Torr, so as to form a P-type AlGaN layer, wherein the Mg doping concentration is 0to 1 × 10 ¹⁶ atom/cm3。

Specifically, as shown in fig. 15, in other embodiments, the second semiconductor layer 205 includes a single P-type GaN layer and a single P-type AlGaN layer, and the P-type GaN layer can be formed by growing GaN to a thickness of, for example, 20 to 30nm at a temperature of, for example, 700 to 900 ℃ and a pressure of, for example, 200 to 500Torr, with a Mg doping concentration of 1 × 10 ¹⁹ ～1×10 ²⁰ atom/cm3. Then at warmAlGaN is grown on the P-type GaN layer to a thickness of, for example, 5 to 10nm at a temperature of, for example, 800 to 950 ℃ and a pressure of, for example, 200 to 500Torr, thereby forming a P-type AlGaN layer in which the Mg doping concentration is, for example, 1X 10 ¹⁹ atom/cm3。

Specifically, as shown in fig. 15, in a further embodiment, the second semiconductor layer 205 includes periodic P-type GaN layers and P-type AlGaN layers, and GaN with a thickness of, for example, 5 to 10nm can be grown on the active layer 204 at a temperature of, for example, 700 to 800 ℃ and a pressure of, for example, 200 to 500Torr to form a P-type GaN layer, in which the Mg doping concentration is 1 × 10E ¹⁹ atom/cm3. AlGaN is grown on the P-type GaN layer at a temperature of, for example, 700 to 950 ℃ and a pressure of, for example, 50to 500Torr, to form a P-type AlGaN layer with a thickness of, for example, 5 to 10nm, wherein the Mg doping concentration is 0to 1X 10E16 atom/cm3. And alternately and continuously growing the P-type GaN layer and the P-type AlGaN layer for 3-10 periods.

As shown In fig. 15, the hole injection layer 22 is located on the second semiconductor layer 205, and the hole injection layer 22 includes non-or low-doped In _x Ga _y N layer, and/or doping with In _x Ga _y The N layer, i.e., the hole injection layer 22, includes In _x Ga _y And x is more than or equal to 0 and less than or equal to 1, and y is more than or equal to 0 and less than or equal to 1. Wherein is not doped with In _x Ga _y The N layer is In not doped with other ions _x Ga _y N layer doped with In _x Ga _y N layer made of, for example, mg-doped In _x Ga _y And N is prepared.

As shown in fig. 15, in one embodiment, the second semiconductor layer 205 is, for example, a P-type aluminum gallium nitride layer, the hole injection layer 22 disposed thereon includes at least a first doped layer 206 and a second doped layer 207, the first doped layer 206 is disposed on the second semiconductor layer 205, and the second doped layer 207 is disposed on the first doped layer 206. The first doping layer 206 is a non-or low-doped InxGayN layer, and the doping concentration of the first doping layer 206 is, for example, a first doping concentration, the second doping layer 207 is a doped InxGayN layer, and the doping concentration of the second doping layer 207 is, for example, a second doping concentration, and the second semiconductor layer 205 has, for example, a third doping concentration. Wherein the first doping concentration is less than the second doping concentration, and the third doping concentration is less than the second doping concentrationAnd the first doping concentration is in the range of 0to 1 x 10 ¹⁹ atom/cm ³ . The thickness of the first doped layer 206 is less than the thickness of the second doped layer 207, and the thickness of the first doped layer 206 is, for example, 40% to 50% of the thickness of the second doped layer 207, and specifically, 30% of the thickness of the second doped layer 207.

As shown in fig. 15, in another embodiment of the present invention, the hole injection layer 22 includes a first doped layer 206 and a second doped layer 207, and the first doped layer 206 is an undoped InxGayN layer, and the second doped layer 207 is a doped InxGayN layer, i.e. the first doping concentration of the first doped layer 206 is zero, and the second doped layer 207 is a magnesium-doped InxGayN layer.

As shown in fig. 15, in other embodiments, the hole injection layer 22 further includes a third doped layer, the third doped layer is located on the second doped layer 207, the third doped layer is, for example, inxGayN doped with magnesium, and the fourth doping concentration of the third doped layer is greater than the second doping concentration.

As shown in fig. 15, in one embodiment, the first doped layer 206 is an undoped InxGayN layer, the second doped layer 207 is a low doped InxGayN layer, and the third doped layer is a doped InxGayN layer. GaN is grown to a thickness of, for example, 2 to 5nm at a temperature of, for example, 800 to 950 c and a pressure of, for example, 200 to 500Torr, and the undoped InxGayN layer is formed as the first doping layer 206. Next, gaN is grown to a thickness of, for example, 5 to 50nm at a temperature of, for example, 800 to 950 ℃ and a pressure of, for example, 200 to 500Torr, with a doping concentration of, for example, 1X 10 of magnesium ¹⁶ ～1×10 ¹⁷ atom/cm3, and forming a low-doped InxGayN layer as a second doped layer 207. Finally, gaN is grown to a thickness of, for example, 10 to 20nm, at a temperature of, for example, 800 to 950 ℃ and a pressure of, for example, 200 to 500Torr, with a doping concentration of magnesium of 1X 10 ¹⁸ ～1×10 ¹⁹ and (4) atom/cm < 3 >, and forming a doped InxGayN layer as a third doped layer.

As shown In FIG. 15, in another embodiment of the present invention, in is doped _x Ga _y The N layer includes but is not limited to N layers of In _x1 Ga _y1 N、 In _x2 Ga _y2 N、In _x3 Ga _y3 Superposition of N, orIs alternating In _x1 Ga _y1 N and In _x2 Ga _y2 N cycles of N periods, where N is ≧ 1, X3<X2<X1≤1，Xn<...<X3<X2<X1 is less than or equal to 1. In one embodiment, N is equal to 3, X1 is equal to 1, X2 is equal to 0.2, and X3 is equal to 0.05, i.e., the hole injection layer 22 includes InN and In sequentially disposed _0.2 Ga _0.8 N、In _0.05 Ga _0.95 And (3) doping the N layer. The utility model discloses in hole injection layer 22 can effectively improve epitaxial structure's hole concentration, improve luminous efficacy.

As shown in fig. 17, in another embodiment of the present invention, a semiconductor epitaxial structure 20 with high wavelength stability is further provided, and the semiconductor epitaxial structure 20 is a green light epitaxial structure, and the active layer 204 includes, for example, a stress relief layer 208, a first active layer 209 and a second active layer 210, and the first active layer 209 is located on the stress relief layer 208, and the second active layer 210 is located on the first active layer 209.

As shown in FIG. 17, the material of the stress relieving layer 208 is InxGa (1-x) N and GaN, wherein 0.17<x<0.35 and GaN is doped with silicon ions, the doping concentration of the silicon ions is, for example, a, and a ranges from 5 × 10 ¹⁷ ～1×10 ¹⁸ atoms/cm ³ And the thickness of the stress release layer 208 is 3-40 nm. Specifically, the stress release layer 208 may include a quantum well layer and a quantum barrier layer that are periodically cycled, and the growth period of the stress release layer 208 is, for example, 2 to 6, and is, for example, 3. In this embodiment, a quantum well layer can be formed by growing a layer of InGaN of 1nm to 3nm on the first semiconductor layer 203 by introducing ammonia (NH 3) of 30000 to 60000sccm, triethylgallium (TEGa) of 50to 100sccm, trimethylindium (TMIn) of 500to 1000sccm, and nitrogen (N2) of 100to 130L/min at a temperature of 750 ℃ to 950 ℃ and a pressure of the reaction chamber of 200 Torr to 500Torr, for example. Then, ammonia gas (NH) may be introduced at a flow rate of 30000 to 60000sccm under the conditions that the temperature is, for example, 750 to 950 ℃ and the pressure in the reaction chamber is, for example, 200 to 500Torr ₃ ) 100-200 sccm trimethyl gallium (TMGa), 100-130L/min nitrogen (N2) and 1-2sccm Silane (SiH) ₄ ) Further growing an N-type GaN layer of 30-40 nm on the quantum well layerAnd forming a quantum barrier layer. And repeatedly growing the quantum well layer and the quantum barrier layer for 2-6 periods to obtain the stress release layer 208.

As shown in fig. 17, the first active layer 209 includes a barrier layer and a well layer for, for example, 3 to 8 cycle periods, specifically, 5, for example. In some embodiments, the material of the barrier layer is AlzGa (1-z) N, for example, and 0 ≦ z<0.3, the material of the well layer is, for example, inyGa (1-y) N, and 0.17<y<0.4. Wherein the barrier layer is doped with silicon ions with a doping concentration of b and a>b and b ranges from 5X 10 ¹⁶ ～1×10 ¹⁷ atoms/cm ³ . In other embodiments, the material of the barrier layer may also be GaN, or a superlattice layer of 2 to 6 periods of alternating growth of AlGaN and GaN, and the thickness L1 of the barrier layer is, for example, 70 to 150 angstroms, and, for example, 120 angstroms. In this embodiment, ammonia gas (NH) may be introduced into the reaction chamber at a flow rate of 50000 to 70000sccm under conditions of a temperature of, for example, 750 to 900 ℃ and a pressure of the reaction chamber of, for example, 200 to 500Torr ₃ ) 200-1000sccm of triethylgallium (TEGa), 1-2sccm of Silane (SiH) ₄ ) And 100-130L/min of nitrogen (N) ₂ ) And further growing a layer of 1 nm-3 nm N-type GaN on the stress release layer 208 to form a barrier layer. Further, the temperature is, for example, 710 to 760 ℃. For example, under the condition that the reaction chamber pressure is 200 to 500Torr, inGaN with a thickness of 2 to 6nm is grown on the barrier layer to form a well layer. The first active layer 209 may be formed by repeatedly growing the barrier layer and the well layer for 3 to 8 periods.

As shown In FIG. 17, the second active layer 210 includes In cyclically cycled for 2 to 6 periods _u Ga _1-u N and GaN, the period is, for example, 3, and In is In the second active layer 210 _u Ga _1-u Indium content of N is 0.17<u<0.40, the GaN of the second active layer 210 is doped with silicon ions having a doping concentration of c, a>c>b, c range is 5X 10 ¹⁶ -1×10 ¹⁷ atoms/cm3 and c may be 1.4 times that of b. In an embodiment of the present invention, the second active layer 210 includes a quantum well layer made of N-type GaN, and a quantum barrier layer made of InGaN. In other embodiments, the quantum well layer may also be undopedA superlattice layer of GaN of Si and GaN of the Si doped layer. In this embodiment, for example, under the conditions that the temperature is, for example, 750 to 900 ℃ and the pressure of the reaction chamber is, for example, 200 to 500Torr, ammonia gas (NH) is desirably introduced into the reaction chamber at a flow rate of, for example, 50000 to 70000sccm ₃ ) 200-1000sccm of triethylgallium (TEGa), 1-2sccm of Silane (SiH) ₄ ) And 100-130L/min nitrogen (N) ₂ ) Further, by growing a layer of N-type GaN of 1nm to 3nm on the first active layer 209, a quantum well layer can be formed, the quantum well layer having a thickness L2 in the range of 70 to 150 angstroms and L1>L2=100 angstroms. Further, an InGaN layer with a thickness of 2 to 6nm is grown on the quantum barrier layer under the conditions that the temperature is 710 to 760 ℃ for example and the pressure of the reaction chamber is 200 to 500Torr for example, to form a quantum well layer. The second active layer 210 may be formed by repeatedly growing the quantum barrier layer and the quantum well layer for 2 to 6 periods.

As shown in fig. 17, the second semiconductor structure 21 includes a second semiconductor layer 205, a third semiconductor layer 211, and a fourth semiconductor layer 212, and the third semiconductor layer 211 is located on the second semiconductor layer 205 and the fourth semiconductor layer 212 is located on the third semiconductor layer 211. The second semiconductor layer 205 is a P-type AlGaN layer, the third semiconductor layer 211 and the fourth semiconductor layer 212 are P-type GaN layers, for example, gaN layers doped with Mg, and the doping concentration of the fourth semiconductor layer 212 is greater than that of the third semiconductor layer 211. In this embodiment, alGaN having a thickness of 5 to 10nm may be grown on the active layer 204 under conditions of a temperature of, for example, 700 to 800 ℃ and a reaction chamber pressure of, for example, 200 to 500Torr to form the second semiconductor layer 205. Wherein the doping concentration of Mg in the second semiconductor layer 205 is 1 × 10 ¹⁸ ～1×10 ¹⁹ atom/cm3. Thereafter, gaN is grown to a thickness of 20 to 30nm under conditions of a temperature of, for example, 800 to 950 ℃ and a reaction chamber pressure of, for example, 200 to 500Torr, thereby forming the third semiconductor layer 211. Wherein the doping concentration of Mg is 1 × 10 ¹⁹ ～1×10 ²⁰ atom/cm3. Finally, gaN is grown to a thickness of 10 to 20nm under conditions of a temperature of, for example, 800 to 950 ℃ and a reaction chamber pressure of, for example, 200 to 500Torr, thereby forming the fourth semiconductor layer 212. Wherein the doping concentration of Mg is 1 × 10 ¹⁸ ～1×10 ¹⁹ atom/cm3。

In another embodiment of the present invention, as shown in fig. 18, in order to ensure that the formed led does not flicker due to too fast reaction, a resistance layer 214 with a special structure can be disposed between the first semiconductor layer 203 and the active layer 204, so as to delay the turn-off time of the diode. The semiconductor epitaxial structure 20 with the resistance layer 214 with a special structure can be made into a light emitting diode, and can be used together with an energy-saving power supply, so that the total power-on time can be reduced, the energy consumption can be saved, human eyes can feel the same brightness, the influence caused by flicker can be reduced, and the harm of strong light to human eyes can be further reduced.

As shown in fig. 18, the first semiconductor layer 203 is a gallium nitride layer 203, a superlattice structure 213 is provided on the gallium nitride layer 203, and a resistive layer 214 is provided on the gallium nitride layer 203 and between the gallium nitride layer 203 and the superlattice structure 213. In the present embodiment, the gallium nitride layer 203 includes, for example, a lightly doped N-type gallium nitride layer 203a and a heavily doped N-type gallium nitride layer 203b. A resistive layer 214 is disposed on the heavily doped N-type gallium nitride layer 203b, a superlattice structure 213 is disposed on the resistive layer 214, and the active layer 204 is disposed on the superlattice structure 213. The resistance layer 214 provided in this embodiment can slow down the discharging speed of the finally formed led, prolong the discharging time of the led, and avoid the flickering of the led caused by unstable power supply or low duty ratio.

As shown in fig. 18, the material of the resistive layer 214 is, for example, alxGa1-xN, and x is less than 0.15, and the thickness of the resistive layer 214 is, for example, 50to 200nm, which can prevent the resistive layer 214 from being too thin to control growth and the resistive layer 214 from cracking. A plurality of openings 215 are etched in the photoresist layer, the direction of the openings 215 is parallel to the growth direction of the resistive layer 214, the diameter of the openings 215 is, for example, 3-20 um, and the distance between adjacent openings 215 is, for example, 3-10 um. In this embodiment, the resistive layer 214 may be formed by introducing triethylgallium (TEGa), trimethylaluminum (TMAL) and ammonia (NH 3) into the reaction chamber under the conditions of a temperature of, for example, 700 to 900 and a pressure of, for example, 500mbar, and by using a Metal Organic Chemical Vapor Deposition (MOCVD) method. After the resistive layer 214 is formed, the resistive layer 214 is etched to form an opening 215 by using an etching method of inductively coupled plasma, and the opening 215 penetrates through the resistive layer 214 and contacts the heavily doped N-type gan layer 203b.

As shown in fig. 19, C is the equivalent capacitance of the semiconductor epitaxial structure 20 when the resistive layer 214 is not added, and R is the equivalent circuit of the semiconductor epitaxial structure 20 after etching ₀ Is the equivalent resistance, R, of the semiconductor epitaxial structure 20 without the addition of the resistive layer 214 _L Is the equivalent resistance of the resistive layer 214, and R _L The number or diameter of the openings in the resistive layer 214 can be adjusted, E being the voltage across the semiconductor epitaxial structure 20. The discharge equation of the capacitor is: vt = E × (exp (-t/R × C)), the discharge time of the capacitor is: t = RC × Ln [ E/Vt]And R = R ₀ +R _L . As can be seen from the above formula, the length of the discharge time is proportional to the resistance R, and the larger the resistance R is, the more difficult the electron flow is, and the longer the discharge time is. Can adjust R according to actual requirements _L I.e., the equivalent resistance of the resistive layer 214 can be adjusted by the number and diameter of the openings 215, and the larger the number and diameter of the openings, the smaller the equivalent resistance of the resistive layer 214, and the openings can also restrict the current flow.

The high quality thin film formed in the present application can be applied to various semiconductor structures, electronic components, or electronic devices, such as switching elements, power elements, radio frequency elements, light emitting diodes, micro light emitting diodes, display panels, mobile phones, watches, notebook computers, projection devices, charging piles, virtual Reality (VR) devices, augmented Reality (AR) devices, portable electronic devices, game machines, or other electronic devices.

As shown in fig. 20, the present embodiment and the following embodiments of the present invention are applicable to a micro light emitting diode, which includes a micro led, a miniLED, or other light emitting diodes. The micro light emitting diode comprises a substrate 200, a semiconductor epitaxial structure 20 arranged on the substrate 200, wherein the semiconductor epitaxial structure 20 comprises a first semiconductor layer 203, an active layer 204 and a second semiconductor structure 21, and the micro light emitting diode further comprises a first electrode 226 connected with the first semiconductor layer 203 and a second electrode 227 connected with the second semiconductor structure 21. And the substrate 200 is, for example, a sapphire substrate 200, the semiconductor epitaxial structure 20 may be the semiconductor epitaxial structure 20 shown in fig. 15, 16 or 17. In some embodiments, as shown in fig. 15 and 16, a notch 23 may be disposed on one side of the semiconductor epitaxial structure 20, the notch 23 is disposed on one side of the semiconductor epitaxial structure 20, and the bottom of the notch 23 is in contact with the first semiconductor layer 203. In some embodiments, the gap 23 is in contact with the surface of the first semiconductor layer 203, and in other embodiments, the second semiconductor structure 21, the active layer 204, and a portion of the first semiconductor layer 203 may be etched to form the gap 23.

As shown in fig. 20, a transparent conductive layer 220 is formed on the second semiconductor structure 21, the transparent conductive layer 220 covers the second semiconductor structure 21, and the transparent conductive layer 220 may be made of indium tin oxide, gallium zinc oxide, or indium zinc oxide. In some embodiments, the transparent conductive layer 220 covers a portion of the second semiconductor structure 21, and the transparent conductive layer 220 and the second semiconductor layer form a step 228 on both sides of the transparent conductive layer 220. In other embodiments, the transparent conductive layer 220 may completely cover the second semiconductor structure 21. When the semiconductor epitaxial structure 20 is provided with the notch 23, the transparent conductive layer 220 may cover the first semiconductor layer 203.

As shown in fig. 20, after forming the transparent conductive layer 220, metal materials, such as a titanium/titanium nitride barrier layer and metal tungsten, may be deposited on the first semiconductor layer 203 and the transparent conductive layer 220, respectively, a first conductive plug 221 is formed on the first semiconductor layer 203, and a second conductive plug 222 is formed on the transparent conductive layer 220. The first conductive plug 221 and the second conductive plug 222 are flush, and the first conductive plug 221 covers a portion of the first semiconductor layer 203, and the second conductive plug 222 covers a portion of the transparent conductive layer 220. In some embodiments, an opening may be opened at one side of the semiconductor epitaxial structure 20, a bottom wall of the opening is in contact with the first semiconductor layer 203, an insulating material is laid on a sidewall of the opening, and the first conductive plug 221 is formed in the opening and on the opening. In other embodiments, the semiconductor epitaxial structure 20 is provided with the gap 23, and the first conductive plug 221 may be directly formed on the gap 23.

As shown in fig. 20, after the first and second

conductive plugs

221 and 222 are formed, a reflective layer 223 and a protective layer 224 are sequentially deposited on the first semiconductor layer 203 and the transparent conductive layer 220. The reflective layer 223 covers the transparent conductive layer 220 and the step 228, and exposes a portion of the first and second

conductive plugs

221 and 222. The protective layer 224 covers the reflective layer 223, and part or all of the first and second

conductive plugs

221 and 222. After the reflective layer 223 and the protective layer 224 are formed, the protective layer 224, the reflective layer 223, and the semiconductor epitaxial structure 20 outside the diode chip are etched to form a trench 229. An insulating layer 225 is deposited within the trench 229 and on the protective layer 224, the insulating layer 225 completely covering the first conductive plug 221 and the second conductive plug 222. Etching the insulating layer 225 and the protection layer 224 to form an opening above the first conductive plug 221 and the second conductive plug 222, wherein the opening exposes a portion of the first conductive plug 221 and a portion of the second conductive plug 222, and the area of the opening is larger than the radial dimension of the first conductive plug 221 and the second conductive plug 222, depositing metal in the opening to form a first electrode 226 connected to the first conductive plug 221 and a second electrode 227 connected to the second conductive plug 222. And then laser cutting and splitting are carried out, and the micro light-emitting diode is formed after point division is finished.

As shown in fig. 21, other structures may be added to the light emitting diode to change the light emitting direction of the micro light emitting diode, and specifically, the light emitting direction of the micro light emitting diode may be changed according to specific requirements. When the micro light-emitting diode is used as backlight, in order to reduce the light mixing distance and further realize the ultrathin requirements of electronic equipment such as a display and the like, the micro light-emitting diode with a large angle can be arranged. In one embodiment, a light diffusion layer 230 may be disposed on the substrate 200 of the micro light emitting diode and on a side opposite to the semiconductor epitaxial structure 20 to increase the light emitting angle of the micro light emitting diode, so that the angle of the micro light emitting diode is greater than or equal to 160 degrees. For convenience of description, the present application defines a side of the semiconductor epitaxial structure 20 as an upper surface of the substrate 200, and defines a side of the substrate 200 opposite to the semiconductor epitaxial structure 20 as a lower surface.

As shown in fig. 21, the light dispersion laminate 230 includes a light guiding layer 231, a first reflective layer 232, a light oscillating layer 233, and a second reflective layer 234 disposed on the lower surface of the substrate 200. Specifically, the light guide layer 231 covers the lower surface of the light guide layer 231, and the refractive index of the light guide layer 231 is the same as that of the substrate 200, so that light is ensured not to be deflected on the light guide layer 231. The thickness of the light-guiding layer 231 can be set according to the wavelength of light emitted by the light-emitting layer and the thickness of the light-guiding layer 231, and the thickness of the light-guiding layer 231 conforms to the following relationship: the thickness of the light-introducing layer 231 = wavelength/4 × refractive index. In some embodiments, the substrate 200 is a sapphire substrate 200, the refractive index of sapphire is 1.77, and the light-guiding layer 231 is made of alumina (Al) with the same refractive index as sapphire ₂ O ₃ ) Or magnesium oxide (MgO). The thickness of the light-introducing layer 231 is specifically, for example, 10 to 200nm, and further, for example, 60 to 80nm. In other embodiments, when the substrate 200 is made of other materials, the material of the light guiding layer 231 can be selected correspondingly, and the thickness of the light guiding layer 231 can be set correspondingly.

As shown in fig. 21, the first reflective layer 232 is located on a side of the light guiding layer 231 opposite to the substrate 200, and the first reflective layer 232 covers the light guiding layer 231. The first reflective layer 232 is a forward reflective layer 223, allowing light emitted from the substrate 200 to pass through the first reflective layer 232, and light emitted from the first reflective layer 232 in the direction opposite to the substrate 200 will be reflected by the first reflective layer 232. In some embodiments, the first reflective layer 232 is a periodically cycled titanium oxide (Ti) ₂ O ₃ ) Layer and silicon dioxide (SiO) ₂ ) A layer, and the first reflective layer 232 includes, for example, 4 to 6 periods of Ti ₂ O ₃ And SiO ₂ And, for example, comprises 5 periods of Ti ₂ O ₃ And SiO ₂ . Wherein the titanium sesquioxide layer covers the light guiding layer 231, and the thickness of the titanium sesquioxide layer is, for example, 55-60 nm, and the thickness of the silicon dioxide layer covers the titanium sesquioxide layer, and the thickness of the silicon dioxide layer is, for example, 90-100 nm.

As shown in fig. 21, the light oscillation layer 233 is disposed on a side of the first reflective layer 232 opposite to the light guiding layer 231, and the light oscillation layer 233 covers the first reflective layer 232. The refractive index of the light oscillating layer 233 is less than that of the substrate 200, and in some embodiments,the optical oscillation layer 233 may be made of silicon dioxide (SiO) with a refractive index of 1.46 ₂ ) Magnesium fluoride (MgF) with refractive index of 1.38 ₂ ) Titanium nitride (TiN) having a refractive index of 1.351 or calcium fluoride (CaF) having a refractive index of 1.433 ₂ ) One or more of them. The thickness of the light oscillation layer 233 is, for example, 100to 500nm, and further, for example, 300 to 400nm, so that it can be avoided that the light oscillation layer 233 is too thick and is easy to crack, and the oscillation layer is too thin, which results in too large brightness loss, and the light intensity finally emitted by the micro light emitting diode is weak.

As shown in fig. 21, the second reflective layer 234 is disposed on a side of the light oscillating layer 233 opposite to the first reflective layer 232, and the second reflective layer 234 covers the light oscillating layer 233. The second reflective layer 234 is a reflective layer 223, and light emitted from the second reflective layer 234 in the direction opposite to the substrate 200 passes through the second reflective layer 234 and light emitted from the substrate 200 is reflected by the second reflective layer 234. In some embodiments, the second reflective layer 234 is periodically regrown silicon dioxide (SiO) ₂ ) Layer and titanium oxide (Ti) ₂ O ₃ ) Layer, and the second reflective layer 234 includes, for example, 2 to 3 periods of SiO ₂ And Ti ₂ O ₃ The thickness of the silicon dioxide layer is, for example, 90-100 nm, the titanium oxide layer covers the silicon dioxide layer, and the thickness of the titanium oxide layer is, for example, 55-60 nm.

As shown in fig. 21, by disposing the light diffusion stack 230 on the lower surface of the substrate 200 of the micro light emitting diode, after the light emitted from the semiconductor epitaxial structure 20 sequentially passes through the light guiding layer 231, the first reflective layer 232, and the light oscillating layer 233, the light is reflected by the second reflective layer 234, and is deflected in the light oscillating layer 233, and when the light is reflected or the first reflective layer 232, the light is reflected by the first reflective layer 232, and finally overflows from the side of the light oscillating layer 233. Resulting in the final emitted light making an angle with the plane of the substrate 200 of more than 160 degrees.

As shown in fig. 22, in another embodiment, in order to avoid the light emitting angle of the micro light emitting diodes from being too large when forming the display device or the illumination device, the colors of the adjacent micro light emitting diodes with different colors interfere with each other. The light emitting angle of the micro led can be reduced by adding the shielding layer 235 on the outer side of the substrate 200. In this embodiment, the light emitting angle can be reduced by forming the shielding layer 235 on the outer side of the micro light emitting diode.

As shown in fig. 22, the shielding layer 235 is disposed outside the micro light emitting diode, and specifically, as shown in fig. 23, 24 and 25, the shielding layer 235 is disposed outside the substrate 200 and attached to the sidewall of the substrate 200. The shielding layer 235 may cover one or more sides of the substrate 200, and the light emitting range of the micro led may be changed by disposing the shielding layer 235 at different positions on the sidewall of the substrate 200. In some embodiments, as shown in fig. 24, the shielding layer 235 may cover, for example, two opposite sides of the substrate 200, in which case the light emitting angle of the micro light emitting diode ranges from 90 degrees to 115 degrees, for example, and the maximum light emitting angle is 115 degrees, for example. In other embodiments, as shown in fig. 25, the shielding layer 235 may cover, for example, four sides of the substrate 200, in which case the light emitting angle of the micro light emitting diode ranges from, for example, 90 degrees to 105 degrees, and the maximum light emitting angle is, for example, 105 degrees. In other embodiments, the shielding layer 235 covers, for example, one side of the substrate 200, in which case the light emitting angle of the micro light emitting diode ranges from 90 degrees to 120 degrees, for example, and the maximum light emitting angle is 120 degrees, for example. The shielding layer 235 covers, for example, three sides of the substrate 200, in which case the light emitting angle of the micro light emitting diode ranges from 90 degrees to 110 degrees, and the maximum light emitting angle is, for example, 110 degrees.

As shown in fig. 23, the shielding layer 235 includes a reducing layer 236 and a plating layer 237, wherein the reducing layer 236 is formed by re-crystallizing and roughening the surface of the sidewall of the substrate 200. In the present embodiment, the substrate 200 is, for example, a sapphire substrate 200, and the sidewalls of the substrate 200 can be recrystallized and roughened by laser scribing. Wherein the light wavelength of the laser is, for example, 800 to 1200nm, and the sapphire substrate 200 (Al) is irradiated with the laser ₂ O ₃ ) Recrystallized to Al or AlO, and the sidewall surface of the substrate 200 after final recrystallization may be naturally roughened. And the Al or AlO formed by recrystallization is a light-tight layer and can reflect light, and the naturally roughened side wall of the substrate 200 can also increase reflection.

As shown in fig. 22 and 23, the film coating 237 is covered on the reducing layer 236, and may be, for example, under vacuum and under pressure of, for example, 1 × 10 ³ ～9×10 ³ the plating layer 237 is formed on the reduced layer 236 by vapor deposition or sputtering under torr conditions. Wherein the coating 237 comprises a plurality of composite layers, such as a first composite layer 238 and a second composite layer 239, and the second composite layer 239 overlies the first composite layer 238. The plating layer 237 may be a metal layer combination layer or an oxide layer combination layer. In some embodiments, the material of the first combined layer 238 is Al, or Al and Ni, the material of the second combined layer 239 is Ti or Pt, and the thickness of the plating layer 237 is, for example, 20 to 300nm. In other embodiments, the material of the first combination layer 238 is SiO ₂ Or MgF ₂ The material of the second combination layer 239 is Ti ₂ O ₅ Or SiNx, and the thickness of the plating layer 237 is, for example, 50to 100nm. Where the coating 237 is an oxide composition, the coating 237 may include a plurality of cyclically disposed first and second composition layers 238 and 239.

As shown in fig. 26, in some embodiments, during the crystal growth of the semiconductor epitaxial structure, the surface of the semiconductor epitaxial structure may have an uneven defect, resulting in poor effect of the reflective layer 223. The micro light-emitting diode provided by the embodiment can fill and level up the surface of a semiconductor epitaxial structure, can ensure the stress balance of the whole film layer, avoids the cracking of a coating layer caused by tensile stress, and can also increase the light-emitting effect.

As shown in fig. 26, there is a defect of unevenness on the surface of the semiconductor epitaxial structure 20 in contact with the transparent conductive layer 220, and on the basis of the micro light emitting diode shown in fig. 20, 21 or 22, a composite filling and leveling layer 240 is disposed between the transparent conductive layer 220 and the reflective layer 223 to improve the defect on the semiconductor epitaxial structure, and a bonding layer 243 is disposed between the protective layer 224 and the insulating layer 225 to ensure the stress balance of the whole film layer and avoid the cracking of the coating film due to tension.

As shown in fig. 26 to 27, the filling layer 240 is located on a side of the transparent conductive layer 220 opposite to the semiconductor epitaxial structure, and covers the transparent conductive layer 220. The leveling layer 240 is transparent and non-conductive, and the particles in the leveling layer 240 are coarse first and then fine. Specifically, the filling-up layer 240 includes a first filling-up layer 240a and a second filling-up layer 240b, and the first filling-up layer 240a covers the transparent conductive layer 220, and the thickness of the first filling-up layer 240a is, for example, 200 to 500nm, and specifically, 250nm or 300nm, so as to completely cover the defects on the semiconductor epitaxial structure. The second filling-up layer 240b covers the first filling-up layer 240a, and the thickness of the second filling-up layer 240b is, for example, 50-300 nm, so as to fill up gaps between particles in the first filling-up layer 240 a.

Referring to fig. 26 to 27, in the present embodiment, a filling-up layer 240 may be formed on the transparent conductive layer 220 by PECVD deposition or evaporation, wherein the first filling-up layer 240a has a particle density of, for example, 3 to 4g/cm ³ And the material of the first filling-up layer 240a is, for example, alumina (Al) ₂ O ₃ ) Or magnesium fluoride (MgF) ₃ ) The density of the alumina is 3.5-3.9 g/cm ³ The density of the magnesium fluoride is 3.148g/cm ³ . The second leveling layer 240b has a particle density of, for example, 1.5 to 3g/cm ³ And the material of the second filling-up layer 240b is, for example, silicon dioxide (SiO) ₂ ) Or silicon nitride (SiN) with a density of 2.2g/cm ³ The density of the silicon nitride is 1.8-2.7 g/cm ³ . The filling layer 240 uses coarse particles to form the first filling layer 240a, the plating speed is high, and then fine particles are filled to form the second filling layer 240b, so that no hole is formed, and the film layer has good quality and is not easy to fall off.

As shown in fig. 26 to fig. 27, a plurality of openings 241 are disposed on the filling layer 240, and the plurality of openings 241 are disposed in an array. For example, the opening 241 may be etched by using a BOE etching solution or etched by using an Inductively Coupled Plasma (ICP) dry etching method. The opening 241 is disposed in a column shape and penetrates through the first and

second filling layers

240a and 240b, wherein the cross section of the opening 241 may be circular, square, polygonal or other shapes. In this embodiment, the aperture of the opening 241 is, for example, 3 to 5um, and the interval between adjacent openings 241 is, for example, 3 to 5um. The aperture and the interval between the adjacent openings 241 can prevent the openings 241 from being too small in distance to meet the process requirement, and simultaneously prevent the openings from being too large and the contact area between the leveling layer 240 and the conductive layer from being too small to cause too high voltage difference between the two sides of the leveling layer 240.

As shown in fig. 26, the protective layer 224 covers the reflective layer 223, the lamination layer 243 covers the protective layer 224, and the insulating layer 225 covers the lamination layer 243. The lamination layer 243 comprises a first lamination layer and a second lamination layer, with the second lamination layer overlying the first lamination layer. The ratio of the thicknesses of the first lamination layer and the second lamination layer is, for example, 3:8. and the thickness of the first lamination layer and the second lamination layer is, for example, 30 to 600nm, problems such as the lamination layer 243 being too thin to function and cracking occurring when it is too thick can be avoided. In some embodiments, the lamination layers 243 include, for example, 1 first lamination layer and, for example, 1 second lamination layer. In other embodiments, the lamination layers 243 include a plurality of periodic cycles of first and second lamination layers.

As shown in fig. 26 and 27, a bonding layer 243 may be formed on the transparent conductive layer 220 by PECVD deposition or evaporation, wherein the material of the first bonding layer is, for example, silicon dioxide (SiO) ₂ ) The material of the second lamination layer is, for example, titanium dioxide (TiO) ₂ ) Or Ti ₂ O ₅ 。

As shown in fig. 26 and 28, when the micro light emitting diode is mounted on the substrate 244, the first electrode 226 may be bonded to the substrate 244 through the first bonding pad 245, and the second electrode 227 may be bonded to the substrate 244 through the second bonding pad 246. When the substrate 244 exhibits compressive stress and the thin film provided on the substrate 244 exhibits tensile stress, both sides of the substrate 244 and the thin film may warp toward the thin film side. When the substrate 244 exhibits tensile stress and the thin film provided on the substrate 244 exhibits compressive stress, both sides of the substrate 244 and the thin film may warp toward the substrate 244 side. In the present embodiment, the substrate 244 may exhibit a small tensile stress at room temperature, and the stress of the film of the bonding layer 243 varies as follows: second lamination layer (TiO) ₂ Or Ti ₂ O ₅ ) At a thickness of 300nm, a tensile stress at room temperature, for example 114MPa, first bonding layer (SiO) ₂ ) At a thickness of 400nm, exhibits a compressive stress at room temperature, for example-56 MPa. Since the substrate 244 itself is tensile stress in another direction, the thickness of the first and second bonding layers is set to be 3The point compressive stress may counteract the tensile stress exhibited by the substrate 244. At other temperatures, the substrate 244 may warp too much due to stress, and the stress of the film may be adjusted to balance the film on the substrate 244 and the film on the substrate 244.

As shown in fig. 29 and 30, in order to meet the requirement of high efficiency and energy saving of the micro-led, the brightness of the flip chip is required to be higher and higher. In the crystal growth process of the semiconductor epitaxial structure, defects are easily formed on the surface, and the surface is uneven, so that a complete mirror surface cannot be formed after a reflector is plated on the rear surface, dispersion and light concentration are caused, and the light efficiency is poor after the reflector is packaged into white light. The flip-chip micro led provided in this embodiment, as shown in fig. 29 and fig. 30, utilizes a special composite filling layer 240 to fill the epitaxial surface and increase the vertical light reflection capability. Meanwhile, a laminated layer 243 is used to ensure the stress balance of the whole film layer and avoid the cracking of the coated layer 237 caused by tensile stress, and the light vertical reflection capability required by the flip chip is enhanced by the two designs so as to increase the light output effect.

As shown in fig. 31, the micro light emitting diode needs to be soldered on a circuit through a pad during use, and during soldering, a void is easily generated between the pad and an electrode, so that a metal laminate 250 with a special shape can be formed on the electrode to increase the yield of the solderability of the electrode. In the present embodiment, the metal stack 250 has a thickness of, for example, 20 to 100um, and includes a dielectric layer 251 and a flexible metal layer 252, the dielectric layer 251 is disposed on the first electrode 226 and the second electrode 227, and the flexible metal layer 252 is disposed on the dielectric layer 251. Specifically, the dielectric layer 251 is made of an alloy, and includes, for example, a nickel (Ni) layer, and an alloy of gold (Au) and tin (Sn). The dielectric layer 251 can be formed by first depositing or sputtering a layer of ni with a thickness of, for example, 10-15 nm on the first electrode 226 and the second electrode 227 under yellow light conditions, and then depositing or sputtering a layer of au or sn alloy with a thickness of, for example, 30-1000 nm on the ni, wherein the ratio of au to sn in the au or sn alloy is, for example, 80:20. the thickness of the dielectric layer 251 is the same at each point, and the whole dielectric layer is columnar, specifically, can be columnar. A dielectric layer 251 is formed on the first electrode 226 and the second electrode 227 to prevent the soft metal layer 252 from diffusing.

As shown in fig. 31, the soft metal layer 252 is disposed on the dielectric layer 251 and covers the dielectric layer 251. The soft metal layer 252 is made of metal or alloy, such as gold (Au), tin (Sn), or silver (Ag), or made of alloy of tin (Sn). The soft metal layer 252 can be formed by plating or sputtering a layer of metal or alloy with a thickness of 20-100 um on the dielectric layer under yellow light. The radius of the flexible metal layer 252 gradually decreases with the increase of the thickness of the flexible metal layer 252, and the flexible metal layer 252 may be disposed in a circular truncated cone shape, for example. When the micro light-emitting diode is welded with the welding pad, the hollow between the welding pad and the electrode can be removed, the characteristic of the soft metal is utilized, the uneven welding pad area can be filled, the window allowing the substrate 200 to warp can be enlarged, and the reliability of the product is improved.

In another embodiment, as shown in fig. 32, the function of the conductive plugs and electrodes may be replaced by a special pad, such as a first conductive structure 260 instead of the first conductive plug 221 and the first electrode 226 and a second conductive structure 261 instead of the second conductive plug 222. The first conductive structure 260 and the second conductive structure 261 have elasticity, and may be defects caused by stress generated by thermal expansion of reflow soldering during soldering and use of an uneven substrate, while reducing a package void ratio. In the embodiment, the first conductive structure 260 is electrically connected to the first semiconductor layer, and the second conductive structure 261 is electrically connected to the second semiconductor layer. First conductive structure 260 includes a backing layer 262, an adhesive layer 263, a stretch layer 264, a barrier layer 265, and a weld layer 266, and second conductive structure 261 includes an adhesive layer 263, a stretch layer 264, a barrier layer 265, and a weld layer 266.

As shown in fig. 32, the pad layer 262 is disposed on the first semiconductor layer of the semiconductor epitaxial structure 20, and the height of the pad layer 262 is equal to the height of the transparent conductive layer 220. By arranging the leveling layer 262, the heights of the first conductive structure 260 and the second conductive structure 261 can be equal, and skew is avoided. A planarization layer 262 may be deposited on the first semiconductor layer by a chemical vapor deposition method at a temperature of 200 to 300 degrees. And material of the leveling layer 262The material being, for example, siO ₂ 、SiNx、Al ₂ O ₃ MgO or AlN, and the thickness of the leveling layer 262 is, for example, 900 to 1500nm, and may be specifically the same as the height of the transparent conductive layer 220.

As shown in fig. 32, the adhesive layer 263 of the first conductive structure 260 is disposed on the leveling layer 262, the adhesive layer 263 of the second conductive structure 261 is disposed on the transparent conductive layer 220, and the adhesive layers 263 of the first conductive structure 260 and the second conductive structure 261 are equal in height. An adhesive layer 263 can be deposited or sputtered on the pad layer 262 or the transparent conductive layer 220 under the condition of yellow light. The material of the adhesion layer 263 is, for example, cr, ni, ti or Indium Tin Oxide (ITO), the thickness of the adhesion layer 263 is, for example, 5-100 nm, and the adhesion layer 263 is lower than the height of the insulating layer 225.

As shown in fig. 32, the adhesive layer 263 of the first conductive structure 260 and the second conductive structure 261 is provided with a flexible layer 264, and the flexible layer 264 on the first conductive structure 260 and the flexible layer 264 on the second conductive structure 261 have the same height. The stretchable layer 264 can be deposited or sputtered on the adhesive layer 263 under the yellow condition. The expansion layer 264 is a composite layer formed of, for example, an alloy of titanium and aluminum (Ti/Al), an alloy of nickel and aluminum (Ni/Al), an alloy of titanium and silver (Ti/Ag), or an alloy of nickel and silver (Ni/Ag). The flexible layer 264 is higher than the insulating layer 225, and the thickness of the flexible layer 264 is, for example, (50-200) × N nm, where N ranges from 3 to 9, when N is too small, the flexible layer 264 has no flexible function, and when N is too large, the voltage of the flexible layer 264 is higher.

As shown in fig. 32, barrier layer 265 is disposed over peak layer 264 both on first conductive structure 260 and on second conductive structure 261, and the height of barrier layer 265 over peak layer 265 on first conductive structure 260 and over second conductive structure 261 are equal. A layer of peaks 265 can be deposited or sputtered onto the stretch layer 264 under the condition of yellow light. The material of the layer of peaks 265 is, for example, an alloy of platinum (Pt) and titanium (Ti), or an alloy of titanium (Ti) and nickel (Ni), and the thickness of the layer of peaks 265 is, for example, 100to 300nm.

As shown in fig. 32, a solder layer 266 is disposed over layer of peaks 265 of first conductive structure 260 and second conductive structure 261, and solder layer 266 on first conductive structure 260 and solder layer 266 on second conductive structure 261 are of equal height. A solder layer 266 may be deposited or sputtered onto layer 265 under the yellow glow conditions. The material of the solder layer 266 is, for example, tin (Sn) or gold-tin alloy (AuSn), and the thickness of the solder layer 266 is, for example, 80000 nm to 100000nm.

As shown in fig. 33, when the micro light emitting diode is used for backlight and illumination, the micro light emitting diode is often failed due to various adverse environmental effects, especially moisture infiltration, and the damage to the micro light emitting diode is particularly serious. The utility model provides a micro light-emitting diode sets up a special water proof coating 270 on luminous area and electrode, can let moisture content unlikely stop on the chip, makes the chip keep dry, and then avoids the harmfully of aqueous vapor can prevent the steam invasion.

As shown in fig. 33, the waterproof protective layer 270 includes a protective film layer 271, a hydrophobic film layer 272, and a water barrier layer 273. Here, the waterproof protective layer 270 is disposed on the transparent conductive layer 220 and a portion of the first and

second electrodes

226 and 227, the hydrophobic film layer 272 is disposed on the waterproof protective layer 270, and the water barrier layer 273 is disposed on the hydrophobic film layer 272. As shown in fig. 32, the waterproof layer 270 covers the transparent conductive layer 220, extends toward the first electrode 226 and the second electrode 227, and covers sidewalls and partial top walls of the first electrode 226 and the second electrode 227. As shown in fig. 34, the protective film layer 271 includes a first waterproof protective layer 274, a second waterproof protective layer 275, and a third waterproof protective layer 276, the second waterproof protective layer 275 being provided on the first waterproof protective layer 274, and the third waterproof protective layer 276 being provided on the second waterproof protective layer 275. And the first, second, and third water

protective layers

274, 275, and 276 may be deposited using a plasma enhanced chemical vapor deposition process, respectively. The first waterproof protective layer 274 is an oxide layer and has a thickness of, for example, 100to 300nm. The second water-repellent protection layer 275 is a graded oxide layer and nitride layer, and has a thickness of, for example, 15-25nm, and for example, 20nm, and the third water-repellent protection layer 276 is a nitride layer of a non-hydrophilic material, and has a thickness of, for example, 20-50 nm. Specifically, the material of the first waterproof protective layer 274 is, for example, silicon dioxide (SiO) ₂ ) Example of Material for second Water-repellent protective layer 275Such as silicon oxynitride (SiON), and the third water protective layer 276 is made of silicon nitride ((SiNx).

As shown in fig. 33, the hydrophobic film 272 is disposed on the waterproof protective layer 270, covers the waterproof protective layer 270, and may be formed by Electron Beam Evaporation (Electron Beam Evaporation) to form the hydrophobic film 272, wherein the thickness of the hydrophobic film 272 is, for example, 2 to 5um. The hydrophobic film 272 is a super-hydrophobic nitride layer, such as a metal nitride layer, specifically Boron Nitride (BN) or aluminum nitride (AlN), and other super-hydrophobic metal nitride layers.

As shown in fig. 33 and 35, a water barrier layer 273 is disposed on the hydrophobic film layer 272, and a plurality of protruding structures may be formed on the hydrophobic film layer 272 by annealing and re-crystallizing the hydrophobic film layer 272 to form the water barrier layer 273. The thickness of the water barrier layer 273 is greater than or equal to 1um, specifically, for example, 2um, and the thickness of the water barrier layer 273 is specifically, for example, the height of the protruding structure. Specifically, when the hydrophobic film 272 is formed, a thicker hydrophobic film 272 may be provided, specifically, the thickness of the hydrophobic film 272 before annealing and crystallization is equal to the sum of the thickness of the finally formed hydrophobic film 272 and the thickness of the water fence layer 273. After the hydrophobic film 272 is formed, the top of the hydrophobic film 272 is subjected to rapid high-temperature annealing or furnace tube annealing at a temperature of 200-300 ℃ for 30-60 minutes, and then the top surface of the hydrophobic film 272 is granulated to form a protruding structure, and the water fence layer 273 is formed by a plurality of protruding structures.

As shown in fig. 36 (a), the angle between the tangent to the edge of the droplet on the hydrophilic surface and the reference plane is generally less than 90 degrees, as shown in fig. 36 (b), the angle between the tangent to the edge of the droplet on the hydrophobic surface and the reference plane may range from 90 to 150 degrees, for example, and as shown in fig. 36 (c), the angle between the tangent to the edge of the droplet on the superhydrophobic surface and the reference plane is greater than 150 degrees. The utility model provides a protection film 271's hydrophobicity strengthens gradually, at the outmost super hydrophobic surface that forms of protection film 271, and at the water fence layer 273 that super hydrophobic metal nitriding layer surface formed the protruding structure, further prevents the steam invasion.

As shown in fig. 37, after the light emitting diode is transferred onto the display substrate, the substrate 200 needs to be peeled off to improve brightness. Because the electrodes are arranged on two sides of the semiconductor epitaxial structure and a cavity structure is arranged between the two electrodes, when the substrate 200 is peeled off, the semiconductor epitaxial structure is easy to crack, and the lamp is prevented from being electrically leaked and dead. The utility model provides a miniature light emitting diode can prevent that the semiconductor epitaxial structure fracture when substrate 200 from peeling off.

As shown in fig. 37, in the micro light emitting diode provided in the present embodiment, a supporting layer 280 is formed between the first electrode 226 and the second electrode 227, and the supporting layer 280 fills a gap between the first electrode 226 and the second electrode 227. The supporting layer 280 may be formed by evaporation, sputtering or chemical vapor deposition, and the material of the supporting layer 280 is, for example, siO ₂ 、SiNx、 Al ₂ O ₃ Or diamond like film (DLC). The height of the support layer 280 is not higher than the first and

second pads

245 and 246, and the thickness of the support layer 280 may be, for example, 300 to 4000nm. The micro light emitting diode uses a special supporting layer 280 to support the cracked part, so that the cracked part is not cracked, the top damage of crystal fetching is avoided, and electric leakage caused by the diffusion of bottom soldering flux or solder paste can be avoided.

As shown in fig. 38, after the micro light emitting diodes are formed, a plurality of micro light emitting diodes need to be transferred to the substrate. The semiconductor device described in this embodiment is, for example, a Micro light emitting diode transfer device, where a matrix cutting bar is disposed on the Micro light emitting diode transfer device, the Micro light emitting diode transfer device can divide a plurality of Micro light emitting diodes on a substrate into independent wafers, and each wafer includes at least one Mini LED or Micro LED. The matrix chuck can transfer the micro light emitting diode to the substrate. The micro light-emitting diode transfer device provided by the embodiment can be used for carrying out integrated cutting, and the working efficiency can be improved.

As shown in fig. 38, the micro led transfer device includes a base 301, a cartridge 302 disposed above the base 301, and a hollow slot disposed in the cartridge 302, wherein a neutral line of the hollow slot coincides with a neutral line of the cartridge 302. The lifting platform 303 is arranged in the empty groove, and the top surface of the lifting platform 303 is higher than the top surface of the barrel seat 302. The rotating table 304 is disposed on the lifting table 303, one end of the cantilever 305 is connected to the rotating table 304, and the fixed arm 306 is connected to one end of the cantilever 305 away from the rotating table 304. A transfer plate 308 is disposed below the fixed arm 306, matrix cutting strips 309 and matrix suction cups 310 are secured to the transfer plate 308, and the matrix suction cups 310 are positioned between adjacent matrix cutting strips 309.

As shown in fig. 38, a base 301 is disposed at the bottom of the micro led transfer device to support the whole micro led transfer device. And in some embodiments, in order to realize the movement of the micro led transfer device, the base 301 may be provided with a moving wheel set, and the moving wheel set may be configured with a stopper plate. The position of the whole micro light-emitting diode transfer device can be flexibly adjusted under the action of the moving wheel set and the stop plate. A cylinder base 302 can be arranged above the base 301, an empty slot can be arranged inside the cylinder base 302, the lifting platform 303 is arranged in the empty slot, and the lifting platform 303 can be a cylinder. The top of the lifting platform 303 is higher than the barrel base 302, and a lifting motor is arranged inside the lifting platform 303 to control the movement of the lifting platform 303 in the vertical direction.

As shown in fig. 38, the rotating table 304 is disposed on the lifting table 303, the rotating table 304 may be a cylinder, a central axis of the rotating table 304 coincides with a central axis of the lifting table 303, and a diameter of the rotating table 304 is smaller than a diameter of the lifting table 303. In some embodiments, a rotation motor is disposed inside the rotation stage 304, and the rotation motor controls the rotation stage 304 to perform a bidirectional circular motion. The side of the rotary table 304 is connected to a cantilever 305. The cantilever 305 is welded to the turntable 304. The cantilever 305 may have a hollow structure inside and may be provided with a reinforcing rib. The cantilever 305 is driven by a rotating motor inside the rotating platform 304 to make a bidirectional circular motion along the cantilever end portion motion trajectory line 314.

As shown in fig. 38 and 39, a transfer plate 308 is disposed below the securing arm 306. The upper surface of the transfer plate 308 is provided with bolt holes at positions corresponding to the fixing arms 306. The transfer plate 308 is connected to the fixed plate 306 by bolts 307. The transfer plate 308 is driven by a rotating motor inside the rotating platform 304 through the cantilever 305 to make bidirectional circular motion along the cantilever end movement track line 314, so as to realize the transfer of the wafer in different processing process chambers. The lower surface of the transfer plate 308 is provided with matrix cutting bars 309 and matrix suction cups 310. The transfer plate 308 and the matrix dicing strips 309 are attached under the transfer plate 308, and the matrix chucks 310 are located between the adjacent matrix dicing strips 309, and the matrix chucks 310 can batch-pick and hold the dies of the wafer 311 to be transferred to the target array substrate.

As shown in fig. 38 and 39, matrix cutting bars 309 and matrix suction cups 310 are fixed to the lower surface of the transfer plate 308, and the matrix cutting bars 309 may be arranged in a grid pattern, and the matrix suction cups 310 are arranged to intersect at regions between adjacent cutting bars of the matrix cutting bars 309. The height of the matrix suction cups 310 is less than the height of the matrix cutting bars. The ends of the matrix cutting bars 309 may be in the shape of an inverted trapezoid, a pyramid, or a combination or combination of other similar structures.

As shown in fig. 38 and 41, the wafer 311 is processed on the stage 12 in different processes, and a cutting groove is formed between adjacent wafers. The dicing grooves may be divided into a transverse dicing groove 315 and a longitudinal dicing groove 316, and the number of dicing grooves is different according to the number of wafers to be processed. In some embodiments, h 1-h 8 are transverse cut slots 315 and S1-S8 are longitudinal cut slots 316. The matrix dicing lines 309 correspond to the transverse dicing grooves 315 and the longitudinal dicing grooves 316, and perform integrated dicing of the wafer 311, thereby dividing different wafers 311 in the transverse direction and the longitudinal direction. As shown in fig. 39, a sawing line 317 may be defined between adjacent wafers 311, and a cutting plane at a vertical distance from the sawing line 317 is a stress concentration plane 318. The dicing force is applied to the stress concentration surface 318 by the saw wire 317, and after the dicing is completed, the wafer 311 is sucked and fixed by the matrix chuck 310. The adsorbed wafer 311 follows the transfer plate 308 and moves in a bidirectional circular motion along the cantilever end motion trajectory 314 under the driving of the rotation motor of the rotation stage 304. The utility model discloses an in other embodiments, can replace the matrix sucking disc for if mechanical snatching, sticky, electrostatic absorption, gas adsorption, electromagnetic absorption etc. have adopted the matrix adsorption body of close principle, realize wafer 311's integration cutting and transfer.

In this embodiment, the saw blade is cut across the surface of the wafer 311, as shown in fig. 41, and for thin wafers, the saw blade is lowered to cut a shallow groove into the surface of the wafer 1/3 of the wafer thickness. The chip separation method is still completed by applying pressure by the cylindrical roller in the scribing method and the diamond scribing method.

Referring to fig. 42 to 43, in some embodiments, after transferring the micro light emitting diodes onto the substrate 244, the substrate 244 is provided with a driving circuit 296, and the light emitting diodes are connected to the driving circuit 296 through bonding pads, so as to form a micro light emitting diode display panel. In the present embodiment, a micro led display panel is further provided, which includes a substrate 244 and a micro led disposed on the substrate 244 and having a plurality of nano holes, and quantum dots are disposed in the nano holes.

As shown in fig. 42 to 43, the micro light emitting diode in the present embodiment includes a first semiconductor layer 291 and a second semiconductor layer 292 disposed on the first semiconductor layer 291. The first semiconductor layer 291 may be connected to an electrode, and the first semiconductor layer 291 is, for example, an N-type gallium nitride layer. The second semiconductor layer 292 is disposed on the first semiconductor layer 291, and the second semiconductor layer 292 is also a gallium nitride layer, and is, for example, an N-type gallium nitride layer. The second semiconductor layer 292 is provided with a plurality of nano holes 293 in an array, specifically, the N-type gallium nitride layer may be immersed in an acidic solution and biased to form nano-pores in the N-type gallium nitride layer, so as to drive the electrochemical etching of the N-type gallium nitride layer to form the nano holes 293, and the density and size of the nano holes 293 may be changed by changing the applied bias or the silicon doping concentration in GaN. The diameter of the nanopores 293 is, for example, 50to 200nm, and the distance between adjacent nanopores 293 is, for example, 30 to 300nm.

As shown in fig. 42 to fig. 43, in the present embodiment, the nano-hole 293 penetrates through the second semiconductor layer 292, and when no quantum dot is disposed in the nano-hole 293, the micro light emitting diode emits ultraviolet light or blue light. The micro light emitting diode may emit red light when the red quantum dots 295 are disposed in the nano-hole 293, and may emit green light when the green quantum dots 294 are disposed in the nano-hole 293. In some embodiments, the red quantum dots 295, the green quantum dots 294, and the vacant nano-holes 293 are sequentially arranged on the second semiconductor layer 292. In other embodiments, the second semiconductor layer 292 includes a plurality of first type light emitting arrays, second type light emitting arrays, and third type light emitting arrays sequentially disposed thereon. Red quantum dots 295 are filled in the nano holes 293 in the first type light emitting array, green quantum dots 294 are filled in the nano holes 293 in the second type light emitting array, and the nano holes 293 in the third type light emitting array are vacant nano holes 293. The first type light emitting array, the second type light emitting array and the third type light emitting array are equal in shape and size, so that the formed micro light emitting diode emits light more uniformly, the length of the arrays is 100-2000 nm, and the width of the arrays is 100-2000 nm. The quantum dots are disposed in the quantum nano-holes 293, which can improve the absorption rate of the quantum dots and prolong the service life of the quantum dots.

As shown in fig. 42 to 43, when the micro led display panel is formed, the driving circuit 296 is provided on the substrate 244, and the driving circuit 296 may be provided on the surface of the substrate 244 or may be provided in the substrate 244. After bonding the micro light emitting diodes to the substrate 244, the driving circuit 296 drives the micro light emitting diodes to display light. The nano holes 293 are formed in the micro light-emitting diodes, and quantum dots with different colors are filled in the nano holes 293, so that the sorting of the light-emitting diodes with different colors can be avoided, and the production cost is reduced.

Referring to fig. 44, the present disclosure further provides an electronic device, which includes a micro led display panel 300 and an electronic device body 301, wherein the micro led display panel 300 is connected to the electronic device body 301, and the micro led display panel 300 includes a circuit substrate and a plurality of micro led chips. The electronic device body 301 includes a controller 302, a memory 303, and a power supply 304. The power supply 304 can convert the commercial power (220V ac) into dc power required by the controller 302 and the memory 303, and provide power for the micro led panel 300. The memory 303 is connected to a power supply 304 for storing data related to the operation of the electronic device, the controller 302 is connected to the power supply 304 and also connected to the memory 303, the power supply 304 is used for supplying power to the controller 302, and the controller executes a program in the memory 303 to control the electronic device. The electronic device may be, for example, a display panel, a mobile phone, a watch, a notebook computer, a projection device, a charging post, a Virtual Reality (VR) device, an Augmented Reality (AR) device, a portable electronic device, a game console, or other electronic devices.

As shown in fig. 45, when the semiconductor epitaxial structure of the present disclosure is applied to manufacture a semiconductor device, the semiconductor device includes a substrate 200, a buffer layer 201, a first semiconductor layer 203, a second semiconductor layer 205, a source electrode 301, a drain electrode 302, and a gate electrode 303. The buffer layer 1401 is disposed on the substrate 200, the first semiconductor layer 203 is disposed on the buffer layer 201, the second semiconductor layer 205 is disposed on the first semiconductor layer 203, the source 301 is formed on the second semiconductor layer 205, the drain 302 is formed on the second semiconductor layer 205, and the gate 303 is formed on the second semiconductor layer 203 and between the source 301 and the drain 302. A source doped region 303 and a drain doped region 304 are disposed on the second semiconductor layer 205, and the source doped region 303 and the drain doped region 304 are, for example, N-type heavily doped regions, and the source 301 is disposed on the source doped region 303 and the drain 302 is disposed on the drain doped region 304.

As shown in fig. 46, when the semiconductor device of the present disclosure is applied to a radio frequency module, the radio frequency module includes the semiconductor device. The radio frequency module mainly includes a Radio Frequency (RF) switching device 311, a Radio Frequency (RF) active device 314, a Radio Frequency (RF) passive device 312, and a control device 313. Wherein the Radio Frequency (RF) active device 314 may be a semiconductor device as described herein, and the Radio Frequency (RF) passive device 312 may be a passive device such as a capacitor, a resistor, and an inductor. Here, a Radio Frequency (RF) switching device 311, a Radio Frequency (RF) active device 314, a Radio Frequency (RF) passive device 312, and a control device 313 are formed on the semiconductor substrate 200.

The above description is only a preferred embodiment of the present application and the description of the applied technical principle, and it should be understood by those skilled in the art that the scope of the present invention is not limited to the technical solution of the specific combination of the above technical features, and also covers other technical solutions formed by any combination of the above technical features or their equivalent features, for example, the technical solutions formed by mutually replacing the above technical features (but not limited to) having similar functions disclosed in the present application, without departing from the inventive concept.

Besides the technical features described in the specification, other technical features are known to those skilled in the art, and further description of the other technical features is omitted here in order to highlight the innovative features of the present invention.

Claims

1. A light emitting diode, comprising:

a substrate;

a gallium nitride layer disposed on the substrate;

the semiconductor epitaxial structure is arranged on the substrate and comprises a first semiconductor layer, an active layer and a second semiconductor layer which are sequentially arranged on the gallium nitride layer;

a second electrode disposed on the transparent conductive layer; and

waterproof layer sets up transparent conducting layer and part first electrode with on the second electrode, just waterproof layer includes protection rete, hydrophobic rete and water fence layer, the protection rete covers transparent conducting layer, and towards first electrode with the second electrode extends, just the protection rete covers the lateral wall and the partial roof of first electrode and second electrode, the hydrophobic rete sets up on the protection rete, the water fence layer sets up on the hydrophobic rete, just the water fence layer includes a plurality of protruding structures.

2. The led of claim 1, wherein the protective film layer comprises a first waterproof protective layer, and the first waterproof protective layer is an oxide layer.

3. The light-emitting diode according to claim 2, wherein the thickness of the first waterproof protective layer is 100to 300nm.

4. The led of claim 2, wherein the protective layer comprises a second waterproof protective layer, the second waterproof protective layer covers the first waterproof protective layer, and the second waterproof protective layer is a graded layer of an oxide layer and a nitride layer.

5. The LED of claim 4, wherein the second waterproof protective layer has a thickness of 15-25nm.

6. The LED of claim 5, wherein the protective film layer comprises a third water-proofing protective layer, the third water-proofing protective layer covers the second water-proofing protective layer, and the third water-proofing protective layer is a nitride layer.

7. The light-emitting diode according to claim 6, wherein the third water-proofing protective layer has a thickness of 20 to 50nm.

8. The led of claim 1, wherein the led is a micro led.

9. A light-emitting diode display comprising the light-emitting diode according to claim 1.