CN217507311U

CN217507311U - Semiconductor packaging device

Info

Publication number: CN217507311U
Application number: CN202221173180.XU
Authority: CN
Inventors: 颜尤龙; 博恩·卡尔·艾皮特
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2022-05-16
Filing date: 2022-05-16
Publication date: 2022-09-27
Anticipated expiration: 2032-05-16

Abstract

The present application relates to semiconductor packaging devices. The semiconductor package device includes: the core layer comprises epoxy plastic packaging material and is provided with a first surface and a second surface opposite to the first surface; a first circuit layer disposed on the first surface of the core layer; and a second circuit layer disposed on the second surface of the core layer. The semiconductor packaging device is beneficial to reducing the thickness of the semiconductor packaging device and improving the manufacturing yield of the semiconductor packaging device.

Description

Semiconductor packaging device

Technical Field

The application relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging device.

Background

In the current core substrate (core substrate) process, glass fiber is used as the core layer and needs a larger thickness to achieve a stronger rigidity, so as to facilitate the subsequent lamination process. This approach is disadvantageous for reducing the overall thickness of the semiconductor package device.

In addition, in the above process, the wiring is formed in both directions on both surfaces of the substrate, and when the number of wiring layers is large, the entire semiconductor package device is likely to be defective due to the defective wiring on one side, and thus the cost of the entire process is high.

Therefore, a new technical solution is needed to solve at least one of the above technical problems.

SUMMERY OF THE UTILITY MODEL

The present application provides a semiconductor package device.

In a first aspect, the present application provides a semiconductor package device comprising:

the core layer comprises epoxy plastic molding compound and is provided with a first surface and a second surface opposite to the first surface;

a first circuit layer disposed on a first surface of the core layer;

a second circuit layer disposed on the second surface of the core layer.

In some optional embodiments, the first circuit layer comprises a first dielectric layer comprising a first filler, the second circuit layer comprises a second dielectric layer comprising a second filler, and the epoxy molding compound comprises a third filler;

the rigidity of the third filler is greater than the rigidity of the first filler and the second filler.

In some optional embodiments, the third filler is filler particles, the first filler is filler particles or filler fibers, and the second filler is filler particles or filler fibers.

In some alternative embodiments, the first circuit layer includes an electrical connector that extends through the core layer and is electrically connected with the second circuit layer.

In some optional embodiments, the electrical connector is electrically connected to the second circuit layer by solder.

In some alternative embodiments, the interface of the electrical connector and the solder is located within the core layer.

In some alternative embodiments, the electrical connection is a conductive post, a metal paste, or a solder ball containing a metal core.

In some alternative embodiments, the thickness of the core layer is greater than or equal to 10 microns and less than or equal to 40 microns.

In some alternative embodiments, the first dielectric layer and/or the second dielectric layer comprises a prepreg, an ajinomoto film, or an epoxy molding compound.

In some optional embodiments, the first circuit layer and/or the second circuit layer is a buried circuit substrate.

In some alternative embodiments, a chip or passive component is disposed within the core layer.

In the semiconductor packaging device provided by the application, the upper circuit layer and the lower circuit layer can be manufactured firstly and electrically connected, and the core layer is formed by molding in the butted gap, so that the core layer containing the epoxy molding compound replaces the core layer substrate, the thickness of the semiconductor packaging device is reduced, and the manufacturing yield of the semiconductor packaging device is improved.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

FIG. 1 is a schematic diagram of a semiconductor package device in the prior art;

fig. 2-6 are first through fifth schematic views of semiconductor packaging devices according to embodiments of the present application;

fig. 7-15 are schematic diagrams of a manufacturing process of a semiconductor package device according to an embodiment of the present application.

Description of the symbols:

11. a core layer substrate; 12. adding layers; 100. a first circuit layer; 110. a first dielectric layer; 200. a second circuit layer; 210. a second dielectric layer; 300. a core layer; 310. epoxy plastic packaging material; 410. an electrical connection; 430. a metal core; 420. welding flux; 500. a first chip; 510. a passive element; 520. a second chip; 600. molding the material; 910. and a carrier plate.

Detailed Description

The following description of the embodiments of the present application will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects that the present application solves and provides by the contents of the present specification. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and are not limiting of the invention. In addition, for convenience of description, only portions related to the related utility model are shown in the drawings.

It should be noted that the structures, proportions, sizes, and other elements shown in the drawings are only used for understanding and reading the contents of the specification, and are not used for limiting the conditions under which the present application can be implemented, so they do not have the technical significance, and any structural modifications, changes in proportion, or adjustments of sizes, which do not affect the efficacy and achievement of the purposes of the present application, shall still fall within the scope of the technical content disclosed in the present application. In addition, the terms "above", "first", "second" and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present application, and changes or modifications of the relative relationship may be made without substantial technical changes.

It should be further noted that, in the embodiments of the present application, the corresponding longitudinal section may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.

It should be readily understood that the meaning of "in.. on," "over,", and "above" in this application should be interpreted in the broadest sense such that "in.. on" not only means "directly on something," but also means "on something" including an intermediate member or layer between the two.

Furthermore, spatially relative terms, such as "below," "lower," "over," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 or at other orientations) and the spatially relative descriptors used in this application interpreted accordingly as such.

In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Fig. 1 is a schematic diagram of a semiconductor package device in the prior art. As shown in fig. 1, the semiconductor package device includes a core layer substrate 11 and two build-up layers 12. The two build-up layers 12 are respectively provided on the upper surface and the lower surface of the core layer substrate 11, and are formed by bidirectionally building a wiring on the upper surface and the lower surface of the core layer substrate 11. When the number of the wiring layers is large, the whole semiconductor package device is easily defective due to the defective wiring on one side, so that the cost of the whole process is high, and the number of the delivered products is also affected to cause the shortage of the products on the market.

Fig. 2-6 are first to fifth schematic views of a semiconductor package device according to an embodiment of the present application.

Fig. 2 shows a longitudinal section of the semiconductor package device. As shown in fig. 2, the semiconductor package device in the embodiment of the present application includes a core layer 300, a first circuit layer 100, and a second circuit layer 200. The core layer 300 includes an Epoxy Molding Compound (EMC) 310. The core layer 300 has a first surface (i.e., an upper surface in fig. 2) and a second surface (i.e., a lower surface in fig. 2) opposite the first surface. The first wiring layer 100 is disposed on a first surface of the core layer 300. The second circuit layer 200 is disposed on the second surface of the core layer 300. In other words, the core layer 300 is located between the first circuit layer 100 and the second circuit layer 200. The first circuit layer 100 and the second circuit layer 200 are both Coreless substrates (Coreless substrates).

The first circuit layer 100 includes one or more first dielectric layers 110. The first dielectric layer 110 includes a first filler (not shown). The second wiring layer 200 includes one or more second dielectric layers 210. The second dielectric layer 210 includes a second filler material (not shown). The epoxy molding compound 310 includes a third filling material (not shown). Wherein the rigidity of the third filling material is greater than the rigidity of the first filling material and the second filling material. Accordingly, the overall stiffness of the core layer 300 is greater than the overall stiffness of the first and second circuit layers 100 and 200, and the core layer 300 can support the first and second circuit layers 100 and 200.

In some embodiments, the third filler material may be filler particles (filler), the first filler material may be filler particles or filler fibers (fiber, e.g., glass fibers), and the second filler material may be filler particles or filler fibers.

In some embodiments, the material of the first dielectric layer 110 and/or the second dielectric layer 210 may be a prepreg (preprg), Ajinomoto Build-up Film (ABF), or an epoxy molding compound. Wherein, the prepreg contains filling fibers and has better rigidity. The ajinomoto film contains filler particles, is soft in material, and can be used for making Fine Pitch. The materials of the first dielectric layer 110 and the second dielectric layer 210 may be the same or different.

In some embodiments, the first circuit layer 100 and/or the second circuit layer 200 may be an Embedded Trace Substrate (ETS), in which the Trace is Embedded in a dielectric material, and the surface has better flatness.

The first circuit layer 100 includes an electrical connector 410. The electrical connector 410 extends through the core layer 300 and is electrically connected with the second circuit layer 200. The electrical connection element 410 is a conductive pillar (pillar), which can be formed by electroplating or wire bonding. After the conductive pillars are molded, conductive vias (via) are formed in the core layer 300. The electrical connector 410 is electrically connected to the second circuit layer 200 by solder 420. The interface of the electrical connector 410 and the solder 420 is located within the core layer 300. The bonding process of the first circuit layer 100 and the second circuit layer 200 will be described in detail below.

In the semiconductor package device according to the embodiment of the present application, the first circuit layer 100 and the second circuit layer 200 may be fabricated and electrically connected, and then the core layer 300 is formed by molding in the abutted gap, so that the core layer 300 including the epoxy molding compound 310 replaces the substrate with the core layer 300, which is beneficial to reducing the thickness of the semiconductor package device.

The thickness of the gap between the first circuit layer 100 and the second circuit layer 200 may be greater than or equal to 10 micrometers and less than or equal to 40 micrometers, so that the molding material 600 can smoothly enter the gap, and the thickness of the whole semiconductor package device can be thinned. Accordingly, the thickness of the core layer 300 may be greater than or equal to 10 micrometers and less than or equal to 40 micrometers.

Since the first circuit layer 100 and the second circuit layer 200 are separately manufactured, yield loss of one does not affect the other, and thus the manufacturing yield of the semiconductor package device can be improved.

In fig. 2, the number of the first dielectric layers 110 and the second dielectric layers 210 is the same. In other embodiments, the number of first dielectric layers 110 and second dielectric layers 210 may also be different.

The first circuit layer 100 and the second circuit layer 200 may be the same or different in material, number of layers, thickness, and the like. Preferably, the Coefficient of Thermal Expansion (CTE) of the first dielectric layer 110 and the CTE of the second dielectric layer 210 are the same or substantially the same by designing the material, the number of layers and the thickness, so as to reduce warpage of the semiconductor package device due to thermal processing (warpage).

The semiconductor package device in fig. 2 further includes a first chip 500. The first chip 500 is disposed on the upper surface of the first circuit layer 100. The molding material 600 covers the first chip 500 to protect it.

Fig. 3 shows a variation of the semiconductor package device of fig. 2. In fig. 2, electrical connection 410 is a conductive post. In fig. 3, electrical connection 410 is a metal paste (paste). Metal pastes may be respectively disposed on the first and second circuit layers 100 and 200 by printing or the like, and connection between the metal pastes is achieved by heating. The cost of the metal paste is lower than that of the conductive pillars.

Fig. 4 shows a variation of the semiconductor package device of fig. 2. In fig. 2, electrical connection 410 is a conductive post. In fig. 3, electrical connections 410 are solder balls containing metal cores 430. A simple solder ball cannot maintain its shape after melting. Since the melting point of the metal core 430 is high, the solder ball containing the metal core 430 can maintain its shape after being melted, and thus the electrical connection member 410 having a certain height can be formed.

Fig. 5 shows a variation of the semiconductor package device of fig. 4. In addition to the structure shown in fig. 4, a passive element 510 is provided in the core layer 300 in fig. 5.

Fig. 6 shows a variation of the semiconductor package device of fig. 3. In addition to the structure shown in fig. 3, a second chip 520 is disposed in the core layer 300 in fig. 6.

By disposing the passive component 510 or the second chip 520 in the core layer 300, the pin occupation and the space occupation on the upper surface of the first circuit layer 100 can be reduced, which is beneficial for reducing the lateral size of the semiconductor package device.

Fig. 7-10 are schematic diagrams of a manufacturing process of a semiconductor package device according to an embodiment of the present application. The manufacturing process comprises the following steps:

first, as shown in fig. 7, a first circuit layer 100 and a second circuit layer 200 are formed on a carrier plate 910, respectively, and an electrical connector 410 is formed on a surface of the first circuit layer 100, and a solder 420 is disposed on an upper end of the electrical connector 410. The electrical connection element 410 is a conductive pillar, which can be formed by electroplating or wire bonding. When the conductive pillar is formed by using a routing process, a gold (Au) material needs to be disposed on the surface of the conductive pillar of the first circuit layer 100, then a longitudinal metal wire is formed by routing, and finally the metal wire is cut short to form the conductive pillar.

In the second step, as shown in fig. 8, the carrier 910 under the first circuit layer 100 and the second circuit layer 200 is removed for subsequent processes.

Third, as shown in fig. 9, the first circuit layer 100 is turned over and the electrical connector 410 and the solder 420 are connected through a Reflow (Reflow) process to achieve the connection of the first circuit layer 100 and the second circuit layer 200.

Fourth, as shown in fig. 10, molding is performed in the gap between the first circuit layer 100 and the second circuit layer 200 (see fig. 9) to form a core layer 300, thereby obtaining a semiconductor package device.

Reference may also be made to the above-described manufacturing process when electrical connections 410 are metal paste or solder balls containing metal cores. When the electrical connector 410 is made of metal paste, the metal paste is disposed on the first circuit layer 100, and the metal paste is disposed on the second circuit layer 200, and then the metal paste of the first circuit layer 100 and the metal paste of the second circuit layer 200 are connected by a thermal process.

Fig. 11 to 15 show variations of the manufacturing process of the above semiconductor package device, respectively.

In fig. 11, electrical connection 410 is a metal paste.

In fig. 12, electrical connections 410 are solder balls containing metal cores 430 (see fig. 5).

In fig. 13, the first dielectric layer 110 and the second dielectric layer 210 are made of different materials, wherein the material of the first dielectric layer 110 is an ajinomoto film, and the material of the second dielectric layer 210 is a prepreg.

In fig. 14, the number of the line layers of the first line layer 100 and the second line layer 200 is different, wherein the number of the line layers of the first line layer 100 is three, and the number of the line layers of the second line layer 200 is two.

Different materials are selected for the first circuit layer 100 and the second circuit layer 200, or the number of the selected circuit layers is different, and different number of layers can be set according to the functional requirements or other factor requirements.

In fig. 15, different substrate manufacturing techniques are used for the first circuit layer 100 and the second circuit layer 200, where the first circuit layer 100 is a buried circuit substrate and the second circuit layer 200 is a copper connection in molding (C2 iM) substrate. Copper connections provide better signal transmission because copper has a higher conductivity than most metals.

For the details of the embodiments in fig. 11-15, reference may be made to the description of the embodiments in fig. 7-10, which is not repeated here.

While the present application has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present application. It will be apparent to those skilled in the art that various changes may be made and equivalents may be substituted in the embodiments without departing from the true spirit and scope of the application as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present application and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the application that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present application. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present application. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present application.

Claims

1. A semiconductor package device, comprising:

a first circuit layer disposed on a first surface of the core layer;

a second circuit layer disposed on the second surface of the core layer.

2. The semiconductor packaging device of claim 1, wherein the first circuitry layer comprises a first dielectric layer comprising a first filler material, the second circuitry layer comprises a second dielectric layer comprising a second filler material, and the epoxy molding compound comprises a third filler material;

3. The semiconductor package device according to claim 2, wherein the third filler is filler particles, the first filler is filler particles or filler fibers, and the second filler is filler particles or filler fibers.

4. The semiconductor package device of claim 1, wherein the first circuit layer includes an electrical connector that extends through the core layer and electrically connects with the second circuit layer.

5. The semiconductor package device of claim 4, wherein the electrical connection is electrically connected to the second circuit layer by solder.

6. The semiconductor package device of claim 5, wherein the interface of the electrical connector and the solder is located within the core layer.

7. The semiconductor package device of claim 4, wherein the electrical connection is a conductive pillar, a metal paste, or a solder ball containing a metal core.

8. The semiconductor package device of claim 1, wherein the thickness of the core layer is greater than or equal to 10 microns and less than or equal to 40 microns.

9. The semiconductor packaging apparatus of claim 2, wherein the first dielectric layer and/or the second dielectric layer comprises a prepreg, a ajinomoto film, or an epoxy molding compound.

10. The semiconductor package device of claim 1, wherein the first circuit layer and/or the second circuit layer is a buried circuit substrate.