CN217335555U - Secondary oblique wave generating circuit - Google Patents
Secondary oblique wave generating circuit Download PDFInfo
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- CN217335555U CN217335555U CN202220782100.4U CN202220782100U CN217335555U CN 217335555 U CN217335555 U CN 217335555U CN 202220782100 U CN202220782100 U CN 202220782100U CN 217335555 U CN217335555 U CN 217335555U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The utility model relates to a secondary oblique wave produces circuit. The circuit comprises two operational amplifiers OP1 and OP2, M1 generated by second-order current, voltage-dividing resistors R1 and R2, switches S1 and S2, PWM output signals, an inverter INV, a current mirror formed by M2 and M3, a resistor R3, M4 generated by fourth-order current and a current mirror formed by M5 and M6.
Description
Technical Field
The utility model belongs to the technical field of switch DC-DC converter, be the oblique wave compensating circuit scheme of current mode PWM switch converter, especially relate to a secondary oblique wave produces the circuit.
Background
In general, with a Pulse Width Modulation (PWM) DC-DC converter, subharmonic or subharmonic oscillation occurs when the duty ratio of the modulation signal is greater than 50%, and in order to eliminate the oscillation, ramp compensation must be introduced to stabilize the system. According to the principle of ramp compensation, the invention discloses a ramp generating circuit with high-order characteristics, and high-order current generated by the circuit has the characteristics of small current and large slope, so that the load capacity of a DC-DC converter can be improved.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model is that DC-DC converter's load capacity is lower among the prior art, in order to improve its weak point, the utility model provides a can improve DC-DC converter's load capacity's secondary oblique wave generating circuit.
In order to achieve the purpose, the utility model is realized by the following technical proposal:
a second-order oblique wave generating circuit comprises two operational amplifiers OP1 and OP2, a second-order current generating M1, voltage dividing resistors R1 and R2, switches S1 and S2, a PWM output signal, an inverter INV, a current mirror composed of M2 and M3, a resistor R3, a fourth-order current generating M3, and a current mirror composed of M3 and M3, wherein an input voltage Vr of the oblique wave generating circuit is input to a positive input terminal of the operational amplifier OP 3, an output Vo of the operational amplifier OP 3 is connected to an upper terminal of the resistor R3, a lower terminal of the R3 is connected to the V3, a lower terminal of the resistor R3 is grounded, the V3 is connected to a negative input terminal of the operational amplifier 3, an output Vo of the operational amplifier is connected to one terminal of the switch S3, the other terminal of the switch S3 is connected to a gate of the M3, and a source terminal of the PWM control signal MO of the switch S3 is connected to the ground, the PWM output signal INV 3, the switch S3 is connected to the ground. The drain of M1, the drain and the gate of M2 and the gate of M3 are connected to VD1, the sources of M2 and M3 are connected to VCC, the drain of M3 is connected to the upper end of resistor R3 at V2, V2 is connected to the positive input end of operational amplifier OP2, the output Vg2 of operational amplifier OP2 is connected to the negative input end of OP2 and simultaneously to the gate of M4, the source of M4 is grounded, the drain, the gate of M5 and the gate of M6 are connected to VD2, the drain of M6 is the output Io, and the sources of M5 and M6 are connected to VCC.
Preferably, the M1 and M4 are NMOS, and M2, M3, M5 and M6 are PMOS.
Compared with the prior art, the beneficial effects of the utility model are that: the device eliminates harmonic oscillation when the pulse width of the switching power supply converter is larger than 50%, and simultaneously, due to the high-order characteristic of the device, the compensation current has the characteristic of low current and high slope, so that the problem of load capacity reduction caused by the compensation technology can be effectively reduced, and the device is suitable for industrial production and has strong practicability.
Drawings
Fig. 1 is a schematic diagram of the circuit structure of the present invention.
Fig. 2 is a schematic diagram of the relationship between Vr, PWM and Io in the present invention.
Detailed Description
The technical solution of the present application will be further described and explained with reference to the accompanying drawings and embodiments.
As shown in fig. 1, in the second-order ramp generating circuit, a ramp input voltage Vr is input to a positive input terminal of an operational amplifier OP1, an output Vo of the operational amplifier OP1 is connected to an upper end of a resistor R1, a lower end of R1 is connected to an upper end V1 of R2, a lower end of a resistor R2 is grounded, a V1 is connected to a negative input terminal of the operational amplifier OP1, an output Vo of the operational amplifier is connected to one end of a switch S1, the other end of the switch S1 is connected to a gate of a MOSM1 and an upper end of a switch S2, a lower end of S2 is grounded, a control terminal of the switch S1 is connected to a PWM signal, a control terminal of the switch S2 is connected to an output signal PWMO of the INV, and the operational amplifier and the resistors R1 and R2 form a same-direction amplification, so that an output Vg1 is Vr (R1/R1+ R2).
The source of MOS M1 is grounded, and the drain, the drain and the gate of M2 and the gate of M3 are connected to VD 1. The sources of M2 and M3 are connected with a power supply VCC, the drain of M3 is connected with the upper end of a resistor R3 at a point V2, and V2 is connected with the positive input end of an operational amplifier OP 2. The drain current of M1 Is the same as the drain current Is of M3, so that Is k 1V g1 2 And the voltage V2 ═ R3 ═ K1 ═ R3 ═ V g1 2 。
The output Vg2 of the operational amplifier OP2 is connected to its negative input,meanwhile, the source of the M4 is grounded, the drain of the M5, the gate of the M6 and the drain of the M4 are connected to VD2, the drain of the M6 is used as the output Io, and the sources of the M5 and the M6 are connected to a power VCC. Since the drain current of M4 Is the same as the drain current Is of M6, Io Is K2 × V2 2 And the voltage V2 ═ R3 ═ K1 ═ R3 ═ V g1 2 So Io-K2-K1 2 *R3 2 *V g1 4 。
Therefore, a high-order ramp current Io can be obtained by the scheme of fig. 1, wherein K2 is a coefficient related to the size and the process of M4, and K1 is a coefficient related to the size and the process of R1, R2 and M1.
The relationship between Vr, PWM, PWMO and Io in FIG. 1 is shown in FIG. 2.
The present invention is not limited to the above embodiments, and based on the technical solutions disclosed in the present invention, those skilled in the art can make some replacements and transformations for some technical features without creative labor according to the disclosed technical contents, and these replacements and transformations are all within the protection scope of the present invention.
Claims (2)
1. A secondary ramp generating circuit, characterized by: two operational amplifiers OP1 and OP2 are included, a second-order current generating M1, voltage dividing resistors R1 and R1, switches S1 and S1, a PWM output signal, an inverter INV, a current mirror formed by M1 and M1, a resistor R1, a fourth-order current generating M1, and a current mirror formed by M1 and M1, an input voltage Vr of the ramp wave generating circuit is input to a positive input terminal of the operational amplifier OP1, an output Vo of the operational amplifier OP1 is connected to an upper terminal of the resistor R1, a lower terminal of the R1 is connected to the V1, a lower terminal of the resistor R1 is grounded, the V1 is connected to a negative input terminal of the operational amplifier OP1, an output Vo of the operational amplifier is connected to one terminal of the switch S1, the other terminal of the switch S1 is connected to a gate of the M1, the switch S1 is connected to an upper terminal of the switch S1, a lower terminal of the S1 is grounded, a drain of the switch S1 controls the drain of the PWM signal, a source of the PWM signal MOS 1 is connected to the drain of the switch S1, a drain of the M1 is connected to the drain of the M1, and a drain of the M1 is connected to the drain of the switch M1, The grid and the grid of M3 are connected with VD1, the sources of M2 and M3 are connected with a power supply VCC, the drain of M3 is connected with the upper end of a resistor R3 at a point V2, V2 is connected with the positive input end of an operational amplifier OP2, the output Vg2 of the operational amplifier OP2 is connected with the negative input end of OP2 and is simultaneously connected with the grid of M4, the source of M4 is grounded, the drain of M4, the drain of M5, the grid of M6 and the grid of M2 are connected with VD2, the drain of M6 is the output Io, and the sources of M5 and M6 are connected with the power supply VCC.
2. The secondary ramp generating circuit of claim 1, wherein: the M1 and M4 are NMOS, and M2, M3, M5 and M6 are PMOS.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220782100.4U CN217335555U (en) | 2022-04-06 | 2022-04-06 | Secondary oblique wave generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220782100.4U CN217335555U (en) | 2022-04-06 | 2022-04-06 | Secondary oblique wave generating circuit |
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| Publication Number | Publication Date |
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| CN217335555U true CN217335555U (en) | 2022-08-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202220782100.4U Active CN217335555U (en) | 2022-04-06 | 2022-04-06 | Secondary oblique wave generating circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115378234A (en) * | 2022-09-16 | 2022-11-22 | 北京炎黄国芯科技有限公司 | High-order oblique wave generating circuit for harmonic compensation and electronic equipment |
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2022
- 2022-04-06 CN CN202220782100.4U patent/CN217335555U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115378234A (en) * | 2022-09-16 | 2022-11-22 | 北京炎黄国芯科技有限公司 | High-order oblique wave generating circuit for harmonic compensation and electronic equipment |
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