CN217333288U - FPGA power supply circuit of miniwatt usage occasion - Google Patents
FPGA power supply circuit of miniwatt usage occasion Download PDFInfo
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- CN217333288U CN217333288U CN202221121194.7U CN202221121194U CN217333288U CN 217333288 U CN217333288 U CN 217333288U CN 202221121194 U CN202221121194 U CN 202221121194U CN 217333288 U CN217333288 U CN 217333288U
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Abstract
An FPGA power supply circuit for a low-power use occasion is provided with a main control chip U12 and a load chip U24; the main control chip U12 provides power supply support for the load chip U24; the input decoupling circuit is added to a power supply input pin of the main control chip U12; the resistor R951 is connected to a feedback pin of the main control chip U12; a capacitor C852 is added to an output tracking and soft start pin of the main control chip U12; a capacitor C857 is added to a current threshold control and phase compensation pin of the main control chip U12; the resistor R949 is used as a ground isolating resistor of the main control chip U12; an output decoupling circuit is added to a power supply output pin of the main control chip U12. The utility model discloses be fit for FPGA miniwatt use occasion, reduce the complexity of hardware design, reduce the area that occupies PCB, reduce cost improves the reliability and the holistic stability of system of design.
Description
Technical Field
The utility model belongs to the technical field of supply circuit, concretely relates to FPGA supply circuit of miniwatt usage occasion.
Background
The FPGA is a product which is further developed on the basis of programmable devices such as PAL (programmable array logic), GAL (general array logic) and the like, is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), and forms a typical integrated circuit in the semi-custom circuit, wherein the typical integrated circuit comprises a digital management module, an embedded unit, an output unit, an input unit and the like, so that the defects of a custom circuit are overcome, and the defect that the number of gate circuits of the original programmable device is limited is overcome.
In the existing scheme, the power supply of the domestic FPGA is based on multiple discrete power supplies, and the power supplies of VCC _ INT, VCC _ BRAM, VCC _ AUX and VCC _3V3 are respectively provided, so that the circuit design is relatively complex, the complexity of the hardware design is high, the occupied area of a PCB is large, the layout pressure is too large for a circuit board with a small PCB and a tense layout, and the reliability and stability of the design are poor, even the power supply cannot be realized.
SUMMERY OF THE UTILITY MODEL
Therefore, the utility model provides a FPGA supply circuit of miniwatt usage occasion solves the problem that current miniwatt occasion power supply scheme design complexity is high, reliability and poor stability.
In order to achieve the above object, the present invention provides the following technical solutions: an FPGA power supply circuit for a low-power use occasion comprises a main control chip U12 and a load chip U24; the main control chip U12 provides power supply support for the load chip U24;
the main control chip U12 is provided with an input decoupling circuit, a resistor R951, a capacitor C852, a capacitor C857, a resistor R949 and an output decoupling circuit; the input decoupling circuit is added to a power supply input pin of the main control chip U12; the resistor R951 is connected to a feedback pin of the main control chip U12; a capacitor C852 is added to an output tracking and soft start pin of the main control chip U12; a capacitor C857 is added to a current threshold control and phase compensation pin of the main control chip U12; the resistor R949 is used as a ground isolating resistor of the main control chip U12; an output decoupling circuit is added to a power supply output pin of the main control chip U12.
As an optimal scheme of an FPGA power supply circuit on a low-power use occasion, an input decoupling circuit comprises a decoupling capacitor C855, a decoupling capacitor C851, a decoupling capacitor C849 and a decoupling capacitor C854;
decoupling capacitor C855, decoupling capacitor C851, decoupling capacitor C849 and decoupling capacitor C854 are connected in parallel and then are added to the power supply input pin of main control chip U12.
As the preferred scheme of the FPGA power supply circuit in the low-power use occasion, the output decoupling circuit comprises a decoupling capacitor C841, a decoupling capacitor C838, a decoupling capacitor C846, a decoupling capacitor C839, a decoupling capacitor C840, a decoupling capacitor C848, a decoupling capacitor C842, a decoupling capacitor C843, a decoupling capacitor C836, a decoupling capacitor C860, a decoupling capacitor C861 and a decoupling capacitor C858;
a decoupling capacitor C841, a decoupling capacitor C838, a decoupling capacitor C846, a decoupling capacitor C839, a decoupling capacitor C840 and a decoupling capacitor C848 are connected in parallel and then are added to a power supply output pin VCC _ INT of the main control chip U12;
a decoupling capacitor C842, a decoupling capacitor C843 and a decoupling capacitor C836 are connected in parallel and then are added to a power supply output pin VCC _ AUX of the main control chip U12;
the decoupling capacitor C860, the decoupling capacitor C861 and the decoupling capacitor C858 are connected in parallel and then are added to a power supply output pin VCC _3V3 of the main control chip U12.
As the preferred scheme of the FPGA power supply circuit in the low-power use occasion, the resistor R951 is added to the feedback pin FB1 and the feedback pin FB2 of the main control chip U12 through the first channel and the second channel.
The FPGA power supply circuit used in a low-power use occasion preferably comprises a resistor R952 and a resistor R950, wherein the resistor R952 is added to a feedback pin FB3 of a main control chip U12 through a channel III; the resistor R950 is connected to the feedback pin FB4 of the main control chip U12 through the channel four.
As the preferred scheme of the FPGA power supply circuit in the low-power use occasion, the FPGA power supply circuit further comprises a capacitor C856 and a capacitor C850, wherein the capacitor C856 and the capacitor C850 are respectively added to the other output tracking and soft start pins of the main control chip U12.
As the preferred scheme of the FPGA power supply circuit in the low-power use occasion, the FPGA power supply circuit further comprises a capacitor C847 and a capacitor C853, wherein the capacitor C847 and the capacitor C853 are respectively added to other current threshold control and phase compensation pins of the main control chip U12.
The utility model has the advantages of it is following: the main control chip U12 and the load chip U24 are arranged; the main control chip U12 provides power supply support for the load chip U24; the main control chip U12 is provided with an input decoupling circuit, a resistor R951, a capacitor C852, a capacitor C857, a resistor R949 and an output decoupling circuit; the input decoupling circuit is added to a power supply input pin of the main control chip U12; the resistor R951 is connected to a feedback pin of the main control chip U12; a capacitor C852 is added to an output tracking and soft start pin of the main control chip U12; a capacitor C857 is added to a current threshold control and phase compensation pin of the main control chip U12; the resistor R949 is used as a ground isolating resistor of the main control chip U12; an output decoupling circuit is added to a power supply output pin of the main control chip U12. The utility model discloses be fit for the FPGA miniwatt usage occasion, use a chip, solve VCC _ INT, VCC _ BRAM, VCC _ AUX, the trouble of the multiple voltage power supply of each part of VCC _3V3, and can realize going up the control of electric time sequence, satisfy and go up the electric time sequence requirement, reduce the complexity of hardware design on the one hand, on the other hand reduces the area that occupies PCB, and reduce cost improves the reliability of design and the holistic stability of system.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary, and that other embodiments can be derived from the drawings provided by those of ordinary skill in the art without inventive effort.
The structure, ratio, size and the like shown in the present specification are only used for matching with the content disclosed in the specification, so as to be known and read by people familiar with the technology, and are not used for limiting the limit conditions which can be implemented by the present invention, so that the present invention has no technical essential significance, and any structure modification, ratio relationship change or size adjustment should still fall within the scope which can be covered by the technical content disclosed by the present invention without affecting the efficacy and the achievable purpose of the present invention.
Fig. 1 is a schematic circuit diagram of a main control chip U12 of an FPGA power supply circuit in a low-power use situation provided in an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of a first part of a load chip U24 of an FPGA power supply circuit for a high-power application site according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a second part of a load chip U24 of the FPGA power supply circuit in a high-power application scenario according to an embodiment of the present invention;
fig. 4 is a schematic circuit diagram of a third part of the load chip U24 of the FPGA power supply circuit in the high-power application scenario provided in the embodiment of the present invention.
Detailed Description
The present invention is described in terms of specific embodiments, and other advantages and benefits of the present invention will become apparent to those skilled in the art from the following disclosure. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Because the design of the existing FPGA power supply circuit is relatively complex, the occupied area of a PCB is large, and the layout pressure is too large even for a board which is small in the PCB and is tense in layout. The method aims to solve the trouble of supplying power by various voltages of VCC _ INT, VCC _ BRAM, VCC _ AUX and VCC _3V3, and can realize the control of power-on time sequence, meet the requirements of power-on time sequence, reduce the complexity of hardware design, reduce the area of occupied PCB, reduce cost, and improve the reliability of design and the stability of the whole system. The utility model provides the following specific implementation scheme.
Referring to fig. 1, fig. 2, fig. 3 and fig. 4, an embodiment of the present invention provides an FPGA power supply circuit for a low-power application occasion, including a main control chip U12 and a load chip U24; the main control chip U12 provides power supply support for the load chip U24; the load chip U24 adopts SMQ7K325TFFG900 IP;
the main control chip U12 is provided with an input decoupling circuit, a resistor R951, a capacitor C852, a capacitor C857, a resistor R949 and an output decoupling circuit; the input decoupling circuit is added to a power supply input pin of the main control chip U12; the resistor R951 is connected to a feedback pin of the main control chip U12; a capacitor C852 is added to an output tracking and soft start pin of the main control chip U12; a capacitor C857 is added to a current threshold control and phase compensation pin of the main control chip U12; the resistor R949 is used as a ground isolation resistor of the main control chip U12; an output decoupling circuit is added to a power supply output pin of the main control chip U12.
In this embodiment, the input decoupling circuit includes a decoupling capacitor C855, a decoupling capacitor C851, a decoupling capacitor C849, and a decoupling capacitor C854; decoupling capacitor C855, decoupling capacitor C851, decoupling capacitor C849 and decoupling capacitor C854 are connected in parallel and then are added to the power supply input pin of main control chip U12. The output decoupling circuit comprises a decoupling capacitor C841, a decoupling capacitor C838, a decoupling capacitor C846, a decoupling capacitor C839, a decoupling capacitor C840, a decoupling capacitor C848, a decoupling capacitor C842, a decoupling capacitor C843, a decoupling capacitor C836, a decoupling capacitor C860, a decoupling capacitor C861 and a decoupling capacitor C858; a decoupling capacitor C841, a decoupling capacitor C838, a decoupling capacitor C846, a decoupling capacitor C839, a decoupling capacitor C840 and a decoupling capacitor C848 are connected in parallel and then are added to a power supply output pin VCC _ INT of the main control chip U12; a decoupling capacitor C842, a decoupling capacitor C843 and a decoupling capacitor C836 are connected in parallel and then are added to a power supply output pin VCC _ AUX of the main control chip U12; the decoupling capacitor C860, the decoupling capacitor C861 and the decoupling capacitor C858 are connected in parallel and then are added to a power supply output pin VCC _3V3 of the main control chip U12.
In this embodiment, the resistor R951 is added to the feedback pin FB1 and the feedback pin FB2 of the main control chip U12 through the first channel and the second channel. In addition, the circuit also comprises a resistor R952 and a resistor R950, wherein the resistor R952 is added to a feedback pin FB3 of the main control chip U12 through a channel III; the resistor R950 is connected to the feedback pin FB4 of the main control chip U12 through the channel four. The circuit also comprises a capacitor C856 and a capacitor C850, wherein the capacitor C856 and the capacitor C850 are respectively added on other output tracking and soft start pins of the main control chip U12. The current threshold compensation circuit also comprises a capacitor C847 and a capacitor C853, wherein the capacitor C847 and the capacitor C853 are respectively added to the other current threshold control and phase compensation pins of the main control chip U12.
Specifically, the main control chip U12 adopts SM4644MPY, can provide four ways of 4A current, is flexible in configuration, can be configured according to actual needs, is used in parallel with four channels, can provide a single way of 16A current, and can provide 20A peak current to the maximum.
The electronic elements and functional principles adopted in the peripheral circuit of the main control chip U12 are as follows:
decoupling capacitor C855(22 uF/25V): the input decoupling capacitor is used as an input decoupling capacitor and is added to a power supply input pin of the main control chip U12, so as to ensure low noise and stability of an input power supply;
decoupling capacitor C851(22 uF/25V): the input decoupling capacitor is used as an input decoupling capacitor and is added to a power supply input pin of the main control chip U12, so as to ensure low noise and stability of an input power supply;
decoupling capacitor C849(22 uF/25V): the input decoupling capacitor is used as an input decoupling capacitor and is added to a power supply input pin of the main control chip U12, so as to ensure low noise and stability of an input power supply;
decoupling capacitor C854(22 uF/25V): the input decoupling capacitor is used as an input decoupling capacitor and is added to a power supply input pin of the main control chip U12, so as to ensure low noise and stability of an input power supply;
resistance R951 (90.9K/1%): and feedback pins FB1 and FB2 (negative input pin of the error amplifier) of the first channel and the second channel. Inside the main control chip U12, the pin is connected to the voltage output pin of the channel through a 60.4KR resistor. The requirement that the voltage of the channel I and the voltage of the channel II output 1.0V is realized by connecting a resistor R951 (90.9K/1%) between the FB1 and FB2 and a ground pin, and the maximum output current can reach 10A;
capacitance C852(100 nF/16V): a capacitor is configured on an output tracking and soft start pin of the main control chip U12 to provide a soft start function;
resistance R952 (30.1K/1%): channel three feedback pin FB3 (negative input pin of error amplifier). Inside the main control chip U12, the pin is connected to the voltage output pin of the channel through a 60.4KR resistor. The requirement that three-channel voltage outputs 1.8V is realized by connecting a resistor R952 (30.1K/1%) between the FB3 and a ground pin, and the maximum output current can reach 5A;
capacitance C856(100 nF/16V): a capacitor is configured on the other output tracking and soft start pin of the main control chip U12 to provide a soft start function;
resistance R950 (13.3K/1%): and a feedback pin FB4 (the negative input pin of the error amplifier) for channel four. Inside the main control chip U12, the pin is connected to the voltage output pin of the channel through a 60.4KR resistor. The requirement that the four-channel voltage outputs 3.3V is realized through the connecting resistor R950 (13.3K/1%) between the FB4 and the ground pin, and the maximum output current can reach 5A;
capacitance C850(100 nF/16V): a capacitor is arranged on the other output tracking and soft start pin of the main control chip U12 to provide a soft start function;
capacitance C857(100 nF/16V): a current threshold control and phase compensation pin configured on the main control chip U12 is reserved, the threshold of an internal current comparator is proportional to the voltage, and compensation is arranged in a device, so that the capacitor is reserved and designed, and can be adjusted according to actual conditions during debugging;
capacitance C847(100 nF/16V): a current threshold control and phase compensation pin configured on the main control chip U12 is reserved, the threshold of an internal current comparator is proportional to the voltage, and compensation is arranged in a device, so that the capacitor is reserved and designed, and can be adjusted according to actual conditions during debugging;
capacitance C853(100 nF/16V): a current threshold control and phase compensation pin configured on the main control chip U12 is reserved, the threshold of an internal current comparator is proportional to the voltage, and compensation is arranged in a device, so that the capacitor is reserved and designed, and can be adjusted according to actual conditions during debugging;
resistance R949 (0R): the ground isolation resistor is designed as a digital ground and an analog ground to ensure that the digital ground and the analog ground do not interfere with each other, and the stability and the anti-interference capability of the system are improved;
decoupling capacitor C841(47 uF/16V): the output decoupling capacitor is used as an output decoupling capacitor and is added to a power supply output pin of the main control chip U12, so as to ensure low noise and stability of an output power supply;
decoupling capacitor C838(47 uF/16V): the output decoupling capacitor is used as an output decoupling capacitor and is added to a power supply output pin of the main control chip U12, so as to ensure low noise and stability of an output power supply;
decoupling capacitor C846(100 nF/16V): the output decoupling capacitor is used as an output decoupling capacitor and is added to a power supply output pin of the main control chip U12, so as to ensure low noise and stability of an output power supply;
decoupling capacitor C839(47 uF/16V): the output decoupling capacitor is used as an output decoupling capacitor and is added to a power supply output pin of the main control chip U12, so as to ensure low noise and stability of an output power supply;
decoupling capacitor C840(47 uF/16V): the output decoupling capacitor is used as an output decoupling capacitor and is added to a power supply output pin of the main control chip U12, so as to ensure low noise and stability of an output power supply;
decoupling capacitor C848(100 nF/16V): the output decoupling capacitor is used as an output decoupling capacitor and is added to a power supply output pin of the main control chip U12, so as to ensure low noise and stability of an output power supply;
decoupling capacitor C842(47 uF/16V): the output decoupling capacitor is used as an output decoupling capacitor and is added to a power supply output pin of the main control chip U12, so as to ensure low noise and stability of an output power supply;
decoupling capacitor C843(47 uF/16V): the output decoupling capacitor is used as an output decoupling capacitor and is added to a power supply output pin of the main control chip U12, so as to ensure low noise and stability of an output power supply;
decoupling capacitance C836(100 nF/16V): the output decoupling capacitor is used as an output decoupling capacitor and is added to a power supply output pin of the main control chip U12, so as to ensure low noise and stability of an output power supply;
decoupling capacitor C860(47 uF/16V): the output decoupling capacitor is used as an output decoupling capacitor and is added to a power supply output pin of the main control chip U12, so as to ensure low noise and stability of an output power supply;
decoupling capacitor C861(47 uF/16V): the output decoupling capacitor is used as an output decoupling capacitor and is added to a power supply output pin of the main control chip U12, so as to ensure low noise and stability of an output power supply;
decoupling capacitor C858(100 nF/16V): the output decoupling capacitor is added to a power supply output pin of the main control chip U12, and is used for ensuring low noise and stability of an output power supply.
In summary, the utility model is provided with a main control chip U12 and a load chip U24; the main control chip U12 provides power supply support for the load chip U24; the main control chip U12 is provided with an input decoupling circuit, a resistor R951, a capacitor C852, a capacitor C857, a resistor R949 and an output decoupling circuit; the input decoupling circuit is added to a power supply input pin of the main control chip U12; the resistor R951 is connected to a feedback pin of the main control chip U12; a capacitor C852 is added to an output tracking and soft start pin of the main control chip U12; a capacitor C857 is added to a current threshold control and phase compensation pin of the main control chip U12; the resistor R949 is used as a ground isolating resistor of the main control chip U12; an output decoupling circuit is added to a power supply output pin of the main control chip U12. The input decoupling circuit comprises a decoupling capacitor C855, a decoupling capacitor C851, a decoupling capacitor C849 and a decoupling capacitor C854; decoupling capacitor C855, decoupling capacitor C851, decoupling capacitor C849 and decoupling capacitor C854 are connected in parallel and then are added to the power supply input pin of main control chip U12. The output decoupling circuit comprises a decoupling capacitor C841, a decoupling capacitor C838, a decoupling capacitor C846, a decoupling capacitor C839, a decoupling capacitor C840, a decoupling capacitor C848, a decoupling capacitor C842, a decoupling capacitor C843, a decoupling capacitor C836, a decoupling capacitor C860, a decoupling capacitor C861 and a decoupling capacitor C858; a decoupling capacitor C841, a decoupling capacitor C838, a decoupling capacitor C846, a decoupling capacitor C839, a decoupling capacitor C840 and a decoupling capacitor C848 are connected in parallel and then are added to a power supply output pin VCC _ INT of the main control chip U12; a decoupling capacitor C842, a decoupling capacitor C843 and a decoupling capacitor C836 are connected in parallel and then are added to a power supply output pin VCC _ AUX of the main control chip U12; the decoupling capacitor C860, the decoupling capacitor C861 and the decoupling capacitor C858 are connected in parallel and then are added to a power supply output pin VCC _3V3 of the main control chip U12. The utility model discloses be fit for the FPGA miniwatt usage occasion, use a chip, solve VCC _ INT, VCC _ BRAM, VCC _ AUX, the trouble of the multiple voltage power supply of each part of VCC _3V3, and can realize going up the control of electric time sequence, satisfy and go up the electric time sequence requirement, reduce the complexity of hardware design on the one hand, on the other hand reduces the area that occupies PCB, and reduce cost improves the reliability of design and the holistic stability of system.
Although the invention has been described in detail with respect to the general description and the specific embodiments, it will be apparent to those skilled in the art that modifications and improvements can be made based on the invention. Therefore, such modifications and improvements are intended to be within the scope of the invention as claimed.
Claims (7)
1. An FPGA power supply circuit for a low-power use occasion is characterized by comprising a main control chip U12 and a load chip U24; the main control chip U12 provides power supply support for the load chip U24;
the main control chip U12 is provided with an input decoupling circuit, a resistor R951, a capacitor C852, a capacitor C857, a resistor R949 and an output decoupling circuit; the input decoupling circuit is added to a power supply input pin of the main control chip U12; the resistor R951 is connected to a feedback pin of the main control chip U12; a capacitor C852 is added to an output tracking and soft start pin of the main control chip U12; a capacitor C857 is added on a current threshold control and phase compensation pin of the main control chip U12; the resistor R949 is used as a ground isolating resistor of the main control chip U12; an output decoupling circuit is added to a power supply output pin of the main control chip U12.
2. The FPGA power supply circuit for a low-power use occasion according to claim 1, wherein the input decoupling circuit comprises a decoupling capacitor C855, a decoupling capacitor C851, a decoupling capacitor C849 and a decoupling capacitor C854;
decoupling capacitor C855, decoupling capacitor C851, decoupling capacitor C849 and decoupling capacitor C854 are connected in parallel and then are added to the power supply input pin of main control chip U12.
3. The FPGA power supply circuit of claim 2, wherein the output decoupling circuit comprises a decoupling capacitor C841, a decoupling capacitor C838, a decoupling capacitor C846, a decoupling capacitor C839, a decoupling capacitor C840, a decoupling capacitor C848, a decoupling capacitor C842, a decoupling capacitor C843, a decoupling capacitor C836, a decoupling capacitor C860, a decoupling capacitor C861 and a decoupling capacitor C858;
a decoupling capacitor C841, a decoupling capacitor C838, a decoupling capacitor C846, a decoupling capacitor C839, a decoupling capacitor C840 and a decoupling capacitor C848 are connected in parallel and then are added to a power supply output pin VCC _ INT of the main control chip U12;
a decoupling capacitor C842, a decoupling capacitor C843 and a decoupling capacitor C836 are connected in parallel and then are added to a power supply output pin VCC _ AUX of the main control chip U12;
the decoupling capacitor C860, the decoupling capacitor C861 and the decoupling capacitor C858 are connected in parallel and then are added to a power supply output pin VCC _3V3 of the main control chip U12.
4. The FPGA power supply circuit of claim 3, wherein the resistor R951 is connected to the feedback pin FB1 and the feedback pin FB2 of the main control chip U12 through a first channel and a second channel.
5. The FPGA power supply circuit of claim 4, further comprising a resistor R952 and a resistor R950, wherein the resistor R952 is applied to the feedback pin FB3 of the main control chip U12 through the channel III; the resistor R950 is connected to the feedback pin FB4 of the main control chip U12 through the channel four.
6. The FPGA power supply circuit for a small power use occasion according to claim 5, further comprising a capacitor C856 and a capacitor C850, wherein the capacitor C856 and the capacitor C850 are respectively added to the other output tracking and soft start pins of the main control chip U12.
7. The FPGA power supply circuit of claim 6, further comprising a capacitor C847 and a capacitor C853, wherein the capacitor C847 and the capacitor C853 are respectively added to the other current threshold control and phase compensation pins of the main control chip U12.
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