CN201298810Y - Electrification sequence control circuit of chip voltages - Google Patents
Electrification sequence control circuit of chip voltages Download PDFInfo
- Publication number
- CN201298810Y CN201298810Y CNU200820213339XU CN200820213339U CN201298810Y CN 201298810 Y CN201298810 Y CN 201298810Y CN U200820213339X U CNU200820213339X U CN U200820213339XU CN 200820213339 U CN200820213339 U CN 200820213339U CN 201298810 Y CN201298810 Y CN 201298810Y
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- China
- Prior art keywords
- voltage
- chip
- voltage input
- control circuit
- sequence control
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Abstract
The utility model relates to a electrification sequence control circuit of chip voltages, the voltages of the chip including voltages from V1 to VN of the first, second until the Nth voltage input ports separately, wherein V1 < V2 < < VN, the control circuit including a voltage input source VCC; first, second, , Nth voltage switching circuits connected with the voltage input source VCC for switching the voltage input source VCC into the voltages from V1 to VN; capacitance time-delay units from the first to the Nth connected with the voltage switching circuits from the first to the Nth separately for providing working voltage for each voltage input ports of the chip, wherein the capacitance from C1 to CN of the capacitance time-delay units meet the following relation: C1 < C2 < < CN. By means of setting capacitances with different capacities between the voltage input ends of the chip and each voltage switching circuit, various voltage input ends of the chip is supplied with power in sequence according to the capacitance charging time, thus it is capable saving extra voltage management chips.
Description
Technical field
The utility model relates to control circuit, more particularly, relates to a kind of electric sequence control circuit of chip voltage.
Background technology
Need get well several voltages during some chip operation, as chip 3.3V, 1.5V commonly used, 1V or the like.Operating voltage if desired powers on simultaneously and can bring damage to chip, for being very difficult for this to happen usually by control electric sequence (being realized to high voltage by low-voltage).Voltage electric sequence is in the past realized by some voltage management chip usually, can increase the cost of circuit so undoubtedly.
The utility model content
The technical problems to be solved in the utility model is, realizes the defective that causes cost to increase by some voltage management chip usually at the above-mentioned voltage electric sequence of prior art, and a kind of electric sequence control circuit of chip voltage is provided.
The technical scheme that its technical problem that solves the utility model adopts is: construct a kind of electric sequence control circuit of chip voltage, described chip has voltage and is respectively V
1, V
2..., V
NThe 1st, 2 ..., N voltage input end mouth, wherein V
1＜V
2＜...＜V
N, according to the utility model, described electric sequence control circuit comprises voltage input source V
CC, with voltage input source V
CCConnect and be used for voltage input source V
CCBe converted to V respectively
1, V
2..., V
NThe 1st, 2 ..., the N voltage conversion circuit, with the 1st, 2 ..., the N voltage conversion circuit connect respectively be used to chip the 1st, 2 ..., N voltage input end mouth provide operating voltage the 1st, 2 ..., N electric capacity delay unit, wherein the 1st, 2 ..., the capacity C of N electric capacity delay unit
1＜C
2＜...＜C
N
In electric sequence control circuit described in the utility model, described the 1st, 2 ..., N electric capacity delay unit comprises the capacitor of one or more parallel connections respectively.
In electric sequence control circuit described in the utility model, described electric sequence control circuit comprises 5V voltage input source V
CC, with 5V voltage input source V
CCThe 1st, 2,3 voltage conversion circuits that connect, with the 1st, 2, the 3 electric capacity delay units that the 1st, 2,3 voltage conversion circuits are connected respectively, wherein said chip has the voltage input end mouth that circuit is respectively 1V, 1.5V, 3.3V.
In electric sequence control circuit described in the utility model, described the 1st electric capacity delay unit comprises a 47uF capacitor, described the 2nd electric capacity delay unit comprises the 47uF capacitor of two parallel connections, and described the 3rd electric capacity delay unit comprises the 47uF capacitor of three parallel connections.
Implement the electric sequence control circuit of chip voltage of the present utility model, has following beneficial effect: by between the voltage input end of voltage conversion circuit and chip, the different electric capacity of amount of capacity being set, be followed successively by the different voltage input end power supplies of chip like this according to the length of capacitor charging time, thereby saved extra voltage management chip, reduced circuit cost.
Description of drawings
The utility model is described in further detail below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the schematic diagram of the electric sequence control circuit of chip voltage of the present utility model;
Fig. 2 is the 3.3V circuit theory diagrams of an embodiment of electric sequence control circuit of the present utility model;
Fig. 3 is the 1.5V circuit theory diagrams of an embodiment of electric sequence control circuit of the present utility model;
Fig. 4 is the 1V circuit theory diagrams of an embodiment of electric sequence control circuit of the present utility model;
Fig. 5 is the chip schematic diagram of an embodiment of electric sequence control circuit of the present utility model.
Embodiment
In order to make technical problem to be solved in the utility model, technical scheme and beneficial effect clearer,, the utility model is further elaborated below in conjunction with drawings and Examples.Should be understood that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
As shown in Figure 1, there is shown the electric sequence control circuit of chip voltage of the present utility model.Shown chip 1 has voltage and is respectively V
1, V
2..., V
NThe 1st, 2 ..., N voltage input end mouth, wherein V
1＜V
2＜...＜V
NBecause required voltage powers on simultaneously and can cause damage to chip during chip 1 work, so the utility model adds the electric capacity delay unit and replaces traditional voltage management chip, electric sequence to chip voltage is controlled, and this electric sequence can effectively be controlled the impact that high voltage brings chip 1.
According to the utility model, above-mentioned electric sequence control circuit comprises voltage input source V
CC, the 1st, 2 ..., the N voltage conversion circuit (among the figure with Reference numeral 21,22 ..., N represents) and the 1st, 2 ...., N electric capacity delay unit (among the figure with Reference numeral 31,32 ..., N represents).1st, 2 ..., the N voltage conversion circuit respectively with voltage input source V
CCConnect, be used for voltage input source V
CCBe converted to V respectively
1, V
2..., V
N1st, 2 ..., N electric capacity delay unit respectively with the 1st, 2 ..., the N voltage conversion circuit connects, be used to chip the 1st, 2 ..., N voltage input end mouth provides operating voltage, wherein the 1st, 2 ..., the capacity C of N electric capacity delay unit
1＜C
2＜...＜C
N
According to this configuration, voltage input source V
CCAfter converting correspondent voltage to by voltage conversion circuit the electric capacity delay unit is charged, the corresponding chip of the electric capacity delay unit of capacity minimum needs the voltage input end mouth that powers at first, the electric capacity delay unit of capacity minimum at first is full of electricity and is corresponding chip voltage input port power supply, and the electric capacity delay unit that increases gradually of capacity is full of electricity successively and is corresponding chip voltage input port power supply then.For example, 5V voltage input source obtains the voltage of 1V, 1.5V, 3.3V after conversion, and 1V connects 6uF electric capacity, 1.5V connect 18uF electric capacity, 3.3V connect 48uF electric capacity, like this capacitance minimum will be full of earlier electricity to chip power supply, the order of power supply is 1V, 1.5V, 3.3V just.
As mentioned above, the 1st, 2 ..., N electric capacity delay unit comprises the capacitor of one or more parallel connections respectively because the total capacity of a plurality of shunt capacitances is a plurality of capacitance sums, a total capacity that therefore only needs to guarantee the electric capacity delay unit gets final product.For ascending a plurality of operating voltage controls of same chip, when the corresponding electric capacity of configuration, difference blanking time that powers on of each voltage request, the capacitance ratio of configuration does not have rule.
To shown in Figure 5, there is shown the schematic diagram of an embodiment of electric sequence control circuit of the present utility model as Fig. 2.Fig. 2 to Fig. 5 is actual to be a circuit diagram, because domain is divided into 1V circuit, 1.5V circuit, 3.3V circuit and four modules of chip circuit at this.
Shown chip has the voltage input end mouth that circuit is respectively 1V, 1.5V, 3.3V.Comprise 5V voltage input source V according to electric sequence control circuit of the present utility model
CC, with 5V voltage input source V
CCThe 1st, 2,3 voltage conversion circuits that connect and the 1st, 2, the 3 electric capacity delay units that are connected respectively with the 1st, 2,3 voltage conversion circuits.
Wherein, the 1st electric capacity delay unit comprises a 47uF capacitor (being C24), the 2nd electric capacity delay unit comprises the 47uF capacitor (being C2, C3) of two parallel connections, and described the 3rd electric capacity delay unit comprises the 47uF capacitor (being C13, C15, C16) of three parallel connections.It should be noted that not only to show main several capacitors among the figure, also show shunt capacitance with it in parallel in addition, these shunt capacitances are to the not too big influence of charging of electric capacity delay unit, do not remember so can ignore at this.
The operating voltage of shown chip U4 demand is 1V, 1.5V, 3.3V, and electric sequence adopts 1V to the safest to chip U4 when 1.5V arrives 3.3V again.The 5V voltage transitions is simultaneously corresponding electric capacity to be charged behind 1V, 1.5V, the 3.3V, and electric capacity is full of the chip U4 power supply of electricity back to these three kinds of operating voltages of needs.According to this configuration, the saturated voltage that charges is 1V, 1.5V, 3.3V in proper order, to the power supply order of chip U4 just 1V, 1.5V, 3.3V.So just the voltage mode from low to high that realizes is powered to chip U4, thereby has reduced the damage to chip U4.
The utility model is by being provided with the different electric capacity of amount of capacity between the voltage input end of voltage conversion circuit and chip, be followed successively by the different voltage input end power supplies of chip like this according to the length of capacitor charging time, thereby saved extra voltage management chip, reduced circuit cost.
The above only is preferred embodiment of the present utility model; not in order to restriction the utility model; any modification of being done within every spirit of the present utility model and the principle, be equal to and replace and improvement etc., all should be included within the protection range of the present utility model.
Claims (4)
1, a kind of electric sequence control circuit of chip voltage, described chip has voltage and is respectively V
1, V
2..., V
NThe 1st, 2 ..., N voltage input end mouth, wherein V
1＜V
2＜...＜V
N, it is characterized in that described electric sequence control circuit comprises voltage input source V
CC, with voltage input source V
CCConnect and be used for voltage input source V
CCBe converted to V respectively
1, V
2..., V
NThe 1st, 2 ..., the N voltage conversion circuit, with the 1st, 2 ..., the N voltage conversion circuit connect respectively be used to chip the 1st, 2 ..., N voltage input end mouth provide operating voltage the 1st, 2 ..., N electric capacity delay unit, wherein the 1st, 2 ..., the capacity C of N electric capacity delay unit
1＜C
2＜...＜C
N
2, electric sequence control circuit according to claim 1 is characterized in that, described the 1st, 2 ..., N electric capacity delay unit comprises the capacitor of one or more parallel connections respectively.
3, according to claim 1 or 2 arbitrary described electric sequence control circuits, it is characterized in that described electric sequence control circuit comprises 5V voltage input source V
CC, with 5V voltage input source V
CCThe 1st, 2,3 voltage conversion circuits that connect, with the 1st, 2, the 3 electric capacity delay units that the 1st, 2,3 voltage conversion circuits are connected respectively, wherein said chip has the voltage input end mouth that circuit is respectively 1V, 1.5V, 3.3V.
4, electric sequence control circuit according to claim 3, it is characterized in that, described the 1st electric capacity delay unit comprises a 47uF capacitor, and described the 2nd electric capacity delay unit comprises the 47uF capacitor of two parallel connections, and described the 3rd electric capacity delay unit comprises the 47uF capacitor of three parallel connections.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU200820213339XU CN201298810Y (en) | 2008-11-07 | 2008-11-07 | Electrification sequence control circuit of chip voltages |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU200820213339XU CN201298810Y (en) | 2008-11-07 | 2008-11-07 | Electrification sequence control circuit of chip voltages |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201298810Y true CN201298810Y (en) | 2009-08-26 |
Family
ID=41044797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU200820213339XU Expired - Fee Related CN201298810Y (en) | 2008-11-07 | 2008-11-07 | Electrification sequence control circuit of chip voltages |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201298810Y (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102902567A (en) * | 2012-11-06 | 2013-01-30 | 上海斐讯数据通信技术有限公司 | Peripheral circuit of DC-DC (Direct Current) power chip |
| CN105024370A (en) * | 2015-07-29 | 2015-11-04 | 国核自仪系统工程有限公司 | IO daughter card sequential starting control circuit |
| CN105207463A (en) * | 2015-10-28 | 2015-12-30 | 上海斐讯数据通信技术有限公司 | Input power supply control circuit |
| CN108519806A (en) * | 2018-04-26 | 2018-09-11 | 北京比特大陆科技有限公司 | A kind of chip controls method, apparatus, computer equipment and computer storage media |
-
2008
- 2008-11-07 CN CNU200820213339XU patent/CN201298810Y/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102902567A (en) * | 2012-11-06 | 2013-01-30 | 上海斐讯数据通信技术有限公司 | Peripheral circuit of DC-DC (Direct Current) power chip |
| CN102902567B (en) * | 2012-11-06 | 2015-09-02 | 上海斐讯数据通信技术有限公司 | A kind of peripheral circuit of DC-DC power source chip |
| CN105024370A (en) * | 2015-07-29 | 2015-11-04 | 国核自仪系统工程有限公司 | IO daughter card sequential starting control circuit |
| CN105207463A (en) * | 2015-10-28 | 2015-12-30 | 上海斐讯数据通信技术有限公司 | Input power supply control circuit |
| CN108519806A (en) * | 2018-04-26 | 2018-09-11 | 北京比特大陆科技有限公司 | A kind of chip controls method, apparatus, computer equipment and computer storage media |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090826 Termination date: 20171107 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |