CN210518267U - Low-rate level conversion circuit - Google Patents
Low-rate level conversion circuit Download PDFInfo
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- CN210518267U CN210518267U CN201921353350.0U CN201921353350U CN210518267U CN 210518267 U CN210518267 U CN 210518267U CN 201921353350 U CN201921353350 U CN 201921353350U CN 210518267 U CN210518267 U CN 210518267U
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Abstract
The utility model discloses a level conversion circuit of low rate, including switch element and smooth unit, switch element's input is used for the electricity to connect outside low level input signal, switch element's output high level signal, switch element's control end with smooth unit's output electricity is connected, smooth unit's input is used for the electricity to connect outside voltage signal. The utility model relates to a low-speed level conversion circuit, which is characterized in that a switch unit and a smoothing unit are arranged, so that the circuit structure of the level conversion circuit is simple, and the design and the connection of each electronic component are convenient; and can also avoid the level spike and sunken that the device characteristic of transistor itself arouses to guarantee the normal stable work of circuit, improve the stability of circuit and equipment.
Description
Technical Field
The utility model relates to a level conversion circuit field especially relates to a level conversion circuit of low rate.
Background
At present, no matter a mos transistor or a transistor is adopted in the design of the level conversion circuit, namely, no matter a 5V level is converted into a 3.3V level or a 3.3V level is converted into a 5V level, 2 mos transistors or 2 transistors are adopted in a matched mode. With the wide application of the level conversion circuit and the popularization of the internet of things technology, various intelligent wearable devices and intelligent household products generally emerge as bamboo shoots in spring after rain, and based on the technology and the products, the requirements on data transmission rate are low, meanwhile, product positioning is generally miniaturized and high in market competitiveness, under the large environment, the defects of the traditional design scheme are increasingly highlighted due to cost pressure and component selection, whether the traditional complex and high-cost level conversion circuit can be replaced by the low-cost and low-space level conversion circuit under the low-rate requirement is the technical problem which needs to be considered by technical personnel in the field.
SUMMERY OF THE UTILITY MODEL
The utility model aims to overcome the defects in the prior art, and provides a low-speed level conversion circuit which has simple circuit structure and is convenient for the design and connection of each electronic component; and can also avoid the level spike and sunken that the device characteristic of transistor itself arouses to guarantee the normal stable work of circuit, improve the stability of circuit and equipment.
The purpose of the utility model is realized through the following technical scheme:
a low rate level shift circuit comprising: the input end of the switch unit is used for being electrically connected with an external low-level input signal, the output end of the switch unit outputs a high-level signal, the control end of the switch unit is electrically connected with the output end of the smoothing unit, and the input end of the smoothing unit is used for being electrically connected with an external voltage signal;
the switch unit comprises a switch tube and a resistor R1, wherein the control end of the switch tube is electrically connected with the output end of the smoothing unit, the input end of the switch tube is used for electrically connecting an external low-level input signal Vin, the output end of the switch tube is used as the output end of the switch unit to output a high-level signal Vout, the first end of the resistor R1 is electrically connected with the output end of the switch tube, and the second end of the resistor R1 is used for connecting an external direct-current voltage;
the smoothing unit comprises a resistor R2 and a capacitor C1, a first end of the resistor R2 is electrically connected with one end of the capacitor C1 and a control end of the switch tube respectively, a second end of the resistor R2 is used for being electrically connected with an external voltage signal, and the other end of the capacitor C1 is grounded.
In one embodiment, the switching tube is a transistor Q1, a base of the transistor Q1 is electrically connected to the output terminal of the smoothing unit, an emitter of the transistor Q1 is used for electrically connecting an external low-level input signal Vin, a collector of the transistor Q1 serves as the output terminal of the switching unit to output a high-level signal Vout, and a first end of the resistor R1 is electrically connected to an emitter of the transistor Q1.
In one embodiment, the capacitor C1 has a size of 20pf to 150 pf.
In one embodiment, the level shift circuit further includes a transceiver unit and a main control connection unit, an output terminal of the transceiver unit is electrically connected to an input terminal of the switch unit, and a receiving terminal of the main control connection unit is electrically connected to an output terminal of the switch unit.
In one embodiment, the transceiver unit includes a transceiver chip U1, a resistor R3, and a capacitor C2, a power supply input terminal of the transceiver chip U1 is electrically connected to an external first input voltage, a first terminal of the resistor R3 is electrically connected to the first input voltage, a second terminal of the resistor R3 is electrically connected to an enable terminal of the transceiver chip U1, and an IO pin of the transceiver chip U1 is also electrically connected to an input terminal of the switch unit.
In one embodiment, the master control connection unit includes a connection interface and a resistor R4, a first end of the resistor R4 is electrically connected to the output end of the switch unit, a second end of the resistor R4 is electrically connected to the connection interface, and the connection interface is further configured to be electrically connected to an external second input voltage.
In one embodiment, the level shift circuit further includes a signal conversion unit, an input end of the signal conversion unit is electrically connected to the connection interface, and an output end of the signal conversion unit is electrically connected to a signal receiving pin of the transceiver unit.
In one embodiment, the signal conversion unit includes a resistor R5, a resistor R6, a capacitor C3, a capacitor C4, and a transistor Q2, an emitter of the transistor Q2 is electrically connected to the connection interface, a collector of the transistor Q2 is electrically connected to an output terminal of the switching unit, a base of the transistor Q2 is electrically connected to one end of the resistor R5 and one end of the capacitor C3, the other end of the resistor R5 is used for receiving a first input voltage, the other end of the capacitor C3 is grounded, two ends of the resistor R6 are electrically connected to a collector of the transistor Q2 and the other end of the resistor R5, one end of the capacitor C4 is electrically connected to a collector of the transistor Q2, and the other end of the capacitor C4 is grounded.
In one embodiment, the level shift circuit further includes a voltage stabilizing unit, an input terminal of the voltage stabilizing unit is used for receiving an external second input voltage, and an output terminal of the voltage stabilizing unit outputs a first input voltage to the input terminal of the smoothing unit.
In one embodiment, the voltage regulation unit comprises a regulator tube Q3, an inductor L01 and a capacitor C5, an input end of the regulator tube Q3 is used for being connected with an external second input voltage, an output end of the regulator tube Q3 outputs a first input voltage through the inductor L01, one end of the capacitor C5 is electrically connected with one end of the inductor L01, which is far away from the output end of the regulator tube Q3, and the other end of the capacitor C5 is grounded.
The utility model discloses compare in prior art's advantage and beneficial effect as follows:
the utility model relates to a low-speed level conversion circuit, which is characterized in that a switch unit and a smoothing unit are arranged, so that the circuit structure of the level conversion circuit is simple, and the design and the connection of each electronic component are convenient; and can also avoid the level spike and sunken that the device characteristic of transistor itself arouses to guarantee the normal stable work of circuit, improve the stability of circuit and equipment.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a functional block diagram of a low rate level shift circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of the low rate level shifter circuit shown in FIG. 1;
fig. 3 is a functional block diagram of a low rate level shift circuit according to another embodiment of the present invention;
FIG. 4 is a circuit diagram of a transceiver unit of the low rate level shifter circuit shown in FIG. 3;
FIG. 5 is a circuit diagram of a main control connection unit of the low rate level shift circuit shown in FIG. 3;
FIG. 6 is a circuit diagram of a signal conversion unit of the low rate level shift circuit shown in FIG. 3;
fig. 7 is a circuit diagram of a voltage stabilizing unit of the low-rate level shift circuit shown in fig. 3.
Detailed Description
In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. The preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not represent the only embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The utility model discloses solve the extravagant problem in cost and the space that causes to the low speed requirement on the traditional level conversion circuit emphatically, the utility model discloses an adopt a transistor or mos pipe design circuit to go to solve 5V level and convert 3.3V level into the two-way level conversion of 5V level with 3.3V level conversion. And simultaneously, the problem of level pricks and depressions caused by the device characteristics of a single mos tube or a transistor is solved, so that the normal work of the circuit is ensured, and the high-sensitivity level-sensitive transistor is in line with certain products with extremely high requirements. The circuit simultaneously solves the requirement of master control on level conversion control, and meets the requirement of most of the users. In addition because of the cost transistor has an advantage than mos, the utility model discloses the key transistor of introducing, the utility model discloses also establish to mos.
In the present invention, referring to fig. 1, a low-rate level shift circuit includes: the switch unit 100 and the smoothing unit 200, the input end of the switch unit is used for electrically connecting an external low level input signal, the output end of the switch unit outputs a high level signal, the control end of the switch unit is electrically connected with the output end of the smoothing unit, and the input end of the smoothing unit is used for electrically connecting an external voltage signal. It should be noted that the switching unit 100 is used for converting a level signal; the smoothing unit 200 is used for controlling the on/off of the switch, so as to realize the level conversion function.
Referring to fig. 2, the switch unit includes a switch tube and a resistor R1, a control end of the switch tube is electrically connected to an output end of the smoothing unit, an input end of the switch tube is used for electrically connecting an external low-level input signal Vin, an output end of the switch tube is used as an output end of the switch unit to output a high-level signal Vout, a first end of the resistor R1 is electrically connected to the output end of the switch tube, and a second end of the resistor R1 is used for connecting an external dc voltage.
It should be noted that, in the present embodiment, the design of reducing the level shift circuit formed by combining two transistors into one transistor is intended to reduce the circuit space and cost, and perform level shift well at a low rate. In fig. 2, Vin is a signal input port, Vout is a signal output port, vdd (Vout) is a dc voltage having a level equal to that of the signal output port, and vdd (l) is a voltage having a level equal to that of a low level from a high level to a low level.
Referring to fig. 2, the smoothing unit includes a resistor R2 and a capacitor C1, a first end of the resistor R2 is electrically connected to one end of the capacitor C1 and a control end of the switching tube, a second end of the resistor R2 is used for electrically connecting an external voltage signal, and another end of the capacitor C1 is grounded.
It should be noted that the utility model provides a sunken and the problem of burr of conversion back level that often appears in the level transition. At present, no matter what kind of high-specification device is, under the influence of the characteristics of the transistor and different layout factors, the converted level is difficult to be as smooth as the input waveform, and level pits and level peaks (burrs) always appear. In the actual use scenario, if the converted level has a dip and a peak, the impact on the use scenario is very serious. If the converted level is concave, the converted level is smaller than the required level, so that the receiving party cannot judge the state of the level and cannot recognize the level, and the whole system is broken down. If the converted level spikes, meaning that the level is greater than the desired level, the system can be directly broken down or burned out. Thus, after a number of experiments it was concluded that both pits and peaks could be dealt with by adjusting the value of C1 as shown above. The value of C1 generally takes 36pF, 56pF or 100pF to compensate the concave and peak of the level, so as to avoid the whole system from being broken down.
Further, the present invention can also control the whole level system by controlling the voltage of vdd (l), in the level conversion system, if vdd (l) is low level (high and low voltages are defined according to the usage scenario), the whole level conversion system will be out of order, and when vdd (l) is high level (high and low voltages are defined according to the usage scenario), the whole level conversion system can be operated normally. And then if the control pin is accessed at VDD (L), the whole system can be effectively controlled according to the requirement of the whole system.
Therefore, the utility model discloses in the level switching circuit only set up a switch tube, thereby make the circuit structure simple, can reduce cost effectively, make the whole product structure compacter, the space that the level switching circuit took is littleer, can also make things convenient for the design and the connection of each electronic components; and through being provided with filter capacitor C1 at the control end of switch tube, can also avoid the level spine and sunken that the device characteristic of transistor itself arouses to guarantee the normal stable work of circuit, improve the stability of circuit and equipment.
The utility model discloses effectual saving level transition's cost and space have very strong practical application ability, and the unsatisfactory problem of level after the effectual solution meets the conversion in level transition moreover increases level transition's control interface, and effectual solution needs to control or the demand of time delay to level transition circuit in some special areas, makes whole level transition level have the controllability.
In this embodiment, the switch transistor is a transistor Q1, a base of the transistor Q1 is electrically connected to the output terminal of the smoothing unit, an emitter of the transistor Q1 is used to electrically connect to an external low-level input signal Vin, a collector of the transistor Q1 serves as the output terminal of the switching unit to output a high-level signal Vout, and a first end of the resistor R1 is electrically connected to an emitter of the transistor Q1. The utility model discloses a single transistor or mos pipe scheme replace traditional double transistor or mos nest of tubes combination scheme, and the transistor is introduced to this scheme focus, and the mos pipe is also suitable for equally.
The capacitor C1 has a size of 20pf to 150 pf.
Referring to fig. 3, the level shift circuit further includes a transceiver unit 300 and a main control connection unit 400, wherein an output terminal of the transceiver unit is electrically connected to an input terminal of the switch unit, and a receiving terminal of the main control connection unit is electrically connected to an output terminal of the switch unit. The transceiver unit 300 is configured to receive a signal and send the signal according to a level signal; the main control connection unit 400 is used for connecting an external motherboard.
Referring to fig. 4, the transceiver unit includes a transceiver chip U1, a resistor R3, and a capacitor C2, a power supply input terminal of the transceiver chip U1 is electrically connected to an external first input voltage, a first end of the resistor R3 is electrically connected to the first input voltage, a second end of the resistor R3 is electrically connected to an enable terminal of the transceiver chip U1, and an IO pin of the transceiver chip U1 is also electrically connected to an input terminal of the switch unit. The resistor R3 and the capacitor C2 form a filter unit, so that the input voltage is smoother and more stable; the transceiver chip U1 is used to receive signals from the motherboard and output level signals through the IO pins.
Referring to fig. 5, the main control connection unit includes a connection interface and a resistor R4, a first end of the resistor R4 is electrically connected to the output end of the switch unit, a second end of the resistor R4 is electrically connected to the connection interface, and the connection interface is further configured to be electrically connected to an external second input voltage.
Referring to fig. 3 again, the level shift circuit further includes a signal conversion unit 500, an input end of the signal conversion unit is electrically connected to the connection interface, and an output end of the signal conversion unit is electrically connected to the signal receiving pin of the transceiver unit. The signal conversion unit 500 is configured to receive a signal of the motherboard, convert the signal, and transmit the converted signal to the transceiver chip U1.
Referring to fig. 6, the signal conversion unit includes a resistor R5, a resistor R6, a capacitor C3, a capacitor C4, and a transistor Q2, an emitter of the transistor Q2 is electrically connected to the connection interface, a collector of the transistor Q2 is electrically connected to an output terminal of the switching unit, a base of the transistor Q2 is electrically connected to one end of the resistor R5 and one end of the capacitor C3, the other end of the resistor R5 is used for receiving a first input voltage, the other end of the capacitor C3 is grounded, two ends of the resistor R6 are electrically connected to a collector of the transistor Q2 and the other end of the resistor R5, one end of the capacitor C4 is electrically connected to a collector of the transistor Q2, and the other end of the capacitor C4 is grounded. Therefore, the signal conversion is more stable and reliable by arranging the resistor R5, the resistor R6, the capacitor C3, the capacitor C4 and the triode Q2.
Referring to fig. 3 again, the level shift circuit further includes a voltage stabilizing unit 600, an input terminal of the stabilized voltage is used for receiving an external second input voltage, and an output terminal of the stabilized voltage outputs a first input voltage to an input terminal of the smoothing unit. The voltage stabilizing unit 600 is configured to convert a second input voltage into a first input voltage, where the second input voltage is a 5V input voltage, and the first input voltage is a 3.3V input voltage.
Referring to fig. 7, the voltage regulator unit includes a regulator Q3, an inductor L01, and a capacitor C5, an input end of the regulator Q3 is used for accessing an external second input voltage, an output end of the regulator Q3 outputs a first input voltage through the inductor L01, one end of the capacitor C5 is electrically connected to one end of the inductor L01, which is far away from the output end of the regulator Q3, and the other end of the capacitor C5 is grounded. Therefore, the voltage regulator tube Q3 is used for realizing voltage reduction, the inductor L01 is used for realizing rectification, and the capacitor C5 is used for realizing filtering of the output voltage, so that the stability of the output voltage can be improved.
The utility model discloses compare in prior art's advantage and beneficial effect as follows:
the utility model relates to a low-speed level conversion circuit, which is characterized in that a switch unit and a smoothing unit are arranged, so that the circuit structure of the level conversion circuit is simple, and the design and the connection of each electronic component are convenient; and can also avoid the level spike and sunken that the device characteristic of transistor itself arouses to guarantee the normal stable work of circuit, improve the stability of circuit and equipment.
The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (10)
1. A low rate level shift circuit, comprising: the input end of the switch unit is used for being electrically connected with an external low-level input signal, the output end of the switch unit outputs a high-level signal, the control end of the switch unit is electrically connected with the output end of the smoothing unit, and the input end of the smoothing unit is used for being electrically connected with an external voltage signal;
the switch unit comprises a switch tube and a resistor R1, wherein the control end of the switch tube is electrically connected with the output end of the smoothing unit, the input end of the switch tube is used for electrically connecting an external low-level input signal Vin, the output end of the switch tube is used as the output end of the switch unit to output a high-level signal Vout, the first end of the resistor R1 is electrically connected with the output end of the switch tube, and the second end of the resistor R1 is used for connecting an external direct-current voltage;
the smoothing unit comprises a resistor R2 and a capacitor C1, a first end of the resistor R2 is electrically connected with one end of the capacitor C1 and a control end of the switch tube respectively, a second end of the resistor R2 is used for being electrically connected with an external voltage signal, and the other end of the capacitor C1 is grounded.
2. The low-rate level shifter circuit as claimed in claim 1, wherein the switch transistor is a transistor Q1, a base of the transistor Q1 is electrically connected to the output terminal of the smoothing unit, an emitter of the transistor Q1 is used for electrically connecting to an external low-level input signal Vin, a collector of the transistor Q1 is used as the output terminal of the switching unit to output the high-level signal Vout, and a first terminal of the resistor R1 is electrically connected to the emitter of the transistor Q1.
3. The low-rate level shifter circuit as claimed in claim 1, wherein the capacitor C1 is 20pf 150pf in size.
4. The low-rate level shifter circuit according to claim 1, further comprising a transceiver unit and a main control connection unit, wherein an output terminal of the transceiver unit is electrically connected to an input terminal of the switch unit, and a receiving terminal of the main control connection unit is electrically connected to an output terminal of the switch unit.
5. The low-rate level shifter circuit as claimed in claim 4, wherein the transceiver unit comprises a transceiver chip U1, a resistor R3 and a capacitor C2, a power supply input terminal of the transceiver chip U1 is electrically connected to an external first input voltage, a first terminal of the resistor R3 is electrically connected to the first input voltage, a second terminal of the resistor R3 is electrically connected to an enable terminal of the transceiver chip U1, and an IO pin of the transceiver chip U1 is also electrically connected to the input terminal of the switch unit.
6. The low-rate level shifter circuit as claimed in claim 4, wherein the master connection unit comprises a connection interface and a resistor R4, a first terminal of the resistor R4 is electrically connected to the output terminal of the switch unit, a second terminal of the resistor R4 is electrically connected to the connection interface, and the connection interface is further used for electrically connecting to an external second input voltage.
7. The low-rate level shift circuit according to claim 6, further comprising a signal conversion unit, wherein an input terminal of the signal conversion unit is electrically connected to the connection interface, and an output terminal of the signal conversion unit is electrically connected to the signal receiving pin of the transceiver unit.
8. The low-rate level shifter circuit according to claim 7, wherein the signal conversion unit includes a resistor R5, a resistor R6, a capacitor C3, a capacitor C4, and a transistor Q2, an emitter of the transistor Q2 is electrically connected to the connection interface, a collector of the transistor Q2 is electrically connected to the output terminal of the switching unit, a base of the transistor Q2 is electrically connected to one end of the resistor R5 and one end of the capacitor C3, the other end of the resistor R5 is used for receiving a first input voltage, the other end of the capacitor C3 is grounded, two ends of the resistor R6 are electrically connected to a collector of the transistor Q2 and the other end of the resistor R5, one end of the capacitor C4 is electrically connected to a collector of the transistor Q2, and the other end of the capacitor C4 is grounded.
9. The low-rate level shift circuit according to claim 1, further comprising a voltage-stabilizing unit, wherein an input terminal of the voltage-stabilizing unit is connected to an external second input voltage, and an output terminal of the voltage-stabilizing unit outputs the first input voltage to the input terminal of the smoothing unit.
10. The low-rate level shift circuit according to claim 9, wherein the voltage regulator unit includes a regulator Q3, an inductor L01, and a capacitor C5, an input terminal of the regulator Q3 is used for receiving an external second input voltage, an output terminal of the regulator Q3 outputs a first input voltage through the inductor L01, one end of the capacitor C5 is electrically connected to one end of the inductor L01, which is far away from the output terminal of the regulator Q3, and the other end of the capacitor C5 is grounded.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921353350.0U CN210518267U (en) | 2019-08-20 | 2019-08-20 | Low-rate level conversion circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921353350.0U CN210518267U (en) | 2019-08-20 | 2019-08-20 | Low-rate level conversion circuit |
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| CN210518267U true CN210518267U (en) | 2020-05-12 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024021538A1 (en) * | 2022-07-29 | 2024-02-01 | 普源精电科技股份有限公司 | High-low level conversion circuit |
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2019
- 2019-08-20 CN CN201921353350.0U patent/CN210518267U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024021538A1 (en) * | 2022-07-29 | 2024-02-01 | 普源精电科技股份有限公司 | High-low level conversion circuit |
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Granted publication date: 20200512 |