CN217238692U - LCD driving circuit - Google Patents
LCD driving circuit Download PDFInfo
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- CN217238692U CN217238692U CN202221163455.1U CN202221163455U CN217238692U CN 217238692 U CN217238692 U CN 217238692U CN 202221163455 U CN202221163455 U CN 202221163455U CN 217238692 U CN217238692 U CN 217238692U
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Abstract
The utility model relates to the technical field of LCD drive, and discloses an LCD drive circuit, which comprises a band gap reference circuit, a first control switch, an energy storage unit, a comparison unit, an oscillator circuit, a charge pump circuit, a second control switch and a voltage division circuit; band gap reference circuit's reference voltage output is connected with first control switch's input electricity, and first control switch's output is connected with the negative input end of comparing element and energy storage unit electricity respectively, and the comparing element's output is connected with oscillator circuit's the enable end and the enable end electricity of charge pump circuit respectively, when the in-service use the utility model discloses a let energy storage unit cycle charge and discharge and let first control switch cycle switch on and turn-off can let band gap reference circuit cycle output band gap reference voltage, need not let band gap reference circuit output band gap reference voltage always, and then reduce LCD drive circuit's use consumption.
Description
Technical Field
The utility model relates to a LCD drive technical field, concretely relates to LCD drive circuit.
Background
In electronic products, a liquid crystal display or an LCD display is commonly used for information display and man-machine interaction, and becomes an indispensable component of most electronic products. Currently, the existing LCD driving circuit usually uses a charge pump circuit to provide a reference voltage, and then controls the charge pump to operate based on the comparison result between the reference voltage and the detection point voltage, so that the charge pump generates a driving voltage for driving the LCD display. When the existing LCD driving circuit is actually used, the band-gap reference circuit is enabled all the time, namely, a stable band-gap reference voltage is output all the time and is supplied to other circuit modules, so that the power consumption is high.
SUMMERY OF THE UTILITY MODEL
In view of the deficiency of the background art, the utility model provides a LCD drive circuit, the technical problem that solve is that current LCD drive circuit is when in-service use, because the charge pump circuit enables work always, the consumption is higher.
For solving the technical problem, the utility model provides a following technical scheme: the LCD driving circuit comprises a band gap reference circuit, a first control switch, an energy storage unit, a comparison unit, an oscillator circuit, a charge pump circuit, a second control switch and a voltage division circuit; the reference voltage output end of the band-gap reference circuit is electrically connected with the input end of the first control switch, the output end of the first control switch is electrically connected with the negative input end of the comparison unit and the energy storage unit respectively, and the output end of the comparison unit is electrically connected with the enable end of the oscillator circuit and the enable end of the charge pump circuit respectively; the clock signal output end of the oscillator circuit is electrically connected with the charge pump circuit; the voltage output end of the charge pump circuit is electrically connected with the voltage dividing circuit, the voltage dividing circuit comprises a first voltage dividing node, a second voltage dividing node and a feedback voltage node, and the feedback voltage node is electrically connected with the positive input end of the comparison unit.
In one embodiment, the first voltage dividing node is electrically connected with a first output buffer module, and the second voltage dividing node is electrically connected with a second output buffer module.
In one embodiment, the system further comprises a logic control unit and a second control switch; the clock signal output end of the oscillator circuit is electrically connected with the logic control unit; the voltage output end of the charge pump circuit is electrically connected with the input end of the second control switch, the output end of the second control switch is electrically connected with the voltage dividing circuit, and the logic control unit inputs control signals to the control end of the second control switch, the oscillator circuit and the enabling end of the comparison unit respectively;
the first voltage division node is electrically connected with the input end of a third control switch, the output end of the third control switch is respectively electrically connected with the second energy storage unit and the first output buffer module, and the output end of the first output buffer module is electrically connected with a third energy storage unit;
the second voltage division node is electrically connected with the input end of a fourth control switch, the output end of the fourth control switch is respectively electrically connected with a fourth energy storage unit and a second output buffer module, and the output end of the second output buffer module is electrically connected with a fifth energy storage unit;
and the logic control unit respectively inputs a second control signal to the control end of the third control switch and the control end of the fourth control switch, and the second control signal is configured to control the on-off of the third control switch and the fourth control switch.
In one embodiment, the first control switch, the third control switch and the fourth control switch are transmission gates.
In a certain embodiment, the energy storage unit, the second energy storage unit, the third energy storage unit, the fourth energy storage unit and the fifth energy storage unit are all capacitors.
In one embodiment, the voltage divider circuit includes a plurality of resistors connected in series, the voltage of the first voltage divider node is one third of the output voltage of the charge pump circuit, and the voltage of the second voltage divider node is two thirds of the output voltage of the charge pump circuit.
In one embodiment, the feedback voltage nodes are electrically connected to input terminals of a plurality of switches, respectively, an output terminal of one switch is electrically connected to an electrical node of the voltage divider circuit, the electrical node to which the output terminal of each switch is electrically connected is different, and the electrical node is one end to which two resistors are connected.
Compared with the prior art, the utility model the beneficial effect who has is: the utility model discloses owing to set gradually first control switch and energy storage unit through the voltage output end at band gap reference circuit, the charge-discharge of energy storage unit is realized to break-make through controlling first control switch, then provide comparative voltage to comparative unit's negative input end by the energy storage unit, consequently can let band gap reference circuit cycle output band gap reference voltage through letting energy storage unit cycle charge-discharge and letting first control switch cycle switch on and turn-off when in-service use, need not let band gap reference circuit output band gap reference voltage always, and then reduce LCD drive circuit's use consumption.
Drawings
Fig. 1 is a schematic structural diagram of the present invention in an embodiment;
fig. 2 is a second schematic structural diagram of the present invention in an embodiment;
fig. 3 is a second schematic structural diagram of the present invention in an embodiment;
FIG. 4 is a waveform diagram of the clock signal CK, the clock signal CLK32, the control signal EN1 and the control signal EN2 in the embodiment;
fig. 5 is a waveform diagram of the clock signal CK, the clock signal CLK32, the control signal EN1, and the control signal EN2 at a certain period in the embodiment.
Detailed Description
The present invention will now be described in further detail with reference to the accompanying drawings. The drawings are simplified schematic drawings, which illustrate the basic structure of the present invention in a schematic manner, and thus show only the components related to the present invention.
As shown in fig. 1, the LCD driving circuit includes a bandgap reference circuit 1, a first control switch 2, an energy storage unit 3, a comparison unit 4, an oscillator circuit 5, a charge pump circuit 6 and a voltage divider circuit 9;
the bandgap reference circuit 1 in this embodiment includes a bandgap output enable terminal BGP _ EN, and when the bandgap output enable terminal BGP _ EN inputs an enable signal of a high level, the bandgap reference circuit 1 starts to output a bandgap reference voltage;
the reference voltage output end of the band gap reference circuit 1 is electrically connected with the input end of the first control switch 2, and the output end of the first control switch 2 is respectively electrically connected with the negative input end of the comparison unit 4 and the energy storage unit 3; in practical use, the energy storage unit 3 provides reference voltage for the negative input end of the comparison unit 4, the band-gap reference circuit 1 is not required to output band-gap reference voltage all the time, the band-gap reference circuit 1 can periodically output band-gap reference voltage to periodically charge and discharge the energy storage unit 3, and power consumption can be further reduced;
the output end of the comparison unit 4 is electrically connected with the enable end of the oscillator circuit 5 and the enable end of the charge pump circuit 6 respectively; in actual use, the output signal of the comparison unit 3 is used for enabling the oscillator circuit 5 and the charge pump circuit 6, and when the enable signal output by the comparison unit 3 is a low level signal, the oscillator circuit 5 and the charge pump circuit 6 start to work; when the enable signal output from the comparing unit 3 is a high level signal, the enable signal does not enable the oscillator circuit 5 and the charge pump circuit 6 to operate;
the clock signal output end of the oscillator circuit 5 is electrically connected with the charge pump circuit 6; in actual use, when the oscillator circuit 5 starts operating to supply the clock signal CK to the charge pump circuit, the charge pump circuit 6 starts operating to output the voltage VLCD whose amplitude gradually rises from the start of generation and finally stabilizes.
The voltage output end of the charge pump circuit 6 is electrically connected with the voltage dividing circuit 9, the voltage dividing circuit 9 comprises a first voltage dividing node, a second voltage dividing node and a feedback voltage node, the voltage output by the first voltage dividing node is 1/3 voltage VLCD, and the voltage output by the second voltage dividing node is 2/3 voltage VLCD; in actual use, the voltage input ends of the first voltage division node and the second voltage division node are driven by the LCD; the feedback voltage node is electrically connected to the positive input terminal of the comparison unit 4, and feeds back a voltage Vb to the positive input terminal of the comparison unit 4, where the feedback voltage Vb is positively correlated with the output voltage of the charge pump circuit 6.
Specifically, the voltage dividing circuit 9 includes a plurality of resistors connected in series in sequence. The series resistance values are set so that the voltage output by the first voltage division node is 1/3VLCD, and the voltage output by the second voltage division node is 2/3 VLCD.
In addition, in practical use, the magnitude of the voltage VLCD can be adjusted by adjusting the operating time of the charge pump circuit 6, and the operating time of the charge pump circuit 6 is related to the magnitude of the feedback voltage Vb, in order to adjust the magnitude of the feedback voltage Vb, in this embodiment, the feedback voltage nodes are respectively electrically connected to the input ends of a plurality of switches, the output end of one switch is electrically connected to one electrical node of the voltage dividing circuit, the electrical node to which the output end of each switch is electrically connected is different, and the electrical node is one end to which two resistors are connected. In practical use, the magnitude of the feedback voltage Vb can be adjusted by closing different switches, and it should be noted that only one switch can be turned on and off at the same time.
In actual use, the circuit in fig. 1 does not need to make the bandgap reference circuit 1 output the bandgap reference voltage all the time, thereby reducing power consumption.
In actual use, in order to ensure that the voltage provided by the first voltage division node and the second voltage division node to the LCD display is stable, as shown in fig. 2, the first voltage division node is electrically connected to the first output buffer module 12, and the second voltage division node is electrically connected to the second output buffer module 16. Wherein the first output buffer module 12 and the second output buffer module 16 may employ voltage followers.
In addition, in the LCD driving circuit in fig. 2, when the oscillator circuit 5 supplies the clock signal CK to the charge pump circuit 6 during actual use, the charge pump circuit 6 also always inputs the voltage VLCD to the voltage dividing circuit 9, and there is a problem that power consumption is excessive, based on which, as shown in fig. 3, the LCD driving circuit in fig. 3 further includes a logic control unit 7 and a second control switch 8; the clock signal output end of the oscillator circuit 5 is electrically connected with the logic control unit 7, and the logic control unit 7 also inputs a clock signal CLK 32; the voltage output end of the charge pump circuit 6 is electrically connected with the input end of a second control switch 8, the output end of the second control switch 8 is electrically connected with a voltage dividing circuit 9, the logic control unit 7 inputs control signals to the control end of the second control switch 8, the oscillator circuit 5 and the enabling end of the comparison unit 4 respectively based on a clock signal CLK32 and the clock signal output by the oscillator circuit 5, the control signals are used for controlling the on and off of the second control switch and controlling the enabling of the oscillator circuit 5, when the control signals enable the oscillator circuit 5, the second control switch 8 is on, and the comparison unit 4 outputs a comparison result based on the feedback voltage Vref and the voltage of the energy storage unit 3; when the control signal does not enable the oscillator circuit 5, the second control switch 8 is turned off, the comparison unit 4 outputs a high level signal, and the oscillator circuit 5 and the charge pump circuit do not work;
the first voltage division node is electrically connected with the input end of a third control switch 10, the output end of the third control switch 10 is respectively electrically connected with a second energy storage unit 11 and a first output buffer module 12, and the output end of the first output buffer module 12 is electrically connected with a third energy storage unit 13;
the second voltage division node is electrically connected with the input end of a fourth control switch 14, the output end of the fourth control switch 14 is electrically connected with a fourth energy storage unit 15 and a second output buffer module 16 respectively, and the output end of the second output buffer module 16 is electrically connected with a fifth energy storage unit 17;
the logic control unit 7 inputs a second control signal EN2 to the control end of the third control switch 10 and the control end of the fourth control switch 11, respectively, and the second control signal EN2 is configured to control on/off of the third control switch 10 and the fourth control switch 11; wherein the third control switch 10 and the fourth control switch 11 are turned on and off simultaneously.
In the present embodiment, the first control switch 2, the third control switch 10 and the fourth control switch 14 are all transmission gates. The energy storage unit 3, the second energy storage unit 11, the third energy storage unit 13, the fourth energy storage unit 15 and the fifth energy storage unit 17 are all capacitors.
The operation flow of the LCD driving circuit in fig. 3 is as follows: when the circuit is started, a period enabling signal is input to the control end of the first control switch 2, a clock signal CLK32 is input to the logic control unit 7, the period enabling signal controls the capacitor C0 to be charged and discharged periodically, the capacitor C0 provides a reference voltage Vref to the negative input end of the comparison unit 4, the comparison unit 4 outputs a low-level signal because a feedback voltage Vb input to the positive input end of the comparison unit 4 is smaller than the reference voltage Vref, the oscillator circuit 5 and the charge pump circuit 6 are enabled to work by the low-level signal, and the oscillator circuit 5 provides a clock signal CK to the logic control unit 7 and the charge pump circuit respectively;
the logic control unit 7 outputs the high and low level states of the control signal EN1 and the control signal EN2 based on the clock signal CK and the clock signal CLK32, specifically, at power-up, the logic control unit 7 makes the control signal EN1 be at a high level at the rising edge of the clock signal CLK32, after the control signal EN1 is at a high level, the logic control unit 7 makes the second control signal EN2 be at a high level, the logic control unit 7 counts the clock signal CK after receiving the clock signal CK, makes the control signal EN1 be at a low level state when the count value reaches a target value, and makes the second control signal EN2 be at a low level state when making the control signal EN1 be at a low level state, and when the rising edge of the next clock signal CLK32 comes again, the logic control unit 7 adjusts the high and low level states of the control signal EN1 and the second control signal EN2 according to the above principle;
when the control signal EN1 is at a high level, the second control switch 8 is turned on to operate, when the control signal EN2 is at a high level, the third control switch 10 and the fourth control switch 14 are turned on to operate, waveforms of the clock signal CK, the clock signal CLK32, the control signal EN1 and the second control signal EN2 are shown in fig. 4 and 5, as can be obtained from fig. 4, when the control signal EN1 and the second control signal EN2 are both at a high level, the charge pump circuit 6 charges the capacitor C1 and the capacitor C2, when the control signal EN1 and the second control signal EN2 are both at a low level, the charge pump circuit 6 does not charge the capacitor C1 and the capacitor C2, the capacitor C1 and the capacitor C2 respectively charge and discharge the capacitor C4642 and the capacitor C4 through the first buffer module 12 and the second buffer module 16, the capacitor C3 and the capacitor C4 respectively output VLCD voltage and 2/3VLCD voltage, and because the control signal EN1 is at a low level, the comparison unit 4 outputs a high level signal; therefore, the capacitor C1 and the capacitor C2 can be charged and discharged periodically by periodically generating the control signal EN1 and the second control signal EN2, so that the working time of the charge pump circuit 6 is reduced, and the power consumption is reduced; in addition, the first enable signal PUMP _ OUT _ EN is periodically input to the first buffer module 12 and the second buffer module 16, so that the first buffer module 12 and the second buffer module 16 can periodically work, the capacitor C3 and the capacitor C4 can be periodically charged and discharged, the 1/3VLCD voltage and the 2/3VLCD voltage can be kept stable, meanwhile, the working time of the first buffer module 12 and the second buffer module 16 can be reduced, and the power consumption can be reduced.
In light of the above, the present invention is not limited to the above embodiments, and various changes and modifications can be made by the worker without departing from the scope of the present invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims (7)
- The LCD driving circuit is characterized by comprising a band gap reference circuit, a first control switch, an energy storage unit, a comparison unit, an oscillator circuit, a charge pump circuit, a second control switch and a voltage division circuit; the reference voltage output end of the band-gap reference circuit is electrically connected with the input end of the first control switch, the output end of the first control switch is electrically connected with the negative input end of the comparison unit and the energy storage unit respectively, and the output end of the comparison unit is electrically connected with the enable end of the oscillator circuit and the enable end of the charge pump circuit respectively; the clock signal output end of the oscillator circuit is electrically connected with the charge pump circuit; the voltage output end of the charge pump circuit is electrically connected with the voltage dividing circuit, the voltage dividing circuit comprises a first voltage dividing node, a second voltage dividing node and a feedback voltage node, and the feedback voltage node is electrically connected with the positive input end of the comparison unit.
- 2. The LCD driver circuit of claim 1, wherein the first voltage division node is electrically connected to a first output buffer module, and the second voltage division node is electrically connected to a second output buffer module.
- 3. The LCD driver circuit according to claim 2, further comprising a logic control unit and a second control switch; the clock signal output end of the oscillator circuit is electrically connected with the logic control unit; the voltage output end of the charge pump circuit is electrically connected with the input end of the second control switch, the output end of the second control switch is electrically connected with the voltage dividing circuit, and the logic control unit inputs control signals to the control end of the second control switch, the oscillator circuit and the enabling end of the comparison unit respectively;the first voltage division node is electrically connected with the input end of a third control switch, the output end of the third control switch is respectively electrically connected with the second energy storage unit and the first output buffer module, and the output end of the first output buffer module is electrically connected with a third energy storage unit;the second voltage division node is electrically connected with the input end of a fourth control switch, the output end of the fourth control switch is respectively electrically connected with a fourth energy storage unit and a second output buffer module, and the output end of the second output buffer module is electrically connected with a fifth energy storage unit;and the logic control unit respectively inputs a second control signal to the control end of the third control switch and the control end of the fourth control switch, and the second control signal is configured to control the on-off of the third control switch and the fourth control switch.
- 4. The LCD driving circuit of claim 3, wherein the first control switch, the third control switch, and the fourth control switch are transmission gates.
- 5. The LCD driving circuit according to claim 3, wherein the energy storage unit, the second energy storage unit, the third energy storage unit, the fourth energy storage unit and the fifth energy storage unit are all capacitors.
- 6. The LCD driver circuit of claim 1, wherein the voltage divider circuit comprises a plurality of resistors connected in series, the first voltage divider node has a voltage one-third of the output voltage of the charge pump circuit, and the second voltage divider node has a voltage two-thirds of the output voltage of the charge pump circuit.
- 7. The LCD driving circuit according to claim 6, wherein the feedback voltage nodes are electrically connected to input terminals of a plurality of switches, respectively, an output terminal of one switch is electrically connected to an electrical node of the voltage dividing circuit, the electrical node to which the output terminal of each switch is electrically connected is different, and the electrical node is one terminal to which two resistors are connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221163455.1U CN217238692U (en) | 2022-05-13 | 2022-05-13 | LCD driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221163455.1U CN217238692U (en) | 2022-05-13 | 2022-05-13 | LCD driving circuit |
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| CN217238692U true CN217238692U (en) | 2022-08-19 |
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| CN202221163455.1U Active CN217238692U (en) | 2022-05-13 | 2022-05-13 | LCD driving circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116009638A (en) * | 2023-02-22 | 2023-04-25 | 禹创半导体(深圳)有限公司 | Reference voltage generation circuit, control method and device thereof and medium |
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2022
- 2022-05-13 CN CN202221163455.1U patent/CN217238692U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116009638A (en) * | 2023-02-22 | 2023-04-25 | 禹创半导体(深圳)有限公司 | Reference voltage generation circuit, control method and device thereof and medium |
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