CN102938610A - Charge pump circuit and storage - Google Patents

Charge pump circuit and storage Download PDF

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Publication number
CN102938610A
CN102938610A CN2012104727590A CN201210472759A CN102938610A CN 102938610 A CN102938610 A CN 102938610A CN 2012104727590 A CN2012104727590 A CN 2012104727590A CN 201210472759 A CN201210472759 A CN 201210472759A CN 102938610 A CN102938610 A CN 102938610A
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China
Prior art keywords
voltage
charge pump
pump circuit
unit
reference voltage
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杨光军
胡剑
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

Provided are a charge pump circuit and a storage. The charge pump circuit comprises a clock driving unit, a boosting unit, a voltage adjustment unit, a voltage dividing unit, a first comparison unit, a second comparison unit and a state control unit. The voltage dividing unit outputs first divided voltage and second divided voltage. The first comparison unit is used for comparing the first divided voltage and first reference voltage and outputting a first comparison result. The second comparison unit is used for comparing the second divided voltage and second reference voltage and outputting a second comparison result. The state control unit is used for outputting control level to the clock driving unit according to the first comparison result and the second comparison result and controlling the clock driving unit to output driving voltage. According to the technical scheme, power loss of the clock driving unit is reduced by reducing awaking times of the clock driving unit.

Description

Charge pump circuit and memory
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of charge pump circuit and memory.
Background technology
Along with the development of semiconductor technology, based on low-power consumption, cheaply designing requirement, the supply voltage of memory is usually lower, such as 2.5V, 1.8V etc.Yet, in order to realize the read-write of the information of storing, usually need to be far above program voltage and the erasing voltage of supply voltage, such as 8V, 11V etc.Therefore, charge pump circuit is widely used in the memory, is used for obtaining higher program voltage and erasing voltage by lower supply voltage.
With reference to figure 1, show the structure chart of existing a kind of charge pump circuit.As shown in Figure 1, existing charge pump circuit comprises: clock driver element 11, boosting unit 12, voltage-adjusting unit 13, partial pressure unit 14 and voltage comparison unit 15.Its operation principle is: after charge pump circuit starts, and boosting unit 12 output booster voltages; 13 pairs of described booster voltages of voltage-adjusting unit carry out shaping and dividing potential drop, and the burning voltage of read-write operation is carried out in output for memory; 14 pairs of described booster voltages of partial pressure unit carry out dividing potential drop, and the output branch pressure voltage is to voltage comparison unit 15; 15 pairs of described branch pressure voltages of voltage comparison unit and a reference voltage that sets in advance compare, and the output control level is to clock driver element 11; Clock driver element 11 is controlled the boost action of boosting unit 12 according to described control level outputting drive voltage.
Particularly, if the branch pressure voltage of partial pressure unit 14 outputs is less than reference voltage, then to make the driving voltage of clock driver element 11 outputs be the rectilinear oscillation signal to the control level of voltage comparison unit 15 output, and described rectilinear oscillation signal makes boosting unit 12 continue to boost; If the branch pressure voltage of partial pressure unit 14 output is greater than reference voltage, then to make the driving voltage of clock driver element 11 outputs be invalid driving signal to the control level of voltage comparison unit 15 outputs, and described invalid driving signal makes boosting unit 12 stop to boost.
Fig. 2 is the booster voltage oscillogram of boosting unit 12 outputs in the charge pump circuit shown in Figure 1, and transverse axis represents time t, and the longitudinal axis represents described booster voltage.After supposing that charge pump circuit starts, the booster voltage of boosting unit 12 outputs is at t 0Constantly reach target voltage V Set, target voltage V SetExpression can drive the voltage of charge pump circuit loaded work piece.Surpass target voltage V at booster voltage SetAfter, clock driver element 11 is answered the failure of oscillations, exports invalid driving signal.Because path delay, clock driver element 11 outputs still can be kept the rectilinear oscillation signal of a period of time, and booster voltage can continue to rise to maximum V MaxAfter 11 failures of oscillations of clock driver element, boosting unit 12 no longer continues to boost, and booster voltage can progressively reduce along with the load consumed current of charge pump circuit.When booster voltage is reduced to target voltage V SetThe time, voltage comparison unit 15 will be exported control level again, because path delay, must be after after a while, described control level could be waken clock driver element 11 up (wake up), and the driving voltage that clock driver element 11 is produced is the rectilinear oscillation signal by invalid driving signal transition.Therefore, booster voltage is owing to the load consumed current of charge pump circuit continues to be reduced to minimum value V MinAfterwards, clock driver element 11 restarts vibration and output rectilinear oscillation signal, re-starts boost action with control boosting unit 12.To t 1Constantly, through a work period, booster voltage reaches target voltage V again Set, charge pump circuit repeats the above-mentioned course of work.
According to the operation principle of charge pump circuit, the power loss of charge pump circuit within each work period is broadly divided into two parts: the power loss C*(V when being the capacitor charging of giving in the process of boosting in the boosting unit 12 Max-V Min), C represents the appearance value of charging capacitor, (V Max-V Min) the expression charging voltage; Another is the power loss of clock driver element 11 when at every turn being waken up.Can find out that in the course of work of charge pump circuit shown in Figure 1, clock driver element 11 can be waken up once in each work period.In this process, the many devices in the clock driver element 11 need to reopen, and therefore can cause more power loss.
More about the technical scheme that reduces the charge pump circuit power consumption can application reference number be 03156438.0, denomination of invention is the Chinese patent application file of high precision low power dissipation charge pump circuit.
Summary of the invention
The problem that the present invention solves provides a kind of charge pump circuit, reduces the power loss of charge pump circuit.
For addressing the above problem, the invention provides a kind of charge pump circuit, described charge pump circuit comprises: the clock driver element is used for outputting drive voltage; Boosting unit, according to the driving voltage booster tension of described clock driver element output, the output booster voltage; Voltage-adjusting unit, the booster voltage that described boosting unit is exported carries out shaping and dividing potential drop, stable output voltage; Described charge pump circuit also comprises: partial pressure unit, be used for described booster voltage is carried out dividing potential drop, and export the first branch pressure voltage and the second branch pressure voltage; The first comparing unit is used for described the first branch pressure voltage and the first reference voltage are compared, and exports the first comparative result; The second comparing unit is used for described the second branch pressure voltage and the second reference voltage are compared, and exports the second comparative result; Status unit is used for exporting control level to described clock driver element according to described the first comparative result and described the second comparative result, controls described clock driver element and exports described driving voltage.
Optionally, described the first reference voltage and described the second reference voltage determine that according to lower limit and the higher limit of described booster voltage described lower limit is less than described higher limit and differ predetermined value respectively.
Optionally, the span of described predetermined value is 0.2V to 1.6V.
Optionally, described the first reference voltage and described the second reference voltage are provided by band gap reference.
Optionally, described the first branch pressure voltage and described the second branch pressure voltage equate that described the first reference voltage is less than described the second reference voltage.
Optionally, described the first branch pressure voltage is less than described the second branch pressure voltage, and described the first reference voltage is less than described the second reference voltage.
Optionally, described the first comparing unit comprises the first comparator, and its anode is inputted described the first reference voltage, and negative terminal is inputted described the first branch pressure voltage.
Optionally, described the second comparing unit comprises the second comparator, and its anode is inputted described the second branch pressure voltage, and negative terminal is inputted described the second reference voltage.
Optionally, described status unit is trigger.
Optionally, described trigger is rest-set flip-flop, and its set end is inputted described the first comparative result, and reset terminal is inputted described the second comparative result, and output is exported described control level.
For addressing the above problem, the present invention also provides a kind of memory, and described memory comprises above-mentioned charge pump circuit.
Compared with prior art, the present invention has following beneficial effect: after the booster voltage of exporting in the charge pump circuit surpasses the lower limit of setting, described clock driver element does not have the failure of oscillations, but continue output rectilinear oscillation signal, controlling described boosting unit boosts again, until after described booster voltage reaches the higher limit of setting, just make the failure of oscillations of described clock driver element by comparing unit and status unit, control described boosting unit and stop to boost.Because the charge and discharge process of electric capacity is elongated in the described boosting unit, so the work period of whole charge pump circuit is elongated, and the number of times that described clock driver element is waken up reduces, and has reduced power loss.
Description of drawings
Fig. 1 is the structural representation of existing a kind of charge pump circuit;
Fig. 2 is the booster voltage waveform schematic diagram of exporting in the existing charge pump circuit;
Fig. 3 is the structural representation of embodiment of the present invention charge pump circuit;
Fig. 4 is the structural representation of the embodiment of the invention 1 charge pump circuit;
Fig. 5 is the booster voltage waveform schematic diagram of exporting in the embodiment of the invention 1 charge pump circuit;
Fig. 6 is the structural representation of the embodiment of the invention 2 charge pump circuits.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with drawings and Examples the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
Just as described in the background art, the power loss of charge pump circuit within each work period is broadly divided into two parts, power loss when being the capacitor charging of giving in the process of boosting in the boosting unit, another is the power loss of clock driver element when at every turn being waken up.The inventor of the technical program considers that the number of times that is waken up by minimizing clock driver element reduces the power power consumption.
Shown in Figure 3 is the structure chart of embodiment of the present invention charge pump circuit.With reference to figure 3, described charge pump circuit comprises: clock driver element 21 is used for outputting drive voltage; Boosting unit 22, according to the driving voltage booster tension of described clock driver element 21 outputs, the output booster voltage; Voltage-adjusting unit 23, the booster voltage that described boosting unit 22 is exported carries out shaping and dividing potential drop, stable output voltage; Also comprise:
Partial pressure unit 24 is used for described booster voltage is carried out dividing potential drop, exports the first branch pressure voltage and the second branch pressure voltage;
The first comparing unit 25 is used for described the first branch pressure voltage and the first reference voltage are compared, and exports the first comparative result;
The second comparing unit 26 is used for described the second branch pressure voltage and the second reference voltage are compared, and exports the second comparative result;
Status unit 27 is used for exporting control level to described clock driver element 21 according to described the first comparative result and described the second comparative result, controls the described driving voltage of described clock driver element 21 outputs.
Be described in detail below in conjunction with the execution mode of specific embodiment to charge pump circuit provided by the invention.In the technical program, the implementation of described clock driver element 21, boosting unit 22, voltage-adjusting unit 23 is same as the prior art, for avoiding giving unnecessary details, only does simple declaration in following embodiment.
Embodiment 1
Fig. 4 is the structure chart of the embodiment of the invention 1 charge pump circuit.With reference to figure 4, voltage-adjusting unit 23 comprises adjusts transistor MP0, and the booster voltage HV of source electrode input boosting unit 22 outputs of described adjustment transistor MP0 connects by divider resistance R between the grid source electrode, drain electrode stable output voltage V EPReference current source I is connected an end and is connected the grid of described adjustment transistor MP0 with filter capacitor C, the other end is connected to ground.
Partial pressure unit 24 comprises the PMOS pipe of a plurality of source electrodes and the connection that is connected, successively series connection.The grid of each PMOS pipe and drain electrode short circuit, substrate is connected with source electrode.The quantity of the PMOS pipe of described series connection is according to the target voltage V of described booster voltage HV SetDetermine described target voltage V with the threshold voltage of the single PMOS pipe of described series connection SetExpression can drive the voltage of charge pump circuit loaded work piece.Particularly, the quantity of the PMOS pipe of described series connection is described target voltage V SetRatio with the threshold voltage of the single PMOS pipe of described series connection.In this enforcement, described target voltage V SetBe 8V, the threshold voltage of the single PMOS pipe of described series connection is 0.8V, and then described partial pressure unit 24 comprises the PMOS pipe of 10 series connection: MP1, MP2 ..., MP10.Need to prove that in the present embodiment, described partial pressure unit 24 has adopted transistor as partial pressure device, in other embodiments, also can adopt other device (such as resistance, electric capacity etc.) to realize dividing potential drop.
Continuation is with reference to figure 4, and in the present embodiment, the first branch pressure voltage and second branch pressure voltage of described partial pressure unit 24 outputs are same voltage V D, by source electrode (that is drain electrode of the PMOS pipe MP2) output of PMOS pipe MP1.The first comparing unit 25 comprises the first comparator A1, and the anode of described the first comparator A1 is inputted the first reference voltage V REF1, negative terminal is inputted described the first branch pressure voltage V D, output is exported the first comparative result FB1.The second comparing unit 26 comprises the second comparator A2, and the anode of described the second comparator A2 is inputted described the second branch pressure voltage V D, negative terminal is inputted the second reference voltage V REF2, output is exported the second comparative result FB2.Described the first reference voltage V REF1With described the second reference voltage V REF2Can be provided by band gap reference, concrete value is determined according to lower limit V1 and the higher limit V2 of described booster voltage HV respectively.Described the first comparator A1 and described the second comparator A2 compare the voltage signal of its positive and negative terminal input respectively, the output comparative result.Particularly, take described the first comparator A1 as example, if the described first branch pressure voltage V of described the first comparator A1 negative terminal input DDescribed the first reference voltage V less than its anode input REF1, then the described first comparative result FB1 of described the first comparator A1 output is high level, i.e. logical one; Otherwise then output low level, i.e. logical zero.The operation principle of described the second comparator A2 is identical, does not repeat them here.
In the present embodiment, status unit 27 is rest-set flip-flop A3.The set end S of described rest-set flip-flop A3 inputs described the first comparative result FB1, and reset terminal R inputs described the second comparative result FB2, and output Q output control level FB give described clock driver element 21, controls described clock driver element 21 outputting drive voltage V DRVThose skilled in the art know, and described status unit 27 can also other circuit form, all can replace described rest-set flip-flop A3, realization state control function such as the state controller that uses JK flip-flop, a plurality of d type flip flop to form etc.
Fig. 5 is the booster voltage HV oscillogram of described boosting unit 22 outputs of the embodiment of the invention 1 charge pump circuit, and transverse axis represents time t, and the longitudinal axis represents described booster voltage HV.For better embodiments of the invention 1 being understood, describe below in conjunction with the operation principle of accompanying drawing to the technical solution of the present invention charge pump circuit.
With reference to figure 5, Vmin shown in the figure and Vmax are respectively minimum value and the maximum of described booster voltage HV, and V1 and V2 are respectively lower limit and the higher limit of the described booster voltage HV of setting.Described lower limit V1 can be arranged to and described target voltage V SetEquate, also can be arranged on described target voltage V SetCertain deviation within.In the present embodiment, described lower limit V1 is set to described target voltage V SetEquate.Described higher limit V2 is greater than described lower limit V1, and differs predetermined value, and the span of described predetermined value is 0.2V to 1.6V.Described target voltage V Set, lower limit V1 and higher limit V2 can set according to particular circuit configurations and device property, in the present embodiment, described lower limit V1 is set to and described target voltage V SetEquate that be 8V, described higher limit V2 is set to 8.5V, then described predetermined value is 0.5V.
With reference to the circuit of figure 4, after the value of the lower limit V1 of described booster voltage HV and described higher limit V2 is determined, just can determine described the first reference voltage V REF1With described the second reference voltage V REF2Value be respectively 0.8V and 0.85V.
After supposing that charge pump circuit starts, the booster voltage HV of described boosting unit 22 outputs is at t 0Constantly reach lower limit V1(that is described target voltage V Set).Be higher than described lower limit V1 at described booster voltage HV, when being lower than described higher limit V2,24 couples of described booster voltage HV of described partial pressure unit carry out dividing potential drop, export described branch pressure voltage VD greater than described the first reference voltage V REF1And less than described the second reference voltage V REF2, described the first comparative result FB1 and the described second comparative result FB2 of described the first comparing unit 25 and 26 outputs of described the second comparing unit are low level.Because the signal of the described rest-set flip-flop A3 set end S of input and reset terminal R is low level, the state of described rest-set flip-flop A3 remains unchanged, and namely the control level FB of described status unit 27 outputs makes the driving voltage V of described clock driver element 21 outputs DRVBe the rectilinear oscillation signal, control described boosting unit 22 and continue to boost.
Described booster voltage HV continues to rise, and when surpassing the higher limit V2 of described booster voltage HV, 24 couples of described booster voltage HV of described partial pressure unit carry out dividing potential drop, export described branch pressure voltage VD greater than described the first reference voltage V REF1With described the second reference voltage V REF2, the described first comparative result FB1 of described the first comparing unit 25 outputs is low level, the described second comparative result FB2 of described the second comparing unit 26 outputs is high level.Because the signal of the described rest-set flip-flop A3 set end S of input is low level, the signal of input reset terminal R is high level, the output Q output low level of described rest-set flip-flop A3, and namely the control level FB of described status unit 27 outputs is low level.Described clock driver element 21 is answered the failure of oscillations, exports invalid driving signal.Since path delay, the driving voltage V of described clock driver element 21 outputs DRVStill can keep the rectilinear oscillation signal of a period of time, described booster voltage HV can continue to rise to maximum V Max
After described clock driver element 21 failures of oscillations, described boosting unit 22 no longer continues to boost, and described booster voltage HV can progressively reduce along with the load consumed current of charge pump circuit.When described booster voltage HV was low to moderate less than described higher limit V2 greater than described lower limit V1,24 couples of described booster voltage HV of described partial pressure unit carried out dividing potential drop, export described branch pressure voltage VD greater than described the first reference voltage V REF1And less than described the second reference voltage V REF2, described the first comparative result FB1 and the described second comparative result FB2 of described the first comparing unit 25 and 26 outputs of described the second comparing unit are low level.Because the signal of the described rest-set flip-flop A3 set end S of input and reset terminal R is low level, the state of described rest-set flip-flop A3 is constant, and namely the control level FB of described status unit 27 outputs makes the driving voltage V of described clock driver element 21 outputs DRVStill be invalid driving signal, control described boosting unit 22 and stop to boost.
When described booster voltage HV is reduced to when being lower than described lower limit V1,24 couples of described booster voltage HV of described partial pressure unit carry out dividing potential drop, export described branch pressure voltage VD less than described the first reference voltage V REF1With described the second reference voltage V REF2, the described first comparative result FB1 of described the first comparing unit 25 outputs is high level, the described second comparative result FB2 of described the second comparing unit 26 outputs is low level.Because the signal of the described rest-set flip-flop A3 set end S of input is high level, the signal of input reset terminal R is low level, the output Q output high level of described rest-set flip-flop A3, and namely the control level FB of described status unit 27 outputs is high level.Described clock driver element 21 will be exported the rectilinear oscillation signal again.Because path delay, must be after after a while, described control level FB could wake clock driver element 21 up, and the driving voltage that clock driver element 21 is produced is the rectilinear oscillation signal by invalid driving signal transition.Therefore, described booster voltage HV is owing to the load consumed current of charge pump circuit continues to be reduced to minimum value V MinAfterwards, described clock driver element 21 restarts vibration and output rectilinear oscillation signal, re-starts boost action to control described boosting unit 22.To t 1Constantly, through a work period, described booster voltage HV reaches described lower limit V1 again, and charge pump circuit repeats the above-mentioned course of work.
Need to prove, behind described voltage-adjusting unit 23 shaping filters of booster voltage HV process of described boosting unit 22 outputs, stable output voltage V EPCarry out writing of information and read operation for memory.Because described boosting unit 22 has carried out boosting for twice, described booster voltage HV correspondingly improves, therefore, and by adjusting the circuit elements device parameters in the described voltage-adjusting unit 23, such as the resistance of divider resistance R, the appearance value of filter capacitor C etc. makes the described burning voltage V of output EPThe program voltage that still needs for memory.
The charge pump circuit that technical solution of the present invention provides, after described booster voltage reached target voltage, described clock driver element did not have the failure of oscillations, but continued output rectilinear oscillation signal, controlled described boosting unit and again boosted.Utilize to lengthen the time that discharges and recharges of electric capacity in the described boosting unit, increase the work period of charge pump circuit, reduce number of times that described clock driver element is waken up to reduce the power consumption of charge pump circuit.Particularly.The power consumption of charge pump circuit can be divided into two parts: the power loss C*(V when being the capacitor charging of giving in the process of boosting in the described boosting unit Max-V Min), C represents the appearance value of charging capacitor, (V Max-V Min) the expression charging voltage; Another is the power loss Pw of described clock driver element when at every turn being waken up.The work period of described charge pump circuit is expressed as T, and then the average power consumption of charge pump circuit in a work period T is [C*(V Max-V Min)+Pw]/T.Compared with prior art, technical solution of the present invention has increased charging voltage (V Max-V Min), suppose that charging voltage in the technical program is 4 times of charging voltage in the prior art, the work period of charge pump circuit is the approximate 4T that becomes correspondingly, and then the average power consumption of charge pump circuit becomes and is [C*(V in a work period T Max-V Min)+Pw/4]/T, namely the power loss during capacitor charging is constant, and the power loss Pw when described clock driver element is waken up at every turn is reduced to original 1/4.
Embodiment 2
Figure 6 shows that the structure chart of the embodiment of the invention 2 charge pump circuits.With reference to figure 2, the embodiment 2 of charge pump circuit of the present invention is roughly the same with the circuit structure of embodiment 1, and its difference is: described the first branch pressure voltage V D1With described the second branch pressure voltage V D2Two different voltages that described partial pressure unit 24 provides.With reference to the circuit of figure 6, after the value of the lower limit V1 of described booster voltage HV and higher limit V2 is determined, just can determine described the first reference voltage V REF1With described the second reference voltage V REF2Value be respectively 0.8V and 1.7V.
The operation principle of the charge pump circuit of embodiment 2 and embodiment 1 are identical, do not repeat them here.
Embodiment of the present invention also provides a kind of memory, comprises the charge pump circuit that above-described embodiment 1 or embodiment 2 provide.
In sum, the charge pump circuit that technical solution of the present invention provides carries out twice charging by the control boosting unit, increases the work period of charge pump circuit, with the number of times that minimizing clock driver element is waken up, has reduced the power loss of charge pump circuit.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.

Claims (11)

1. charge pump circuit comprises: the clock driver element is used for outputting drive voltage; Boosting unit, according to the driving voltage booster tension of described clock driver element output, the output booster voltage; Voltage-adjusting unit, the booster voltage that described boosting unit is exported carries out shaping and dividing potential drop, stable output voltage;
It is characterized in that, also comprise:
Partial pressure unit is used for described booster voltage is carried out dividing potential drop, exports the first branch pressure voltage and the second branch pressure voltage;
The first comparing unit is used for described the first branch pressure voltage and the first reference voltage are compared, and exports the first comparative result;
The second comparing unit is used for described the second branch pressure voltage and the second reference voltage are compared, and exports the second comparative result;
Status unit is used for exporting control level to described clock driver element according to described the first comparative result and described the second comparative result, controls described clock driver element and exports described driving voltage.
2. charge pump circuit according to claim 1 is characterized in that, described the first reference voltage and described the second reference voltage determine that according to lower limit and the higher limit of described booster voltage described lower limit is less than described higher limit and differ predetermined value respectively.
3. charge pump circuit according to claim 2 is characterized in that, the span of described predetermined value is 0.2V to 1.6V.
4. charge pump circuit according to claim 1 is characterized in that, described the first reference voltage and described the second reference voltage are provided by band gap reference.
5. charge pump circuit according to claim 1 is characterized in that, described the first branch pressure voltage and described the second branch pressure voltage equate that described the first reference voltage is less than described the second reference voltage.
6. charge pump circuit according to claim 1 is characterized in that, described the first branch pressure voltage is less than described the second branch pressure voltage, and described the first reference voltage is less than described the second reference voltage.
7. charge pump circuit according to claim 1 is characterized in that, described the first comparing unit comprises the first comparator, and its anode is inputted described the first reference voltage, and negative terminal is inputted described the first branch pressure voltage.
8. charge pump circuit according to claim 1 is characterized in that, described the second comparing unit comprises the second comparator, and its anode is inputted described the second branch pressure voltage, and negative terminal is inputted described the second reference voltage.
9. charge pump circuit according to claim 1 is characterized in that, described status unit is trigger.
10. charge pump circuit according to claim 9 is characterized in that, described trigger is rest-set flip-flop, and its set end is inputted described the first comparative result, and reset terminal is inputted described the second comparative result, and output is exported described control level.
11. a memory is characterized in that, comprises each described charge pump circuit of claim 1 to 10.
CN2012104727590A 2012-11-20 2012-11-20 Charge pump circuit and storage Pending CN102938610A (en)

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CN104460821A (en) * 2013-09-12 2015-03-25 爱思开海力士有限公司 Internal voltage generation circuits and semiconductor devices including the same
CN104615183A (en) * 2014-12-30 2015-05-13 上海华虹宏力半导体制造有限公司 Operating voltage control circuit and method and memorizer

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JP2004248475A (en) * 2003-02-17 2004-09-02 Fujitsu Ltd Charge pump circuit with reduced amplitude of step-up voltage
CN101621248A (en) * 2008-07-02 2010-01-06 登丰微电子股份有限公司 DC to DC converting circuit and controller thereof
US7764526B1 (en) * 2006-10-18 2010-07-27 Intersil Americas Inc. Hysteretic mode controller for capacitor voltage divider
CN101888180A (en) * 2010-07-16 2010-11-17 上海宏力半导体制造有限公司 Output voltage regulator circuit of charge pump
CN101894586A (en) * 2010-07-30 2010-11-24 上海宏力半导体制造有限公司 Programming voltage compensation circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004248475A (en) * 2003-02-17 2004-09-02 Fujitsu Ltd Charge pump circuit with reduced amplitude of step-up voltage
US7764526B1 (en) * 2006-10-18 2010-07-27 Intersil Americas Inc. Hysteretic mode controller for capacitor voltage divider
CN101621248A (en) * 2008-07-02 2010-01-06 登丰微电子股份有限公司 DC to DC converting circuit and controller thereof
CN101888180A (en) * 2010-07-16 2010-11-17 上海宏力半导体制造有限公司 Output voltage regulator circuit of charge pump
CN101894586A (en) * 2010-07-30 2010-11-24 上海宏力半导体制造有限公司 Programming voltage compensation circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104460821A (en) * 2013-09-12 2015-03-25 爱思开海力士有限公司 Internal voltage generation circuits and semiconductor devices including the same
CN104615183A (en) * 2014-12-30 2015-05-13 上海华虹宏力半导体制造有限公司 Operating voltage control circuit and method and memorizer
US9564886B2 (en) 2014-12-30 2017-02-07 Shanghai Huahong Grace Semiconductor Manufacturing Corporation Circuit and method for controlling operation voltage, and storage device

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